XIAMEN OCULAR OPTICS GDM12864HLCM User manual

User’s Guide
GDM12864HLCM
(Liquid Crystal Display Module)
For product support, contact
XIAMEN OCULAR OPTICS CO.,LTD.
厦门高卓立光电有限公司
South2/F.,Guangxia Building Torch Hi-tech
Industrial Development Area Xiamen, China
36100 中国厦门火炬高技术产业开发区光厦楼南二楼
Tel: [phone] Fax: [phone]

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CONTENTS
Mechanical diagram
Absolute maximum ratings
Interface pin connections
Optical characteristics
Electrical characteristics
KS0107B
KS0108B
Write or read cycle
Timing characteristics
Block diagram
Display commands
Reliability and lift time
Operating Principles & Methods

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ØMechanical diagram
ØAbsolute maximum ratings
Item Symbol Min. Max. Unit
Supply voltage for logic Vdd -Vss 0 6.5
Input voltage Vin 0 Vdd V
Operating temperature range T0p -20 70
Storage temperature range Tst -25 75
ØInterface pin connections
Pin No. Symbol Level Description
1 Vdd 5.0V Supply voltage for logic and LCD (+)
2 Vss0V Ground
3 V0 -Operating voltage for LCD (variable)
4~11 DB0~DB7 H/L Data bit 0~7
12 CS2 LChip select signal for IC2
13 CS1 LChip select signal for IC1
14 /RES LReset signal
15 R/W H/L H: read (MUP< module),L: write (MPU >module)
16 D/I H/L H: data, L: instruction code
17 EH, HL Chip enable signal
18 VEE -Operating voltage for LCD (variable)
19 A4.2V Backlight power supply
20 K0V Backlight power supply

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ØOptical characteristics
STN Type display module (Ta=25 , Vdd=5.0V)
Item Symbol Condition Min. Typ. Max. Unit
-60 -35
Viewing angle фCr 2 -40 -40 deg
Contrast ratio (rise) Cr -6 -
Response time (fall) Tr --150 250 ms
Tr --150 250 ms
ØElectrical characteristics
Standard value
Item Symbol Condition Min. Typ. Max. Unit
Logic Vdd -Vss -4.75 5.0 5.25
Supply voltage for LCD Vdd-V0 --9.5 -V
Logic Idd --2.5 -
Supply current for LCD Iee --1.0 -mA
----
25 -9.5 -
Operating voltage for LCD
(Recommended) Vdd-v0 ----
H: level Vih High level 0.7Vdd -Vdd
Input voltage L: Level Vil Low level 0 -0.3Vdd
V
Electrical Absolute Maximum Ratings (KS0107B)
Parameter Symbol Rating Unit Note
Operating voltage VDD -0.3 ~ +7.0 V*1
Supply voltage VEE VDD-19.0 ~ VDD+0.3 V*4
VB-0.3 ~ VDD+0.3 V*1,2Driver supply voltage VLCD VEE-0.3 ~ VDD+0.3 V*3,4
*Notes:
*1. Based on VSS = 0V
*2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and V5L)
*3. Applies to V0L, V1L, V4L, and V5L.
*4. Voltage level: VDD V0 V1 V2 V3 V4 V5 VEE

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DC Electrical Characteristics (KS0107B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85 )
Item Symbol Condition Min. Typ. Max. Unit Note
Operating voltage VDD -4.5 -5.5
VIH -0.7VDD -VDD
Input voltage VIL -VSS -0.3VDD *1
VOH IOH= -0.4mA VDD-0.4 --
output voltage VOL IOL= 0.4mA --0.4
V
*2
Input leakage current ILKG VIN= VDD ~ VSS -1.0 -+1.0 µA*1
OSC Frequency fosc Rf=47k 2%
Cf=20pF 5% 315 450 585 kHz
On Resistance
(Vdiv-Ci) RONS VDD-VEE=17V Load current 150µA--1.5 k
IDD1 Master mode
1/128 Duty --1.0 *3
Operating current IDD2 Master mode
1/128 Duty --0.2 *4
Supply Current IEE Master mode
1/128 Duty --0.1
mA
*5
Operating
fop1 Master mode External Duty 50 - 600
Frequency fop2 Slave mode 0.5 -1500 kHz
Notes
*1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2,
M, and CL2 in the input state.
*2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M, and CL2 in the
output state.
*3. This value is specified about current flowing through VSS.
Internal oscillation circuit: Rf=47k , cf=20pF
Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load.
*4. This value is specified about current flowing through VSS.
Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS
and CL2, M, DIO1 is external clock.
*5. This value is specified about current flowing through VEE, Don’t connect to VLCD (V1~V5).

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Electrical Absolute Maximum Ratings (KS0108B)
Parameter Symbol Rating Unit Note
Operating voltage VDD -0.3 ~ +7.0 V*1
Supply voltageVEE VDD-19.0 ~ VDD+0.3 V*4
VB-0.3 ~ VDD+0.3 V*1,3Driver supply voltage VLCD VEE-0.3 ~ VDD+0.3 V*2
*Notes:
*1. Based on VSS = 0V
*2. Applies the same supply voltage to VEE. VLCD=VDD-VEE.
*3. Applies to M, FRM, CLK1, CLK2, CL, RESETB, ADC, CS1B, CS2B, CS3, E, R/W, RS and
DB0~DB7.
*4. Applies V0L, V2L, V3L and V5L.
Voltage level: VDD V0 V1 V2 V3 V4 V5 VEE
DC Electrical Characteristics (KS0108B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85 )
Item Symbol Condition Min. Typ. Max. Unit Note
Operating voltageVDD -4.5 -5.5
VIH1 -0.7VDD -VDD *1
Input High voltage VIH2 -2.0 -VDD *2
VIL1 -0-0.3VDD *1
Input Low voltage VIL2 -0-0.8 *2
Output High Voltage VOH IOH= -0.2mA 2.4 --*3
Output Low Voltage VOL IOL= 1.6mA --0.4
V
*3
Input leakage current ILKG VIN= VSS ~ VDD -1.0 -+1.0 µA*4
Three-state (OFF)
Input Current ITSL VIN= VSS ~ VDD -5.0 -5.0 *5
Driver Input leakage
current IDIL VIN= VEE ~ VDD -2.0 2.0 *6
On Resistance
(Vdiv-Ci) RONS VDD-VEE=15V Load current 100µA--7.5 k*8
IDD1 During Display --0.1 *7
Operating current IDD2 During Access
Access Cycle=1MHz --0.5 mA *7
Notes
*1. CL, FRM, M, RSTB, CLK1, CLK2
*2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7
*3. DB0~DB7
*4. Except DB0~DB7
*5. DB0~DB7 at high impedance
*6. V0, V1, V3, V3, V4, V5
*7. 1/64 duty, FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load
*8. VDD-VEE=15.5V
V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L

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ØWrite or read cycle
Characteristic Symbol Min. Typ. Max. Unit
E cycle Tc 1000 --ns
E high level width Twh 450 --ns
E low level width Twl 450 --ns
E rise time Tr --25 ns
E fall time Tf --25 ns
Address set-up time Tasu 140 --ns
Address hold time Tah 10 --ns
Data set-up time Tdsu 200 --ns
Data delay time Td --320 ns
Data hold time (write) Tdhw 10 --ns
Data hold time (read) Tdhr 20 --ns
²Write timing
tDSU tDHW
tASU
tASU
tAH
tAH
tRtF
tWL
tWH
tC
DB0~DB7
CS1,CS2
CS,RS
R/W
E
MPU Write timing

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²Read timing
tWL tC
tFtR
tAH
tAH
tASU
tASU
tWH
tD
tWH
MPU Read timing
DB0~DB7
CS1,CS2
CS,RS
R/W
E

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²Block diagram
VDD-Vo:LCD DRIVING VOLTAGE
VSS
VR:10K~20K
VEE
VDD
Vo
LCM
VEE
/RET
VDD
VSS
DB0~DB7
R/W E
A
K
CS
RS 3
8
V0
IC3
GND
VR
3
SEG65~128
83 5
58
LED BACKLIGHT MODULE
+5V
IC1
SEG1~64
IC2
LCD PANEL
COM 1~64
IC4
*Note
1/64 duty, 1/9 bias
VDD>V1>V2>V3>V4>V5>VEE

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²Display Control Instruction
The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to
KS0108B for the display control. The following table shows various instructions.
Instruction RSRW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function
Read Display
Data 1 1 Read data Reads data (DB[7:0])from
display data RAM to the
data bus.
Write Display
Data 1 0 Write data
Writes data (DB[7:0]) into
display data RAM. After
writing instruction, Y
address is incriminated by
1 automatically
Status Read 0 1 Busy 0 ON/
OFF Re- set 0 0 0 0
Reads the internal status
BUSY
0: Ready
1: In operation
ON/OFF
0: Display ON
1: Display OFF
RESET
0: Normal
1: Reset
Set Address
(Y address) 0 0 0 1 Y address (0~63) Sets the Y address in the Y address counter
Set Display
Start Line 0 0 1 1 Display start line (0~63) Indicates the display data
RAM displayed at the top
of the screen.
Set Address
(X address) 0 0 1 0 1 1 1 Page (0~7) Sets the X address at the X address register.
Display On/off 0 0 0 0 1 1 1 1 1 0/1
Controls the display ON or
OFF. The internal status
and the DDRAM data is
not affected.
0: OFF, 1: ON
1. Display On/Off
The display data appears when D is 1 and disappears when D is 0.
Though the data is not on the screen with D=0, it remains in the display data RAM.
Therefore, you can make it appear by changing D=0 into D=1.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000011111D
2. Set Address (Y Address)
Y address (AC0~AC5) of the display data RAM is set in the Y address counter.
An address is set by instruction and increased by 1 automatically by read or write operations of display
data.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0001AC5 AC4 AC3 AC2 AC1 AC0

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3. Set Page (X Address)
X address (AC0~AC2) of the display data RAM is set in the X address register.
Writing or reading to or from MPU is executed in this specified page until the next page is set.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0010111AC2 AC1 AC0
4. Display Start Line (Z Address)
Z address (AC0~AC5) of the display data RAM is set in the display start line register and displayed at the
top of the screen.
When the display duty cycle is 1/64 or others (1/32~1/64), the data of total line number of LCD screen,
from the line specified by display start line instruction, is displayed.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011AC5 AC4 AC3 AC2 AC1 AC0
5. Status Read
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10BUSY 0ON/OFF RESET 0000
lBUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
lON/OFF
When ON/OFF is 1, the display is on.
When ON/OFF is 0, the display is off.
lRESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
6. Write Display Data
Writes data (D0~D7) into the display data RAM.
After writing instruction, Y address is increased by 1 automatically.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
10D7 D6 D5 D4 D3 D2 D1 D0
7. Read Display Data
Reads data (D0~D7) from the display data RAM.
After reading instruction, Y address is increased by 1 automatically.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
11D7 D6 D5 D4 D3 D2 D1 D0

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²Operating principles & methods
1. I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active
mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But
RSTB and ADC can operate regardless CS!B-CS3.
2. Input register
Input register is provided to interface with MPU which is different operating frequency. Input register stores
the data temporarily before writing it into display RAM.
When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is
written into input register. Then writing it into display RAM. Data latched for falling of the E signal and
write automatically into the display data RAM by internal operation.
3. Output register
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active
mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3
is in active mode and R/W=H , RS=L, status data (busy check) can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in
display data RAM is latched into output register. In second access, MPU can read data which is latched. That
is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read.
RS R/W Function
LInstruction
LHStatus read (busy check)
LData write (from input register to display data RAM )
HHData read (from display data RAM to output register)
4. Reset
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving
instruction from MPU. When RSTB becomes low, following procedure is occurred.
1. Display off
2. Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions
after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction.
The conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item Symbol Min Typ Max Unit
Reset Time tRS 1.0 --us
Rise Time tR--200 ns
0.3VDD
0.7VDD
V
DD
RSTB
tR
tRS
4.5[V]

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5. Busy flag
Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in
internal operating .
When busy flag is low, KS0108B can accept the data or instruction.
DB7indicates busy flag of the KS0108B.
Busy Flag
E
TBusy
f
C
L
K
isCLK1, CLK2 Frequency
1/f
C
L
K
<TBusy<3/f
C
L
K
6. Display On/Off Flip-Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low),
selective voltage or non-selective voltage appears on segment output terminals. When flip-flop is set (logic
high), non selective voltage appears on segment output terminals regardless of display RAM data.
The display on/off flip-flop can changes status by instruction. The display data at all segments disappear
while RSTB is low.
The status of the flip-flop is output to DB5 by status read instruction.
The display on/off flip-flop synchronized by CL signal.
7. X Page Register
X page register designates pages of the internal display data RAM.
Count function is not available. An address is set by instruction.
8. Y address counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and
is increased by 1 automatically by read or writes operations of display data.
9. Display Data RAM
Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid
crystal display, write datra1. The other way, off state, writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
ADC=H => Y-address 0: S1~Y address 63: S64
ADC=L => Y-address 0: S64~Yaddress 63: S1
ADC terminal connect the VDD or VSS.
10. Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display.
Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register. Latched
data is transferred to the Z address counter while FRM is high, presetting the Z address counter.
It is used for scrolling of the liquid crystal display screen.