ABA VMIVME-1184 Series Quick user guide

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Hardware Reference Manual
VMIVME-1184* 32-bit Optically Isolated
Change-of-State (COS) Input Board with
Sequence-of-Events (SOE)
Publication No. 500-001184-000 Rev. B.0
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2 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
Document History
Waste Electrical and Electronic Equipment (WEEE) Returns
Revision Date Description
A.0 May 2010 Hardware Reference Manual
B.0 October 2016 Reformatted
Abaco Systems is registered with an approved Producer Compliance Scheme (PCS) and, subject
to suitable contractual arrangements being in place, will ensure WEEE is processed in accordance
with the requirements of the WEEE Directive.
Abaco Systems will evaluate requests to take back products purchased by our customers before
August 13, 2005 on a case-by-case basis. A WEEE management fee may apply.
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Publication No. 500-001184-000 Rev. B.0 About This Manual 3
About This Manual
Conventions
Notices
This manual may use the following types of notice:
WARNING
Warnings alert you to the risk of severe personal injury.
CAUTION
Cautions alert you to system danger or loss of data.
NOTE
Notes call attention to important features or instructions.
TIP
Tips give guidance on procedures that may be tackled in a number of ways.
LINK
Links take you to other documents or websites.
Numbers
All numbers are expressed in decimal, except addresses and memory or register
data, which are expressed in hexadecimal. Where confusion may occur, decimal
numbers have a “D” subscript and binary numbers have a “b” subscript. The
prefix “0x” shows a hexadecimal number, following the ‘C’ programming
language convention. Thus:
One dozen = 12D= 0x0C = 1100b
The multipliers “k”, “M” and “G” have their conventional scientific and
engineering meanings of x103, x106and x109respectively. The only exception to
this is in the description of the size of memory areas, when “k”, “M” and “G”
mean x210, x220 and x230 respectively.
NOTE
When describing transfer rates, “k”, “M” and “G” mean x103, x106and x109not x210, x220 and x230.
In PowerPC terminology, multiple bit fields are numbered from 0 to n where 0 is
the MSB and n is the LSB. PCI terminology follows the more familiar convention
that bit 0 is the LSB and n is the MSB.
Text
Signal names ending with a tilde (“~”) denote active low signals; all other signals
are active high. “N” and “P” denote the low and high components of a differential
signal respectively.
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4 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
Further Information
Abaco Website
You can find information regarding Abaco products on the following website:
LINK
www.abaco.com
Abaco Documents
This document is distributed via the Abaco website. You may register for access
to manuals via the website.
LINK
www.abaco.com/products/
Third-party Documents
For a detailed explanation of the VMEbus and its characteristics, refer to ʺThe
VMEbus Specificationʺavailable from:
VITA
VMEbus International Trade Association
7825 East Gelding Dr., No. 104
Scottsdale, AZ 85260
[phone]
FAX: [phone]
www.vita.com
NOTE
Technical literature describing components used on the VME-1184 is available from the manufacturers’
websites.
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Publication No. 500-001184-000 Rev. B.0 About This Manual 5
Technical Support Contact Information
You can find technical assistance contact details on the website Embedded
Support page.
LINK
www.abaco.com/embedded-support
Abaco will log your query in the Technical Support database and allocate it a
unique Case number for use in any future correspondence.
Alternatively, you may also contact Abaco’s Technical Support via:
LINK
[email protected]
Returns
If you need to return a product, there is a Return Materials Authorization (RMA)
form available via the website Embedded Support page.
LINK
www.abaco.com/embedded-support
Do not return products without first contacting the Abaco Repairs facility.
Additional Notes
The VMIVME-1184* is a 32-channel P2 input board with Change-of-State (COS)
and interrupt capabilities. The interrupt control logic can be programmed to issue
an interrupt for specific state changes. The user selects the state changes to detect
by programming the Control and Status Register (CSR1) and the COS Select
register. This board stores up to 512 state changes when the COS logic is enabled.
This prevents the board from losing a state change during interrupt servicing. For
SOE operation, a maximum of 256 state changes are stored. The board also
supports byte, word and longword data transfers during basic input data
operations.
Features
The following is a list of some of the features of the VMIVME-1184:
• 32 channels of optically-isolated digital inputs with transient voltage
suppression
• Eight inputs are grouped together and called an input port. Each port can be
configured by the user to monitor one of the following output circuits:
• — Current sinking (Contact Closure)
• — Voltage sourcing (Voltage Sensing)
• User-configurable input voltage thresholds on a two channel basis
• Each channel has over-voltage and reverse voltage protection
• Reverse voltage is indicated by surface mounted SOT23 LEDs
• Incoming data is available for direct VMEbus read cycles
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6 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
• Data can be read using 8-, 16-, or 32-bit data transfers
• Each channel can be independently set by the user to perform the following
functions:
– Per channel COS event storage configuration
– Ignore all changes (no events stored due to this channel changing)
– Rising edge (causes 32 channel event storage into FIFO)
– Falling edge (causes 32 channel event storage into FIFO)
– Any edge (causes 32 channel event storage into FIFO)
• Each channel can be set to generate an interrupt for each event
• Sequence of Events logging with optional counter stamping
• Differential or Single-Ended inputs and outputs for Quadrature Counter (A,
B and Marker/Index) with daisy-chaining capability
• This board complies with the VMEbus Specification Rev. C.1
• The board can be set to respond to short I/O (16-bit) accesses or to standard
data I/O (24-bit) accesses
• AM2 setting for supervisor, non-privileged or both VMEbus accesses
Functional Description
The VMIVME-1184 is an optically isolated digital input board with 32 user-
configurable channels. The inputs can be set up to monitor either voltage sensing
or contact closure. Once the hardware has been configured and installed in the
system, you can start monitoring the circuits. The data ports are always available
for VMEbus data transfers. Simply read the address of the specific port, and
record the state of the external circuits. This data is available in byte, word or
longword accesses.
The board can be programmed to interrupt the system based on a change in the
inputs. Change-of-State (COS) circuitry monitors the logical state of the inputs.
When an input channel changes its state (for example, from a logic one to a logic
zero), and the COS logic is set to trigger on that event, an interrupt can be issued
to the host CPU. The COS logic is programmed via the Control and Status
Register to store an event for certain conditions, such as the falling edge described
above, and is channel specific.
The board is also capable of recording Sequence of Events (SOE). In this mode,
when a specified change of state occurs on any of the channels, the previous state
of all 32 channels is stored in the FIFO, followed by the current state. Additionally,
a counter value incremented/decremented from the front panel counter input is
stored in a separate FIFO to give the SOE an optional time stamp. The counter
feature is also available in COS mode.
The VMIVME-1184 stores state changes in an on-board FIFO. The board can be
configured to clear an interrupt request when the FIFO is empty (ROFE), or when
an interrupt has been acknowledged (ROAK). If a COS occurs while a previous
COS is waiting for service, or during the interrupt service routine, the event will
be saved.
NOTE
COS mode only stores the events which have been triggered by certain changes on certain channels
(user configured).
SOE mode additionally stores the latched state of the 32 channels just prior to each event which triggers
a data storage into the FIFO (only one time stamp per pair).
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Publication No. 500-001184-000 Rev. B.0 About This Manual 7
Safety Summary
The following general safety precautions must be observed during all phases of
the operation, service, and repair of this product. Failure to comply with these
precautions or with specific warnings elsewhere in this manual violates safety
standards of design, manufacture and intended use of this product.
Abaco assumes no liability for the customerʹs failure to comply with these
requirements.
Ground the System
To minimize shock hazard, the chassis and system cabinet must be connected to
an electrical ground. A three-conductor AC power cable should be used. The
power cable must either be plugged into an approved three-contact electrical
outlet or used with a three-contact to two-contact adapter with the grounding
wire (green) firmly connected to an electrical ground (safety ground) at the power
outlet.
Do Not Operate in an Explosive Atmosphere
Do not operate the system in the presence of flammable gases or fumes. Operation
of any electrical system in such an environment constitutes a safety hazard.
Keep Away from Live Circuits
Operating personnel must not remove product covers. Component replacement
and internal adjustments must be made by qualified maintenance personnel. Do
not replace components with power cable connected. Under certain conditions,
dangerous voltages may exist even with the power cable removed. To avoid
injuries, always disconnect power and discharge circuits before touching them.
Do Not Service or Adjust Alone
Do not attempt internal service or adjustment unless another person, capable of
rendering first aid and resuscitation, is present.
Do Not Substitute Parts or Modify System
Because of the danger of introducing additional hazards, do not install substitute
parts or perform any unauthorized modification to the product. Return the
product to Abaco for service and repair to ensure that safety features are
maintained.
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8 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
Table of Contents
1 • Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2 VMEbus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2.1 Data Transfer Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2.2 Interrupt Acknowledge Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 Register Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4 Debounce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5 Change-of-State Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.1 Previous State Data Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.2 “Simultaneous” Data Changes, and the Debounce “Stretching” Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.6 Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.6.1 Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.6.2 Contact Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2 • Configuration and Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2 Unpacking Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.3 Physical Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.3.1 Before Applying Power: Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.4 Operational Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.1 Factory Installed Switches/Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.2 Board Address and Address Modifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.3 Debounce Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.5 Input Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.6 Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.6.1 Barrier Terminal Transition Panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3 • Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.1.1 Board ID (BD ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2 Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2.1 CSR1 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.2.2 CSR2 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2.3 Counter Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.4 Quadrature Counter Decoder Bits (Bits 16, 17 and 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.5 Encoder Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3 Data FIFO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.4 Interrupt Processor Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.4.1 Interrupt Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Interrupt Processor COS Vector Register (Offset: $XXXX0D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6 Interrupt Processor Marker Vector Register (Offset: $XXXX0E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.7 Counter FIFO Register (Offset: $XXXX10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.7.1 Counter Register (Offset: $XXXX14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.7.2 COS SEL B/A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7.3 COS Select Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.4 COS Select Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.5 COS Select Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.6 COS Select Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Publication No. 500-001184-000 Rev. B.0 Table of Contents 9
3.7.7 FIFO Count Register (FIFO_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.8 Counter FIFO Count Register (CTR_FIFO_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8 Channel Interrupt Enable Register (CH_INT_ENA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.9 Firmware Revision Register (FREV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.10 Counter Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11.1 CSR1_[5, 4] Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11.2 2X Quadrature Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.3 4X Quadrature Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.12 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.13 VMIVME-1184 Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.14 Marker Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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10 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
List of Figures
Figure 1-1 VMIVME-1184 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 1-2 AM2 Line (Switch S29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1-3 Channels 1-30 Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 1-4 Channel 31 Input Circuitry (Channel 32 uses Vext #2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 2-1 Switch and Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2-2 P1/P2 Connector Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-1 COS and SOE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 3-2 Leading Edge Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3-3 1x Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3-4 2x Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3-5 2X Quadrature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3-6 4X Quadrature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3-7 Marker Gating Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Publication No. 500-001184-000 Rev. B.0 11
List of Tables
Table 1-1 COS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-2 Walking Ones Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-3 Contact Closure SIP Resistors and Switch Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2-1 Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2-2 Jumper E3 (Extended Debounce Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2-3 P1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2-4 P2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 3-1 VMIVME-1184 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 3-2 Board ID Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3-3 Control and Status Register 1 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3-4 Correlating Debounce Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3-5 Control and Status Register 2 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3-6 Data FIFO Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3-7 Interrupt Processor Control Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3-8 Interrupt Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 3-9 COS SEL B/A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3-10 COS Select Register 0 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3-11 COS Select Register 1 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3-12 COS Select Register 2 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3-13 COS Select Register 3 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3-14 FIFO Count Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3-15 Counter FIFO Count Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3-16 Channel Interrupt Enable Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3-17 Differential Termination (S28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3-18 Example Setup of the VMIVME-1184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3-19 Input Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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12 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
1 • Theory of Operation
1.1 Introduction
The board functions are broken down into six major blocks. These blocks are:
•Businterface
• Register decoder
• Interrupt Processor (IP)
• Change-of-State (COS) logic
• Input circuits
•Counter
The bus interface contains the VMEbus interface logic, the boardʹs address
decoding logic and the data steering logic. The register decoder selects which data
register (BD ID, CSR, IP or input) is used during a data transfer. The IP interface
contains the logic to control the IP, interfaces with the VMEbus and issues the
interrupt request. The COS logic controls the FIFO’s data flow, determines if a
change-of-state has occurred and whether it is deemed an event and stored. The
input circuits contain the hardware to configure the topology (the shape or type of
circuit), and their trigger thresholds.
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Publication No. 500-001184-000 Rev. B.0 Theory of Operation 13
Figure 1-1 VMIVME-1184 Block Diagram
During Data-Only operations, the board monitors the external circuitry. When the
boardʹs address decoder determines the board is being accessed, it clocks the
inputs into the data registers, effectively taking a snapshot of the external world.
The data is steered to the correct VMEbus data lines, DTACK* is asserted, and the
board re-arms its address decoder for another cycle. These types of transfers are
always available to the user and do not effect the COS or SOE logic.
During Interrupt Cycles, the Interrupt Processor (IP) handles the board’s
functionality. When the COS logic issues an interrupt request to the IP, it also
stores the incoming data in the associated FIFOs. The IP issues an interrupt
request to the host CPU and waits for the proper Interrupt Acknowledge cycle.
When the IP responds to the Acknowledge cycle, it places the user-programmed
vector for the Interrupt Service Routine (ISR) on the VMEbus.
1.2 VMEbus Interface
The bus interface logic consists of bus signal buffers and transceivers that meet
the VMEbus specification loading requirements. The address decoder (or board-
select logic) can respond to standard (24-bit) or short (16-bit) data I/O accesses.
The steering logic selects which VMEbus data lines to connect to the boardʹs
Internal Data Bus (IDB) and which direction the data will flow. The Board
Identification (BD ID) register, the Control and Status Register (CSR) and the COS
Select registers are considered part of the bus interface logic.
7
21
3
4
27
15
32
715
3
832
32
IDB
32
32
32
P2
Front
Panel
32-Bit
Counter
Board
Address
Selection
Address
Decode
Control
Logic
Data
Transceivers
Interrupt
Processor (IP)
COS
FIFOs
Debounce
Clock
COS
Detection
RS-422
Xcvr
Read Data
Registers
Input
Circuitry
VMEbus
32 User
Input Pairs
64
6
6
3 Differential Pairs
3 Differential Pairs
FPGA
Quadrature
Counter
Recovery
Opto
Isolation
Op
Amps
32
Front Panel
Status LEDs
64
(+) side used for
Single-Ended
Send/Receive
Broken
Wire
Detection
13
32
32
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14 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
1.2.1 Data Transfer Cycles
The Address switch (S12-1) establishes the upper address line decoding. If the
switch is On, the board will respond to standard accesses. If the switch is Off, the
board will respond to short accesses. The default configuration is standard
accesses.
The address decoder compares the 18 address lines (A06 through A23) and the six
address modifier lines (AM0 through AM5) with preset conditions. The address
lines, the STD(A24)/SHT(A16) CSR line and the AM2 line have switches that are
used to establish the base address of the board. When a switch is On, the
corresponding address line is compared to a logic zero (0). When the bus address
and the address modifier matches the preset address, the board will respond to
the bus cycle.
The AM2 line can be set to respond to a specific state (logic high or low) or to
either logic state. With the switch in the ALL position, the board will respond to
either Supervisory or Nonprivileged accesses. When set to the middle position,
the board will respond to Nonprivileged data accesses only. When set to
Supervisory, the board will respond to Supervisory accesses only. Refer to Figure
1-2.
Figure 1-2 AM2 Line (Switch S29)
When the decoder determines that the board is being accessed, the VMEbus state
is stored in a register and the BD_SEL lines are activated. The board-select line
clocks the input registers and records the state of the external circuits. The register
decoder uses the bus state information to put the proper data on the IDB, and to
energize the VMEbus interface data transceivers. The bus interface then issues
DTACK* and watches the Data Strobes (DS0* and DS1*). When both Data Strobes
are asserted high the decoder resets itself and waits for the next matching address.
The cycle then restarts.
1.2.2 Interrupt Acknowledge Cycles
During Interrupt Acknowledge (IACK*) cycles, only the three lowest address
lines are valid. They carry the interrupt level being acknowledged by the host
CPU, bypassing the address decoder and activating the IP. If the IP has an
interrupt pending, it places its vector on the bus and issues a DTACK*. If not, the
IP passes the IACKIN* signal to the IACKOUT* line.
If the interrupting FIFO is not empty after the interrupt service routine is read,
and ROFE is selected, the IP will not release the interrupt until the FIFO is empty.
When more than one longword of data is in the FIFO, multiple events may have
occurred before or after the event that generated the interrupt. If the FIFO gets
full, the state changes are occurring too fast for the system to handle. If COS
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Publication No. 500-001184-000 Rev. B.0 Theory of Operation 15
interrupts are enabled, a full FIFO will generate an interrupt with the same level
and vector as COS.
NOTE
If COS events come faster than the CPU can service, interrupt starvation will occur, keeping regular
programs from executing. Please keep this in mind when configuring your system. Be especially mindful
of completely emptying the FIFO(s) and limiting the capture of events to those which are actually
necessary for operation. You could easily setup a condition in which too many events are being stored
before an interrupt-generating event occurs..
1.3 Register Decoder
The register decoder uses the five lowest address lines and data strobes to select
which register is placed on the IDB. The decoder is used during any board access.
It uses a simple demultiplexer scheme. The address lines are decoded when the
board select lines are asserted. Based upon the address lines and the data strobes,
the proper register or registers are activated or clocked. A memory map showing
the relative addresses for each register is listed in Chapter 3, Programming of this
manual.
1.4 Debounce
The debounce clock is derived from the 16 MHz VMEbus system clock and is not
intended as a synchronizing clock. The debounce clock is started when a COS
condition is detected. This approach yields a lower latency with glitch-reduction
capability.
Debounce is used on inputs to reduce ‘glitches’, false data transitions or noise.
Typically, a state machine is used to transition with a clock of a particular rate or
frequency. If the data’s new state changes back, before two clock cycles, then that
transition is thrown away (the data is considered not to have changed) and the
input channel is resampled for any new changes.
All 32 data input channels are debounced (the debounce time is user-configurable
from 1µs to 10ms). None of the counter inputs are debounced in order to more
accurately track high-speed precision encoders, and to better handle an encoder
stopping on a transition when machine vibration causes small but high speed
movement back and forth across the same transition. The counter should never
accumulate, or lose counts when the encoder is simply vibrating.
NOTE
Although the counter inputs are not debounced, they do have a maximum input change rate of 100nsec.
If changes occur faster than 100nsec, then missed changes or counting errors may occur.
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16 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
1.5 Change-of-State Logic
The COS logic bases its actions on the state of its select lines A and B. These lines
are controlled by the COS register values. The states are listed in Table 1-1 below:
The COS logic writes data into a FIFO based on the board’s configuration. The
COS logic decides when to load data into the FIFO. If either select lines A or B are
set to ‘1’ and the corresponding event occurs on that channel, 32 channels of data
will be stored in the data FIFO. When select lines A or B are set to ‘00’, data
changes for that channel will not flag a COS event and no data is stored in the
FIFO. If interrupts are programmed and being serviced when a new event occurs,
the logic continues to load the new state into the FIFO. The FIFO stores the new
states until they are read by the host or the buffer becomes full.
1.5.1 Previous State Data Algorithm
The definition of previous state data is essential to a system that detects changes
of state. Since all incoming data is compared to the previous state, what this
previous state is and when it is stored is critical to the proper operation of the
COS state machine.
A flagged Change-Of-State (COS) event occurs when one or more input channel’s
state changes in a way that the VMIVME-1184 has been programmed to detect.
For example, if Channel 3 changes from a one (1) to a zero (0), and the COS Select
Register has been programmed to detect falling edges for Channel 3, then
Channel 3 causes a “flagged” COS event. A non-flagged COS event would occur if
the logic level on Channel 3 changed from a zero (0) to a one (1), with falling edge
detection enabled. Flagged COS data is the value of all of the input channels when
one or more “flagged” changes of state have occurred. Non-flagged COS data is
data for one or more channels that may have changed state, but are not flagged
for saving.
1.5.2 “Simultaneous” Data Changes, and the Debounce
“Stretching” Effect
A walking ones test is commonly used during design validation and product
testing. In this test, all input channels are set to zero (0), and a one (1) is written to
each successive channel in the following manner:
Table 1-1 COS Logic
SEL B SEL A COS Logic’s Action
0 0 COS, event not flagged
0 1 COS event flagged on rising edges only
1 0 COS event flagged on falling edges only
1 1 COS event flagged on any edge
Table 1-2 Walking Ones Test
State 0 00000000
State 1 00000001
State 2 00000010
State 3 00000100
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Publication No. 500-001184-000 Rev. B.0 Theory of Operation 17
During this test, two channels are actually changing value after State 1. In State 2,
channel 0 has changed from a 1 to a 0, and channel 1 has changed from a 0 to a 1.
Theoretically, these changes are simultaneous, and are viewed as a single COS
event. The following, factors can be introduced to make the arrival of signals on
different channels non-simultaneous:
• Comparators and Opto Couplers have different times on rising vs. falling
edges.
• Traces, both inside and outside of FPGAs, can have slightly different lengths.
• Cables between sensors and I/O boards may not have precisely matched
lengths.
If any of the above conditions occur, then data transmitted simultaneously on
two or more channels may not arrive simultaneously at the COS detection
circuitry.
The need for the COS inputs to be synchronized to a common clock also
aggravates this situation. If two incoming signals arrive as little as 2 nanoseconds
apart, the first signal may arrive prior to the synchronizing rising clock edge, and
the second signal may arrive after the rising clock edge. If this occurs, the skew
between the two signals is stretched to the period of the 16 MHz synchronizing
clock. The debounce circuitry is another factor that can skew simultaneous events.
Consider a situation where two incoming signals are skewed by one or more
synchronizing clock cycles, the synchronized incoming signals can encounter
another early-late condition (as was in the synchronizing clock) with the
debounce circuitry. With the COS detection and FIFO circuitry running at the
VMEbus clock rate, the first arriving signal will have been stored by the COS
circuit, in the COS FIFO before the second arriving signal has passed the
debounce circuitry. If the second signal is also flagged, the two COS events would
be stored in the COS FIFO instead of one. This “double-hit” COS event can show
what appears to be an invalid state condition.
Consider the following example:
1. Set Channel 5 for rising edge events and channel 4 to falling edge
2. Set the CSR to see SOE mode, the expected FIFO output is:
The actual FIFO output, due to skew introduced by cabling, synchronizing clock
skewing, and/or debounce skewing, may appear as follows:
Channel 5 Channel 4
Previous State 1 0 1
01 to 10 change occurs here
COS State 1 1 0
Channel 5 Channel 4
Previous State 1 0 1
01 to 10 change occurs here, but Channel 4 lags Channel 5 by 3nsec
(New data appears on Channel 5, but old data still lingers on Channel 4)
COS State 1 1 1
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18 VMIVME-1184* 32-bit Optically Isolated Change-of-State (COS) Input Board Publication No. 500-001184-000 Rev. B.0
The recovered COS FIFO data appears to have logically “anded”the previous
state, and the current state of COS State 1 and Previous State 2, while the correct
COS data does not appear until COS State 2. When viewed on a logic analyzer, the
incoming data skew may be as little as 3 or 4 nsec, but due to synchronizing clock
skew and the debounce skew, the saved COS sequence appears as two separate
events.
If the Channel 4 COS detection circuitry had not been set to detect falling edges, a
perceived erroneous result would still occur, but only Previous State 1 and COS
State 1 would have occurred. This would still leave the tester with the impression
that the values of the previous state (01) and final state (10) had somehow been
logically “Anded” together.
A better approach to a walking ones test would be to reset the input channels to
all zeros between walking a 1 from one channel to the next. This allows for the
various skews to settle, and still allows the tester to detect channel cross-talk,
which is one of the primary purposes of the walking ones testing.
Although the likelihood of problems being caused by this condition during “real
world” operation is remote, it is still a possibility. The programer and system
integrator should take this condition into consideration.
1.6 Inputs
The input circuit is easily configured by the user to be either Voltage Sensing or
Contact Closure. Figure 1-3, Channels 1-30 Input Circuitry on page 19 shows the
circuitry for input channels 1-30. For monitoring circuits which short the inputs,
use the Contact Closure input circuit. Otherwise use the Voltage Sensing circuit.
This can be configured differently for each bank of eight channels by inserting or
removing the SIP for that bank.
The user can configure a circuit to monitor various external voltage levels by
adjusting the position of the switch that controls the resistance of the input
voltage divider resistor Rs1. Also shown in Figure 1-3 is the voltage sensing input
circuit and the contact closure input topology. For monitoring closed contacts or
contacts-to-ground, use the contact closure input circuit configuration. To monitor
circuits which supply power, use the voltage sensing input configuration.
1.6.1 Voltage Sensing
When using the Voltage Sensing configuration, the factory-installed SIP must be
removed for that bank. Each of the 32 input channels can be set, in groups of two,
to a different voltage selection. For example, the signal levels for input 1 and 2
could be set to a voltage input sensitivity of 5V, while inputs 3 and 4 could be set
to 12V or 24/28V.
Channel 5 Channel 4
Previous State 2 1 1
COS State 2 1 0
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Publication No. 500-001184-000 Rev. B.0 Theory of Operation 19
1.6.2 Contact Closure
If the Contact Closure configuration is chosen, the user will need to insert a SIP
resistor (provided) and set the appropriate pull-up voltage using either 5V, 12V or
an external user-supplied voltage through contacts on channels 31 or 32.
NOTE
It is recommended that user supplied voltage not exceed 28V.
When using Contact Closure, all inputs for that group (1-8, 9-16, 17-24 or 25-32)
are required to be set to the same voltage sensitivity level using the Voltage
Selection switches. For example, to set the second bank (channels 9-16) for
Contact Closure, install a SIP resistor in socket E6, rotate switch S27 to the
preferred voltage, and set the four input sensitivity switches (S8, S9, S18 and S19)
for the same voltage as S27. As shown in Figure 1-4, Channel 31 Input Circuitry
(Channel 32 uses Vext #2) on page 20, inputs 31 and 32 can be sacrificed to provide
two external voltages (Vext1 and Vext2) to the pull-up SIP resistors.
CAUTION
User supplied voltages should not exceed 28V for normal operation.
Figure 1-3 Channels 1-30 Input Circuitry
Table 1-3 Contact Closure SIP Resistors and Switch Assignments
Channels SIP Resistor Socket Voltage Source Switch
1 through 8 E34 S28
9 through 16 E35 S27
17 through 24 E36 S26
25 through 32 E37 S25
P2
Rows
A&C
Pins 1-30
(Row A) High
(Row C) Low
Channels 1 - 30
TVS
Rs1
(Switch
selectable)
Dp
opto-isolator
Detection
x8 SIP
(socketed)
Vbank (1, 2, 3, 4)
EXT
#1 Ext
#2
+12
+5
Only inserted
for contact
sensing
R bank
(1, 2, 3 and 4) Rs2
Installing a SIP resistor converts a bank of eight (8) channels
from "Voltage Sense" to "Contact Sense"
Bank 1 = channels 1-8
Bank 2 = channels 9-16
Bank 3 = channels 17-24
Bank 4 = channels 25-32
Over Voltage
Protection
60V
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