Achronix Speedster7t GDDR6 User manual

www.achronix.com
Speedster7t GDDR6 User
Guide (UG091)
Speedster FPGAs

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Copyrights, Trademarks and Disclaimers
Copyright © 2019 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster,
and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other
trademarks are the property of their respective owners. All specifications subject to change without notice.
NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
However, Achronix Semiconductor Corporation does not give any representations or warranties as to the
completeness or accuracy of such information and shall have no liability for the use of the information contained
herein. Achronix Semiconductor Corporation reserves the right to make changes to this document and the
information contained herein at any time and without notice. All Achronix trademarks, registered trademarks,
disclaimers and patents are listed at http://www.achronix.com/legal.
Achronix Semiconductor Corporation
2903 Bunker Hill Lane
Santa Clara, CA 95054
USA
Website: www.achronix.com
E-mail : [email protected]

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Table of Contents
Chapter - 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
GDDR6 Subsystem Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supported Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter - 2: GDDR6 Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Controller Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
By 16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
By 8 Clamshell Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter - 3: GDDR6 PHY Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PHY Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PHY Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PHY Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command/Address Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DQ Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CA PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DQ PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter - 4: GDDR6 Clock and Reset Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter - 5: GDDR6 Interface Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Connectivity to the Peripheral NoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Connectivity Through the Beachfront . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter - 6: GDDR6 Core and Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter - 7: GDDR6 IP Software Support in ACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Step 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Step 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Step 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Step 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Step 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Step 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Chapter - 1: Introduction
The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize
the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and
machine learning systems.The number of GDDR6 subsystems varies with Speedster7t device. For example, the
Speedster7t1500 device provides eight GDDR6 interfaces (GDDR6 subsystems), four on the east side and four
on the west side of the FPGA. Each subsystem comprises the GDDR6 controller and PHY hard cores and
supports up to 512 Gbps; as a result, the 7t1500 offers up to 4 Tbps of total bandwidth. The GDDR6 controller
and PHY in the subsystem are implemented as hard IP blocks in the I/O ring of a Speedster7t FPGA. For
resource counts for other Speedster7t family members, refer to the (DS015).Speedster7t FPGA Datasheet
Note
The following sub-sections in this user guide pertain to the 7t1500 device with eight GDDR6
subsystems.
Features
Each GDDR6 subsystem supports the following features:
Memory Density – Supports GDDR6 devices from 8 Gb to 16 Gb, compliant with JEDEC GDDR6
SGRAM Standard JESD250.
Data Rate - Supports 12 Gbps, 14 Gbps and 16 Gbps data transfer rate per pin, delivering up to 512
Gbps per subsystem interface. As a result, the Speedster7t with eight GDDR6 subsystems can deliver a
total bandwidth of 4 Tbps for the entire device.
Memory Interface - The GDDR6 subsystem consists of two separate channels, each providing a 16-bit
interface. Hence each subsystem provides a 32-bit interface to the external memory.
Controller Configuration – Supports dual-controller configuration with an independent memory controller
for each memory channel.
System Configurable Modes – The subsystem can be configured as either ×16 mode or ×8 clamshell
mode for increased memory density applications.
Data Mask and Data Bus Inversion – Supports GDDR6 data bus inversion (DBI) and command address
bus inversion (CABI). Also, supports write double-byte mask and write single-byte mask operations.
CA and DQ format – Double data-rate command address and data bus.
ZQ Calibration - Supports multiple master/slave ZQ calibration.
AXI4 Interface – Connects to the other IP interfaces within the Speedster7t device or directly to the FPGA
fabric via an AXI4 interface with support for full or half-rate clocking. The connections utilize either a 256-
bit AXI4 interface to the network on chip (NoC), which can run up to 1 GHz, or a 512-bit AXI4 direct-to-
fabric interface, which can run up to 500 MHz.

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Architecture Overview
The diagram below shows the architecture of Achronix's 7t1500 FPGA. The eight GDDR6 subsystem are
distributed four on the east and west sides each of the fabric. There are PLLs on four corners of the device that
supply the external reference clock to the GDDR6 SDRAM cores and other high-speed interfaces that connect
with the peripheral NoC over the FPGA fabric.
The GDDR6 subsystems can interface with the FPGA core in two ways:
NoC Interface – By using the network hierarchy that allows high-speed data flow between FPGA and
peripheral interfaces
Beachfront (direct-to-fabric) Interface – By using the beachfront interface that connects the memory
controller directly to the core. All the eight GDDR6 subsystems can accessed from the FPGA fabric
through the NoC. However, there are only four subsystems (namely GDDR6 1, 2, 5 and 6 from the
diagram below) that connect to the FPGA fabric directly.

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Figure 1: Speedster7t1500 Architecture Overview Block Diagram
GDDR6 Subsystem Overview
The GDDR6 subsystem provides a simple interface between off-chip GDDR6 memory component and the user
logic mapped to the FPGA core. This memory subsystem comprises the PHY IP, the controller IP, clock and
reset block, APB interfaces and AXI4 interfaces to connect to the NoC and fabric. Below is a block diagram of the
GDDR6 subsystem.

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Figure 2: Speedster7t GDDR6 Subsystem Block Diagram
The GDDR6 subsystem consists of the following functional blocks:
Clock and Reset – The clock and reset block receives its input clocks from the on-chip PLLs and
generates clocks to drive the GDDR6 memory controller and the PHY, with a maximum controller
frequency of 1 GHz and a PHY clock frequency of 500 MHz. The command address clock runs at 2 GHz
and the word clock (WCLK) at 8 GHz; this configuration generates data transactions at the maximum rate
of 16 Gbps. The GDDR6 memory uses a double-data rate (DDR) protocol with separate data being
latched at the rising and the falling edges of the clock. At reset, the controller performs the required
initialization of the external memory, including calibration and programming of the internal mode registers.
Controller IP – The controller IP consists of two channels, Channel0 and Channel1 and two controllers,
one for each 16-bit channel of the GDDR6 memory. This configuration enables the two memory channels
to operate completely independently. The controller IP uses the available AXI interfaces to either talk
directly to the fabric or connect to it through the NoC interface. On the other side, the controller is
connected to the GDDR6 PHY via the DFI4.0 interface.The controller has some sub-modules such as
read-modify-write, reorder and the multi-port front-end cores. The memory controller performs writes and
reads to/from the memory and are as described below:
Memory read – To perform a read, a user design signals a read request together with an address
and burst size. The controller responds with an acknowledgement before the data is available. The
controller translates such a burst of data into multiple consecutive transactions.
Memory write – To perform a write, a user design signals a write request together with an address
and burst size. When the GDDR6 memory is ready to receive the data, the controller generates a
data request sent to the PHY
AXI4 Slave Interface – The AXI4 slave interface is used in the memory subsystem to connect the
controller to the FPGA fabric. This interface has two components: the 256-bit AXI4 interface that
talks a to the Speedster7t NoC interface, and the 512-bit AXI4 interface that connects the signals
from the controller directly to the user logic in the core through the beachfront Interface.

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PHY IP – The GDDR6 memory PHY enables the communication between the high-speed, high-bandwidth
off-chip GDDR6 memory and the controller. The PHY supports two channels, each with a data width of 16
bits and speeds up to 16 Gbps per pin, delivering a maximum bandwidth of up to 64 GBps.
Memory Interface – The GDDR6 PHY and the controller IP take care of all the details of the
GDDR6 memory interface, such as precharges, activates and refreshes. The controller issues
commands as closely as possible, subject to the timing requirements of the GDDR6 memory to
achieve maximum efficiency
APB Interface – The APB interface operates at 250 MHz and enables the user to configure the GDDR6
subsystem registers. The subsystem registers are configurable through the APB slave interface where the
master can be from the fabric or FPGA configuration unit (FCU) through the NoC. The FCU configures the
subsystem registers during boot-up, and the user can configure the registers from the fabric during user
mode.
Supported Frequency Table
The table below charts out the rates at which each of the interfaces in the GDDR6 subsystem operate:
Table 1: Supported Range of GDDR6 Interface Frequencies
Data Rate AXI-256 AXI-512 Controller Clock PHY Clock Memory CA clock Memory WCK
16 Gbps 1 GHz 500 MHz 1 GHz 500 MHz 2 GHz DDR – 8 GHz
QDR – 4 GHz
14 Gbps 875 MHz 437.5 MHz 875 MHz 437.5 MHz 1.75 GHz DDR – 7 GHz
QDR – 3.5 GHz
12 Gbps 750 Mhz 375 Mhz 750 Mhz 375 Mhz 1.5 GHz DDR – 6 GHz
QDR – 3 GHz

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Chapter - 2: GDDR6 Controller Architecture
The Speedster7t GDDR6 controller IP provides a high-performance interface to external GDDR6 SDRAM
devices. The memory controller accepts read and write requests using a simple interface and translates these
requests to the command sequences.The controller can automatically perform initialization and refresh functions
and is also provided with programmable registers for all timing parameters and memory configurations that
ensures compatibility with any valid GDDR6 subsystem integration.
The controller core’s interface is implemented as a queue so that new requests can be accepted on every clock
cycle as long as the queue is not full. This construct enables the controller to look ahead into the queue to
perform operations and precharges in advance and optimize throughput and efficiency.
The core uses bank management techniques to monitor the status of each memory bank. All banks can be
managed simultaneously and can be opened or closed only when required, thus minimizing access delays. Read
/write commands are issued with minimal idle time between commands, typically limited only by GDDR6 timing
specifications. Proper bank management results in minimal delay between requests and enables higher memory
throughput.
Controller Features
The following table provides a list of important GDDR6 memory controller features
Table 2: GDDR6 Controller Features
Feature Description
Maximum
frequency The controller supports GDDR6 operation at up to 16 Gbps.
Controller
clock rate Controller operates at half the rate of the command address clock.
Number of
channels Two independent channels; Individual channels can also be disabled.
Memory
Initialization
The memory controller supports initialization using PHY-independent mode.This mode is selected by
setting a register bit; each training is performed by the PHY without intervention by the controller. The
controller performs power-up sequence and then directs the PHY to perform CA training, and finally it
enables word clocks (WCK) and initializes the mode registers of the memory devices. The memory
controller then directs the PHY to perform the remaining training steps at the end of which the PHY
asserts training completion, and then the controller can begin issuing commands.
Queue depth Reorder queue depth fixed to 64, it is not configurable during run time.
Bank
management
Bank management logic monitors status of each GDDR6 bank – banks only opened or closed when
necessary, minimizing access delays.
Bandwidth
and latency
optimization
Look-ahead logic that monitors the user interface queue and examines the access requests, issuing
activate, precharge and auto-precharge commands as soon as possible in order to maximize
memory bandwidth and minimize latency.

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Feature Description
Data width Supports GDDR6 ×16 mode or ×8 clamshell modes.
Write masks Supports write single-mask and write double-mask operations.
Bus
inversion Supports GDDR6 data bus inversion (DBI) and CA bus inversion (CABI).
Refresh Per-bank and all-bank refresh support.
User-
controlled
refresh
Optional user-control of per-bank refreshes.
Auto-
precharge Read/write commands may be issued with or without auto-precharge.
Bus
utilization
optimization
Read/write commands automatically promoted to use auto-precharge to improve bus utilization:
if page-miss requests are detected in the queue
if no page-hits are detected in the queue (programmable option)
Page-hit
mitigation
Memory refresh operations are delayed to prevent interrupting page-hit operations so that command
requests to same page are not separated for long by refresh cycles.
Error
detection
Supports GDDR6 error detection code on the data bus for both read and write transfers. The memory
device provides a checksum (CRC) per byte lane for any read or write data transfer to allow the
controller to determine if the data transfer was completed correctly.
Error
interrupt
Mask-able interrupt outputs for all detected error conditions, with corresponding CSR read and clear-
on-write registers.
Error retry
If the controller determines that an error in a read or write data transfer has occurred, the retry logic is
enabled. The read or write request will be retried, and the Error Detection and Correction (EDC)
results will be rechecked until the results are correct or the retry threshold has been exceeded.
Error status Controller tracking of link error statistics such as retries and failures.
Controller Architecture Overview
The figure below shows the memory controller and its sub-modules multi-port front-end, reorder, read-modify-
write, memory test and memory test analyzer cores. These blocks offer higher efficiency and throughput by re-
ordering controller commands and also provide for test and debug capability:

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Figure 3: GDDR6 Controller IP Block Diagram
The GDDR6 controller consists of the following functional blocks:
Multi-Port-Front-End (MPFE) Core – The MPFE block provides a multi-port interface to connect to the
controller channels.There are two MPFE ports per Channel0 and Channel1 controllers where one port is
driven by the NoC interface and the other is driven directly by the fabric.
Reorder Core – This submodule is used in conjunction with controller core to reorder user requests to the
DRAM controller. Reordering can result in significant improvement of DRAM bus efficiency as it reduces
bus idle times imposed by DRAM access rules. The reorder core can be parameterized to use different
reorder criteria. This block can also be bypassed to maintain the original sequence of user requests.The
optimal reorder criteria is chosen based on the nature of the requests coming from the user logic. The
controller offers a queue depth of 64 for optimized performance.
Read Modify Write (RMW) Core – The RMW submodule supports address masking feature.
Memory Test Core – The memory test core can be connected to the controller core to perform write and
read operations to verify the integrity of the memory interface and memory devices. It consists of different
pattern generators to support standalone testing during board bring-up.
Memory Test Analyzer Core – The memory test analyzer can compare the expected data with the read
data and provide a status to the user. It can also be used to capture memory test signals of interest.
Memory Controller Core – This queue-based, high-performance interface helps the controller to perform
queue look-ahead in advance of upcoming commands to better optimize throughput and efficiency. The
core also uses management techniques to monitor the status of each memory bank, including
programmable registers for all timing parameters as well as memory configuration settings.
The controller also interfaces with the following functional blocks:
AXI4 Interface – Provides AXI4 interfaces. The controller can access either the NoC interface via the 256-
bit AXI4 interface or connect directly to core fabric using the 512-bit AXI4 interface.
APB Interface - There are four APB slaves in the GDDR6 subsystem, one per controller and one for the
PHY. It also includes few register maps to enable clock and reset functionalities. The clock and reset of
APB slaves are connected by CSR signals. The last APB slave is connected to IPCNTL components.
Modes of Operation
The Speedster7t GDDR6 controller supports two read/write channels, each with an independent memory
controller. The GDDR6 subsystem supports the following two modes:

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By 16 Mode
In this mode each controller provides an interface to a single 16-bit memory channel. A block diagram of the dual-
controller system using a single memory device in ×16 mode is shown below:
Figure 4: Dual-Controller ×16 Mode Block Diagram
By 8 Clamshell Mode
The controller can also be configured in ×8 mode clamshell mode to talk to two memory devices. Clamshell
mode provides a way to double the density of the system by sharing the same command/address bus between
two devices in the system. A block diagram of the configuration in a clamshell arrangement is shown here:
Figure 5: Dual-Controller ×8 Clamshell Mode Block Diagram

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Chapter - 3: GDDR6 PHY Architecture
PHY Overview
The embedded Speedster7t GDDR6 PHY supports the GDDR6 memory standard at the channel interface and
DFI-4.0 interface on the FPGA side with the memory controller. It supports a maximum data rate of 16 Gbps and
is targeted for systems that require low-latency and high-bandwidth memory solutions.
The PHY consists of two independent 16-bit channels, each composed of a modular command/address block
(CA) and two data byte (DQ0 and DQ1) blocks.The figure below shows the PHY interfacing with the off-chip
GDDR memory on one side and the memory controller on the FPGA side.
Figure 6: Speedster7t GDDR6 PHY Block Diagram

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PHY Features
Table 3: Speedster7t GDDR6 PHY Features
Feature Description
DRAM density SDRAM Density up to 16 Gb per component supported.
DRAM speeds The 7t1500 supports 12 Gbps, 14 Gbps and 16 Gbps data rates.
Number of channels Two independent 16-bit channels. Individual channels can also be disabled.
GDDR PHY interface DFI-style interface provided for PHY. The PCLK is an clock input to the PHY and PCLK:
CK frequency ratio is fixed to 1:2
Command address bus
inversion (CABI) Supports CABI where each controller has a bit to enable CABI.
CA format Double data rate (DDR) where data is latched on both edges of the clock.
CA serialization ratio 4:1 (corresponds to command address clock CK to PHY clock PCLK frequency ratio of
2:1).
CA driver impedance
(RON) 40/48/60Ω.
CA termination 60/120/240Ω.
Data bus inversion (DBI) Supports DBI where each DQ byte has a bit for DBI.
DQ format DDR and QDR based on WCLK.
DQ serialization ratio 16:1 (corresponds to PCLK to CK frequency ratio of 1:2 and QDR/DDR WCK mode).
DQ burst length Supports a burst length of 16
Receiver configuration POD style receiver. Internal V and DFE
REF
DQ driver impedance
(RON) 40/48/60Ω,
Error detection code
(EDC) There is a bit per DQ byte for EDC.

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PHY Architecture
The PHY consists of the command/address (CA) block, DQ byte blocks, PLLs and the global logic block. There
are three PLLs present in the entire PHY: one for the CA block and one for each of the two DQ words.
Command/Address Block
The command/address block executes the following operations:
PHY configuration using DFI status interface.
Serialization of commands and controls in the transmit data path. The controller provides the parallel data
in the PCLK domain and that data is transmitted to the DRAM in CK domain.
Per CA bus timing adjustment capability through CA training.
Memory controller initiated update to interface for periodic driver impedance calibration
PHY-initiated update interface for periodic training in PHY independent mode.
DQ Block
Each DQ block handles:
Serialization of write data in the transmit data path. The controller provides the parallel data and write
control signals in the PCLK domain. Data is then transmitted to DRAM based on the WCK frequency.
De-serialization of read data in the receive data path. The memory controller provides the read control
signals in the PCLK domain. Data is received from the DRAM with reference to WCK and passed on to
controller in PCLK domain.
Per-DQ eye timing adjustment for both transmit and receive paths.
Read/write eye training and calibration such as WCK to CK.
Per-pin internal V generation and calibration.
REF
Registers for debug and control.
CA PLL
The CA PLL block handles high-speed clock (CK/CKN) generation using the PLL. CK/CKN is common for both
the channels of DRAM. Different DRAM data rates are supported with appropriate PLL multiplier and post-divider
ratios. Reference clock and DFI clock is provided by the FPGA. The internal or local PCLK is aligned to FPGA
PCLK using a DLL.
DQ PLL
The DQ PLL (one per ×16 interface) handles high-speed clock (WCK/WCKN) generation using PLL. WCK
/WCKN is present per byte or per word as per DRAM configuration. Different DRAM data rates are supported
with appropriate PLL multiplier ratios and post-divider ratios. The PCLK is supplied by the FPGA to the PHY per
DQ channel. The internal or local PCLK (LPCLK) is aligned to the FPGA PCLK using an embedded PHY DLL
that is present per DQ byte channel. The global logic block handles the APB register interface from the memory
controller and CA PLL configuration, initialization and frequency changes using DFI status interface.
The figure below shows a high-level PHY I/O diagram:

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Figure 7: High-Level PHY I/O Block Diagram

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Chapter - 4: GDDR6 Clock and Reset Architecture
The Speedster7t GDDR6 subsystem has 32 global clocks where the selection of clocks are configurable through
IPCNTL registers. These global clocks are generated from two PLLs, each generating 16 clock outs. There are
two 32×1 clock multiplexer implemented whose selection is driven by IPCNTL registers. The first clock
multiplexer output drives the controller, PHY, AXI1 (256-bit AXI4) blocks, and the second clock multiplexer drives
the AXI2 (512-bit AXI4) block. The selected AXI1 and AXI2 clocks are provided to the NoC and fabric
respectively.
Similarly, there are 32 global resets and 48 active-low FPGA configuration unit startup resets connected to a
80×1 reset multiplexer. The selection of resets is also configurable through IPCNTL reset selection register.
There are three reset multiplexers which generates the reset for the complete subsystem. First reset multiplexer
output drives the IPCNTL reset, second drives the controller, PHY, AXI1 module, and the third drives the AXI2
module.
IPCNTL block is implemented in the subsystem which has the APB slave, address decoding and subsystem
CSR registers. IPCNTL block operates off the CSR clock.
The diagram below shows the clock and reset block:
Figure 8: Clock and Reset Architecture of GDDR6 subsystem
The global PLLs in the FPGA generate the 32-bit wide global clock (gddr6_glb_clk), and the reset block
generates the global resets. The clock and reset generator block generates clocks to drive the controller, PHY,
and also the fabric clock when operating in beachfront mode. The PHY clock frequency is half of the global clock;
and the controller clock operates at the same rate as the global core clock.
The GDDR6 interfaces on the east side receive their clocks from the two PLLs on the east side and similarly, the
two PLLs on the west side generates clocks for the west GDDR6 controllers. There is no clock domain crossing
between the east and west side GDDR6 controllers, helping to achieve the maximum data rates across all eight
GDDR6 interfaces.The resets for all controllers can be tied to an external reset. The figures below show how a
user can connect the reference input clocks to drive all eight GDDR6 controllers, However, the preferred
configuration will be based on the jitter and skew assessments of the user design.

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Figure 9: External Clock to South PLLs Driving the GDDR East/West Subsystems
on the AC7t1500 device
Figure 10: External Clock to North PLLs Driving the GDDR East/West Subsystems
on the AC7t1500 device