ADC Super Net S-100 User manual

nCHNICAL MANDAt
for
SUPER NET
S-100 Single Board Computer
/~
7201 Garden Grove Blvd., Suite E
Garden Grove, CA
92641

INTRODUCTION
·ADVANCED MICRO DIGITAL is proud to introduce the SUPER NET.
The SUPER NET is a ZaB based single board computer designed
t" be a bus master in an 5109 bus system. The. SUPER NET SBC
has aIl the hardware needed to [un a single user CP/M system
or 2 user MP/M system with up to 4 external floppy disk drives
and an external Centronlcs parallel interface prlnter all on
one board.
The SUPER NET sac contains :
1) Z-89A
cpu
2) Floppy disk c~ntroller (up to 4 drives a or 5 1/4 • )
3) 64 k
of dynamic memory ~16K bank selectible)
4) 2k or 4k of shado~ eprom (2716 or 2732)
5) 2 seriaI ports (Za9A 510 opt.syncronous)
6) 2 12 bit parallel ports, one of which cao be used
for 5100 vectored interrupts (Z80A PlO)
7) Real time interrupt clock
(Z80A CTC)
8)' 5190 extended address A16 -A23
1

Introduction
TABLE OF CONTENTS
~------~---------
••• • • • • •• • ••••••••• • • • •• • • • • • •••••• • •• • • • •• • •• • • • • •
Table of Contents •••••••••••••••••••••••••••••••••••••••••••••• 2,3
Operation ••••••••••••••••••••••••••••••••••••••
1.1 Floppy disk ••••••••••••••••••••••••••••
1.2 64 K Dynamic Ram •••••••••••••••••••••••
1.3 Monitor Eprom ••••••••••••••••••••••••••
1.4 SeriaI Ports •••••••••••••••••••••••••••
1.5 Parallel Ports •••••••••••••••••••••••••
1.6 Real Time Clock ••••••••••••••••••••••••
1.7 S100 bus interface •••••••••••••••••••••
4
4
5
5
2.0
EPROM
2.1
2.2
2.3
2.4
a nd Mo n i to r ••••••••••••••••••••••••••••••
Enable / Disable software •••••••••••••••
Monitor Sign-on •• · •••••••••••••••••••••••
Monitor Commands •••••••••••••••••••••••
Cold boot loader program •••••••••••••••
7
8
8
9
3.0 Input ~·Output port assignments ••••••••••••••••• 10
4.0
Input
/
Output port
description
••••••••• • ·1 •••••
Il
4.1
SIO
seriaI
port
channel
A.............. .10 ...
4.2 SIO
seriaI
port
channel
B..............
11
4.3 Pla
parallel port channel
A............
11
4,.4 Pla
parallel port channel
B............
11
4".5
Control timer Interrupt circuit
·......
11
4.6
Floppy Disk
controller
.................
Il
4.7
Floppy
disk control port
...............
12
4.8
Extended
address
port
..................
13
4.9
On-board
memo~y
control port
...........
14
5.0
Jumper
definitions
.............................
1~
6.0 Jumper
descriptions ............................
6.1
Jumper A CPU
clock rate
..............
6.2
Jumper B-
SIO
channel
A
clock
.........
6.3
Jumper C-
SIO
channel
B
clock
.........
6.4
Jumper
0-
Drive
type selection
........
6.5
Jumper
E
VIa
/
PINT
..................
16
6.6
Jumper
F-VIO /
paralled
bit
00
·......
16
6.7 Jumper
G-
VII
/
paralled
bit
Dl
·......
17
6.8
Jumper
H-
VI2
/
paralled
bit
02
·......
18
6.9
Jumper
J-
VI3
/
paralled
bit
03
·......
18
6.10
Jumper
K- VI4
/
paralled
bit
04
·......
18
6.11
Jumper
M- VIS
/
paralled bit 05
·......
6.12
Jumper
N-
VI6
/
paralled bit
06
·......
2

6.13
6.14
6.15
6.16
-.6.11
Jumper P VI1 / paralied bit 01 ••••••• 19
Jumper·R 2116 / 2132 •••••••••••••••••
Jumper S Floppy connector ••••••••••••
Jumper T Memory Write Signal ••••••••• 20
Jumper layout ••••••••••••••••••••••••••• AA
Rate Switch •••••••••••••••••••••••••••••••
1.0
Baud
1.1
Switch Setting
•••••••••••• • ••••• • • •• • • •
21
21
8.9 External Connector pin definitions •••.•••••••••• 22
8.1 Jl S100 bus •• ~ •••••••••••••••••••••••
8.2 J2 paral1el Port •••••••••••••••••••••
8.3 J3 Floppy Oisk controller 2~
8.4 J4 Serial port channel A ••••••••••••• 25
8.5 J5 Serial port channel B •••••••••••••
9.0
Block Oiagram ••••••••••••••••••••••••••••••••••
25
10.0
Factory
10.1
10.2
10.3
la.4
1a.5
10.6
10.1
10.8
10.9
1a.9.1
Installed Jumpers· ••••••••••••••••••••••
8 inch drive configuration ••••.•.••••••••
5.25 inch drive configuration ••••••••••
Shugart 800 drive ••••••••••••••••••••••
:shugart 850 •••••••••••••••••••••••••••••
MP1 dr ive •••.•••••••••••••••••••••••••••
MFE model 700 •••••••••••••••••••••••••••
MITsUB1sat model M2894 ••••••••••••••••••
NEC 'model FD1160 .
QUME Data Track 8 •••••••••••••••••••••••
REMEX mode1 RFD4a00 •••••••••••••••••••••
26
27
28
29
30
31
32
33
34
35
11.a
Appendex & Data sheets •••••••••••••••••••••••••
11.1 Appendex AZ80A 510 / DART •••••••••••
11:.2 Appendex BZ80A PlO ••••••••••••••••••
11.3
11.4
11.4.1
11.S
11.6
11.7
11.8
Appendex CZ80A CTC ••••••••••••••••••
Appendex 0 Floppy Disk contro1ler ••••
WD 1691,BR1941 •••••••••.••••••••••••••••
Appendex E - Z80A CPU ••••••••••••••••••
Appendix F- PS NET/I adapter board •••••
Appendix G- PS NET/PAR parallel adapter
Warrant y ••••••••••••••••••••••••••••••••
12.0
13.0
parts list
Schematic Diagram
3

1.1 The Floppy Disk Controller
-~--~---------------------
The floppy disk controller can access up to four 8 inch or 5.25
inch floppy disk drives. It can read and write IBM 3740 single
-
density format, and double density 128,256,512,1024 sector size
formats. Data -transfer is done by programmed 1/0 with wait and
interrupt syncronization.
Note: The controller cannot access both 8 inch and 5.25 inch drives
simu1taniously,The controller is switched from 8 inch to 5.25 inch
drives by hardware jumper options.
1.2 The 64 k Dynamic ram
------------------~-
-
The 64 k ram array can be switched on and off in 16 k Increments
(0-16K,16K-32K,32K-48K,48K-64K) under software control. This a1low~ t:
CPU to access bank switchab1e external memory on the 5100 bus.
The memory has an access time of 200ns. Refresh is done during
280 Ml cycles and during wait and reset states. The memory can
be accessed by an external DKA device on the 5100 bus.
Note :Any external DKA device that is using continous mode DMA
cycles must transfer data at an average rate of 15 us
per byte or
faster when holding the DMA request line for more than 1.5 ms This .s
not a problem because most designers are smart enough to use
byte-at-a-time or burst transfer modes when dealing with, slow DMA
transfer rates. The ram row address is the low order address there-
for the entire ram array is refreshed by the DMA device every 128
contiguous memory cycles.
4

1.3 System Monitor Eprom
---------~--~~-----~
The system monitor eprom is switched on durlng reset. 1t can be
disabled"and enabied under software control. lt resides when
enabled at F000h to FFFFh. lt bas commands that allow the user
to load the CP/M, MP/M'or other boot loaders from floppy dlsk.
J
In addition it can be used to load , examl~e goto and test
memory. When the prom is disabled it does not use any system addres~
space.
1.4 Serial ports
AZ80A DART is used for the two serial ports , but
aZ80A S10/0 chip can be used in it's place. This allows
asyncronous and synchro~ous serial data communications plus a variety
of interrupt modes. Modem control s1~nals are available at each
seria1 connector. There are· two switch selectible baud rate
generators for baud rates of 50 to 19.2 k baud.
Note : The serial ports are TTL and must be connected to external
interface boards ·for R5232 communications.
(PS NET/I)
1.5 Parallel ports
AZ80A PlO is used as the parallel port. The "A" channel of this chi
t
1s connected to the parallel port connector. This port has 8 bi-dir-
ectional data 11nes and two hand shake lines. The "B" port can be spJ
between the parallel port connector and the 5100 bus vectored interr\
. lines by jumper options. This allows the port to be used as an
additlonal parallel port or interrupt controller or both.
In the output mode the parallel ports can drive one TTLload •
5

1.6 Real Time Interrupt c10ck
AZ80A CTC is used for providing a rea1 time system c10ck for MP/M.
Three channels of the CTC are avai1ab1e to the user for strapping
a jumper header for synchronous baud rates or 10n9 c~ock times.
1.7 5100 Bus Interface
The 5100 bus interface provides the signa1s necessary for an 8 bit
bus master as described by the IEEE 696 bus specification.
Vectored interrupt 1ines VI0 - VI7 are supported via jumper options
and A16 -A23 are also supported vis an 1/0 port.
The PAMNTON line is also implemented for the dynamic ram array.
6

2.0 EPROM and-Monitor operation
The onboard EPROM~ccupies address F000H-FFFFH. The EPROM
is switched on automatically during reset or power on, the
EPROM contains SIO and FOC initia1ization code a10ng with a
simple debuqqer and floppy disk cold start loader. After
the operatinq system is loaded the EPROM.~can be turned off
so that the ram at address F000H-FFFFH can be accessed. The
EPROM can be turned on and off at any time so that hardware
dependent 1/0 routines can be ca11ed.
2.1 Eprom Enable / Disab1e
Switching EPROM
on
:
F033
3E4F
.MVI
A,01001111B ;RESET POWER ON JUMP
;
AND ENABLE MEMORY, EPROM ON
F035
0316
OUT
'168
;WRITE Ta CONTROL PORT
Switching EPROM
off
.
..
.
F033 3E4F MVI
A,01101111B iRESET POWER ON JUMP
;
AND ENABLE MEMORY,
EPROM
OFF
F035 D316
OUT
16H ;WRITE
TO CONTROL PORT
Jumper R configures the board to accept a 2716 or 2732 EPROM.
Note : The EPROM is a1ways addressed at F800H and can not
be moved. Since the 2716 EPROM is 2K long it appears
twice , F800H-FC00H and FBFFH-FFFFH.
2.2 Monitor Siqnon
The EPROM contains a simple debuqqer.
The monitor signs on with :
> AOVANCED MICRO DIGITAL CORP.
Monitor Version 1.0
Nov - 1981
Press "a- for help
>
2.3 Monitor Commands
7

The monitor comm~nds are :
Control C= Load disk boot loader
o SSSS 0000 =Dump memory in hex from SSSS to OQQO
F ssss OQOO BB = Fill memory from SSSS to OQQQ with BB
G AAAA =Go to address AAAA
L AAAA = Load memory starting at AAAA
M= Memory Test
P ssss QQQO = print in ascii from SSSS to OQOO
R= Find system ram
S SSSS QQQQ = Search for byte pattern
T= Test Memory
ESC will terminate any command
The coldboot loader will select and home drive 0.
Track 0 sector 1 will be read into memory at location 0 •..
Single density is assumed for track 0.
If an errOL occures an error code will be printed.
The error code must be translated using the table
in appendex F page F-4 fig 2.
2.4 Cold Boot program
; REAO TRACK 0SECTOR 1INTO MEMORY
BOOT:
F4BS 3E00
MVI A,00H
F4B7 03aC
OUT
FOC
F4B9
00
NOP
FOCW1:
F4BA OB0C IN
FOC
F4BC 0F
RRC
F4BD
OABAF4
JC
FDCWl
F4C0 00
NOP
F4Cl
00
NOP
F4C2
00
NOP
RESET FOC
; ISSUE COMMAND
; CHECK BUSY
KILL TIME

F4C3
00 NOP
F4C4
3E03 MVI
A,3
;GET A RESTORE
F4C6
030C OUT
FOC
·
ISSUE
COMMAND
,
F4C8
a0 NOP
F4C9
0814 IN
WAIT
·WAtT
FOR
,
F4CB
00
NOP
·INTRQ
,
TK0:
F4CC DB0C
IN FOC
F4CE E.604 ANI 4.
CHECK TRACK 0
,
F4D0 CACCF4 JZ TK0
F4D3
AF XRA
A
F4D4
6F
MOV L,A
POINT
AT LOC
0
F4DS
67
MOV
H,A
F4D6 3C INR A
F4D7
030E
OUT FDCSEC ;SET SECTOR
F4D9 3E8C
MVI
A,a8ea
;GET
READ COMMAND
F4DB
030C
OUT
FOC
;
ISSUE COMMAND
F4DD
00
NOP
FDCRD:
F4DE
D814
IN
WAIT WAIT
FOR INTRQ
F4E0
87 ORA
A;
OR ORQ
F4El
F2EBF4
JP
BOOTON
EXIT IF INTRQ
F4E4
DB0F
..
IN FDCDATA
GET DATA
1:'4EG
77
MOV M,A STORE'
I: 4E'7
23
INX H POINT NEXT
F4E8 C30EF4
JMP
FDCRD
:
BOOTDN:
F4EB
DB0C IN
FOC
;
CHECK STATUS
F4ED
B7
ORA A;o= NO ERROR
F4EE CA0000 JZ
"OK,
GO
F4Fl
FS PUSH
PSW ;
SAVE ERROR
F4F2
210FF6
LXI H,BTERR ;
PRINT
F4F5
CDE6F0 CALL
MSG
OISK ERROR
F4F8· Fi
POP
PSW
GET ERROR
F4F9 CD21Fl
CALL
THXB
;
PRINT IT
9