Advanced Digital SUPER SIX S-100 User manual

SUPER SIX
S-1. 00 Single Board
Computer
-Technical - Manual
«j> ADVANCED
DIGITAL
USA OFFICE
5432 PRODUCTION DRIVE
HUNTINGTON BEACH, CA 92649
TELEPHONE : [phone]
TELEX: 183210 ADVANCED HTBH
CORPORATION
UNITED KINGDOM OFFICE
27 PRINCESSS STREET
HANOVER SQUARE, LONDON
W1 R8NQ
UNITED KINGDOM
409-0077 / 409-3351
TLX 265840 FINEST
]

SUPER SIX™
S-lOO Single Board Computer
Technical Manual
June 1, 1983
ADVANCED DIGITAL CORPORATION

TABLE. OF CONTENTS
SECTION TITLE
SECTION I - JNTRODUCTION
1.1 Purpose
1.2 Equipment Overvie'W
1.3 Document Organization
1.4 List of Acronyms
1.5
Document Maintenance
1.6 Theory of Operation
SECTION II -OPERATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.9.1
2.9.2
2.9.3
2.9.4
Floppy Disk
Controller
128K Dynamic RAM
System Monitor EPl{OM
Serial Ports
Para1Jel Ports
Real Time Interrupt Clock
S- 100 Bus Interface
Baud Rate Jumper
EPROM and Monitor Operations
EPR OM Enable and Disable
Monitor Sign-on
Monitor Commands
Cold Start Program
RAM Organization
Z80A DMA Features
PSNET/1 Operation
PSNET /PAR Operation
Synchronous Operations
Power Consumption
SECTION HI -INPUT/OUTPUT POR TS
3.1 Input/Output Port Assignments
3.2 Input/Output Descriptions
3.2.1 Port 00
3.2.2
Port 01
3.2.3 Port 02
3.2.4
Port 03
3.2.5 Port 04
3.2.6
Port 0.5
3.2.7 Port 06
3.2.8
Port 07
3.2.9
Port 08
3.2.10 Port 09
3.2.1 1
Port OA
3.2.12 Port DB
3.2.13 Port OC
3.2.14 Port OD
3.2.15 Port DE
3.2.16 Port OF
3.2.17 Ports 10-13
PAGE
1
1
1
2
2
3
3
4
4
4
5
5
5
5
5
7
.7,
7
8
8
10
11
11
11
12
12
12
13
13
14
14
14
14
14
14
14
14
14
14 .
15
15
15
15
15
15
15
15
AU information contained in this document is the property of Advanced DigitaJ
Corporation.

TABLE OF CONTENTS (continued)
SECTION TITLE
PA~E
3.2.18
Port 14
16
3.2.18.1
Port 14 Read Opera tion
16
3.2.19
Port 15 17
3.2.19.1
Port 15 l{ead Operation
17
3.2.19.2
Port 15 Wri te Operation
17
3.2.20
Ports 16 and 17
17
3.2.20.1
Port 17 \\I ri te Operation
18
3.2.20.2
Port 17 W rite Operation
l~
3.2.21
Ports 18-1B
21
j
SECTION IV - JUMPER CONNECTIONS
22
4.1
Jumper Definitions
22
4.2
Jumper Descriptions
23
4.2.1
Jumper A 23
4.2.2 Jumper B 23
4.2.3
Jumper C 23
4.2.4
Jumper D 24
4.2.5
Jumper E
24
4.2.6 Jumper G 24
4.2.7
Jumpers Hand T
24
4.2.8
Jumper J6
24
4.2.9
Jumper R25 25
4.2.10
Jumper J7
25
4.2.11
Jumpers P, N, M, K, J, R, S, and F
2.5
4.3
Factory and OEM Installed Jumpers
26
4.3.1
8-lnch Floppy Disk Drive
26
4.3.2
~hugart SA800/801 Disk Drive
26
4.3.3
Shugart 850 Disk Ori ve
27
4.3.4 MFE Model 700 Disk Drive
27
4.3.5
Tandon Slim Line Disk Drive
27
4.3.6 NEC Model FD1160 Disk Drive
28
4.3.7
QUME Data Track Disk Drive
28
4.3.8
Tandon 5.2.5 Inch Disk Drive
28
4.3.9
Mitsubishi Model 2894 Disk Drive
28
4.3.10
Mitsubishi Model 2896 Disk Drive
28
4.3.11
Shugart SA 860 Disk Drive
28
4.3.14
Siemens FDD-I00-8 Disk Drive
29
4.3.16
Qume Trak 592 5.25 Inch Disk lJrive
29
4.3.17 All Other Disk Drives 29
SECTION V - EXTERNAL CONNEC10R PINS 30
5.1
Connector S-100
30
5.2
Connector J 2
31
5.3
Connector J3
32
5.4
Connector J 4 33
5.5
Connector J5
33

TABLE OF CONTENTS (continued)
SECTION TITLE
APPENDIX A - Z80A/Z80B SIO AND DART
APPEN DIX B - Z80A/Z80B PIO
APPENDIX C - Z80A/Z80B eTC
APPENDIX D - Z80A/Z80B CPU
APPENDIX E - 280 DMA
APPENDIX F - FLOPPY DISK CONTROLLER
APPENDIX G - FLOPPY DISK El{ROR CODES
APPENDIX H - APPLICATION NOTES
APPENDIX I - SUPER SIX WARRANTY
APPENDIX J -PARTS LAYOUT AND LIST
APPENDIX K - PLL REALIGNMENT
APPENDIX L - PSNET/l SCHEMATICS
APPENDIX M - PSNET /PAR SCHEMATICS
APPENDIX N - SUPER SIX SCHEMATICS
FIGURE NO.
2-1
2-2
TABLE NO.
1-1
2-1
2-2
3-1
3-2
4-1
5-1
5-2
5-3
5-4
5-5
LIST OF FIGURES
TITLE
SUPER SIX Interface To the S-100 Bus
SUPER SIX RAM Configuration
LISl OF TABLES
TITLE
List Of Acronyms
SUPER SIX Baud Rate Jumper Settings
Monitor Commanas For the SUPER SIX
I/O Port Assignments For the SUPER SIX
SUPER SIX
Port 18 Baud Rate Settings
SUPER SIX Jumpers and Abbreviated Functions
SUPER SIX J I Connector Pin Functions
SUPER SIX J2 Connector Pin Functions
SUPER SIX J3 Connector Pin Functions
SUPER SIX J4 Connector Pin Functions
SUPER SIX J5 Connector Pin Functions
PAGE
6
11
PAGE
2
7
9
13
21
22
30
31
32
33
33

SECTION I
INTRODUCTION
1.1
PURPOSE
This Manual
provides the technical information necessary to mstall, uperate dna maintair.
the SUPER SIX singleboard computer by Advanced Digital Corporation.
1.2 EQUIPMENT OVER
VIEW
SUPER SIX, produced by Advanced Digital Corporation, is the first single board computer
for the S-IOO bus running at 6MHz. Without the S-100 bus the SUPER SIX can also run. as
a standalone computer executing a single user CP/M 2.2 or 3.0, or a multiuser MP /M,
OASIS,
or TurboDOS operating system. SUPER SIX runs substantially faster than any
other S-l 00 single board computer a vialable in the market.
The SUPER SIX contains the following set of capabilities:
1. 280B CPU operating at 6MH2
2. 128K
of dynamic bank se lect RAM arranged in 16k banks
3. Floppy Disk
Controller which supports the 8-inch and 5.25-inch disk
drives simultaniously
4.
2/4 K of shadow EPROM (Monitor)
5. 2
serial I/O (RS-232) ports offering software or hardware selectable
baud rate, 280B DART
6. 2
parallel ports (280B PIO)
7. Real time clock (280B CTC)
8.
DM A controller (280 DM A)
9. Extended addressing: A16-A23
10. Single 5 volt supply on board
11. One-year warranty
12. Free copy of CP/M 2.2 BIOS supplied.
* NOTE: Items 5 and 6 require external adaptation for
RS-232 and Centronics. The adapter boards contain a
DB-25
connector on a 2-inch by 2-inch board attached to
the back panel·of the 5-100 system (MODEM and RS 422
Paddle cards are also available).
-1-

1.3 "
This document is organizt'd inh' ') sc\.·t i,-'Ils .. md 14 .lppcndices.
Section I serves as an introductioll to tht' entire document, stating the purpose of the
document and providing an introduction to the SuPER SIX single board computer. This
section also provides a list of acronyms used in the document and provides a statement on
the responsibilities of document maintenance.
Section II provides a description of the operations of aU components associated with the
SUPER SIX single board computer.
Section III lists aU SUPER SIX input/output ports and defines the assignments and
functions of each port.
Section IV lists and defines aJJ SUPER SIX jumper connections. This section includes the
jumper ,assignments for factory (OEM) installed jumpers.
Section V describes the external connector pins for SUPER SIX connectors J 1 through J5.
The
appendices provide supplemental material to the body of the text and are referenced
in the text at the associated points.
1.4 LIST
OF ACRONYMS
Table 1 -1 provides a listing and description of the acronyms used within this text.
ACRONYM
DESCRIPTIO~
CPU
Central Processor Unit
CTC ControJJer
/Timer Circui t
DART Dual Asynchronous
Receiver/Transmitter
DMA
Direct Memory Access
EPROM
ElectricaUy Erasable Programmable Read-Only Memory
FDe Floppy Disk
Controller
IEEE
Institute of Electrical and Electronic Engineers
MP/M Multiuser
Program For Microcomputers
OEM Original
Equipment Manufacturer
PIO ParaUel Input/Output
PROM
Programmable Read-Only Menlory
Table 1-1. List
of Acronyms
-2-

Table I-I. List of Acronyms (Continued)
ACRONYM DE~CRIPTIOi\
1.5
RAM Random Access Memory
SIO
Serial Input/Output
TTL Transistor-transistor Logic
TurboDOS A Multiuser
Networking Operating System used as software with the
SUPER SIX
DOCUMENT MAINTENANCE
This
document is the property of Advanced Digital Corporation, who is responsible for its
content. Any modifications made to this manual must be made with the express written
approval of Advanced Digital Corporation.
1.6 THEORY
OF OPERATION - ST ART-UP PROCEDURE
The SUPER SIX Single board computer is shipped configured for 19.
installation procedure is as follows: baud
rate. The
1. Plug the PSNET /1 to connector J5. Use caution; pin 1 is marked.
2. Connect the CRT. Pins 2, 3, 5, 7, and 20 must be used; no parity
must be specified,
3. Apply power to the system. The monitor message shown in
subsection 2.9.2 appears. Check the CRT baud rate- if 9600 baud is
required, unplug jumper area J7, pin 7-8.
4. Install
the floppy disk cable, load the CP/M diskette, and bootstrap
the system.
Note: CP/M is shipped configured for 64K bytes of
memory. The parallel port is configured as the default
printer. 1024 bytes per sector read/writes are also'
supported (or DMA). The plus 8V and the plus/minus 16 V
on the S-lOO bus must be verified prior to installing the
SUPER SIX board.
-3-

SECTION II
OPERATION
This section describes the opera tion 01 all SUPER SIX <;:ompone.nts.
2.1
FLOPPY DISK CONTROLLER
The floppy disk controiJer can access up to four 8-inch or four 5.25-inch disk drives or any
combination of the two. The controller can read and write ISIv1 3740 single density format
and double density 1024 sector-SIze formats. Data transfer is performed via Direct
Memory Access (DMA). Due to the simultanious operation capability of the SUPER SIX
the format compatibility problems with 5.25-inch disks have been eliminatea. The floppy
disk
controller used is the WD27~3. The WD2793 has on-chip PLL ,data separators and
on-chip write pre-compensation logic. Adjustments for PLL are factory set dnu write
pre-compensation has been provided with the SUPER SIX. 50 Pin and 34 pin connectors
are available for 8-inch and 5.25-inch disk drives respectively.
2.2
NOTE: Customer adjustment of trim pots
may result in cancellation of warranty.
THE 128K DYNAMIC RAM
The 128K RAM
array can be switched ON and OFF in 16K increments, (0-16K, 16K-32K,
32K-48K, 48K-64K
for both banks) under soitware control. This feature allows the CPU
to access bank switchable external memory on the S-IOO bus. The memury has an access
time of 150ns. A Refresh operation is performed during Z80 MI cycles and during \V AIT
and RESET
states. The memory can be accessed by floppy dIsk via D~iA, serial and
paralle 1'I/O, or another DMA device un the S-l 00 bus.
*NOTE: Any external DlV1A device that is
using continous mode DMA cycles must
transfer data at an average rate of 1501s per
byte or faster when holding the DMA request
line for more than 1.5I11s. The RAM row
address is the low order address; therefore
the entire RAM array is refreshed by DMA
device every 128 contiguous memory cycles.
Under CPM 2.2 or CPM 3.0 the additional 64K can be used as a dISk buffer. The ·SUPER
SIX is ideal when operating in the bank mode under CP/M 3.0, as 128K RAM is required.
-4-
\

2.3 SYSTEM
MONIT01< EPHOM
The system monitor t.PHOM is switched ON during reset. Jt C~II t)(~ (jj~~t.Jl(:a dr,G (:rlabled
under software control. When enabled, the system IIluflltor r(:sjrj(:C) dt locations
F800-FFFF (hex) (refer to subsection 2.9.1.2) when using 1716 Ll't<U,\' or CIt locations
FOOO-FFFF (hex) when using the 2732 EPRL'M. lhe ~>stelrr I/lonitur LP~lIM contains the
cold-start loader for CP /tvl, MP /1\1 and 1 urboDl.\). In .:idunia!I jt Cdn De used to perform
LOAD, I/O READ and 1/0 'W RITE operations. 'When the LP1.(,-).vi is disablea no system
address space is used.
2.4
SERIAL PUR IS
A 6MHz Z801:) DART is used for the two serial I/O ports; a 2:805 ,)10 or Z80A DAH T can
be used in it's place (if a 4MHz Z80A DART is used the CPU and all other devices must
also be 4MHz). This allows asynchronous serial data communication plus a variety of
interrupt modes. Modem control signals are available at each serial connector. There are
software selectable baud rates as well as hardware selectable baud rates (mini-jumpers
J7).
2.5
* NOTE: The serial ports are TTL and must
be connected to PSN ET/ 1 (serial adapter
interface) for RS-232 communications. The
J4 connector is for the CR T; the J5
connector is for the serial printer or CH T.
PARALLEL POl{ 15
A 6MHz 280B PIO is used as the parallel port. The "A" channel of this chip is used to
connect the parallel port connector (J2) to PIO. This port has an 8-bit bi-directional data
line and two hand-shake lines. 1 he "13" port can be split between the parallel port
connector and the 5-100 bus vectored interrupts lines by jumper options. This allows the
port to be used as an additional paralJel port, an interrupt controller, or both of the
above. In the output mode the parallel ports can drive one TTL load.
2.6
REAL TIME INTERkUPT LLOCK
A 6MHz 280B eTC is used for providing a real time system clock for tvlP /M or TurboDOS
operating systems. Three channels of the eTC are available to the user for jumpering to
synchronous baud rates or long clock times.
2.7 S-IOO BUS
IN1ERFACE
The 5-100 bus interface provides the signals necessary for an 8-bit bus master as
described by the lEEE-696 bus specification. Vectored interrupt lines VIO- V 17 are
supported via jumper options (refer to section I V) and A 16-A23 are also supported via an
1/0 port. The Phantom line is also implemented for the dynamic RAM array.
The SUPEl{ SlX interface with the S-1 00 bus is depicted in Figure 2-1.
TurboJ..)O~ is the registered trademark of Software 2000, Inc.
CP/M and MP /M are the registered trademarks of Digital i{esearch, Inc.
-5-

I
(j\
I
CONNECTOR
J2
P~RALLEL
PORTS
CLOCK
DATA
RECEIVERS/
DRIVERS
JUMPERS
DMA
EPROM
2K,4K
VI
LINES
5.:100
ADDRESS
DRIVERS
CONNECTOR
J3
CONNECTOR
J1
FLOPPY DISK
CONTROLLER
CPU
5-100 BUS
-CONNECTOR
J4
RAM ARRAY
64K
A
Figure l.~ I. SUPER SIX Interface to the S-100 Bus
SERIAL PORTS
CONNECTOR
J5
B
RAM ARRAY

2.8 BAUD RATE JUMPER
Upon SUPER
SIX initialization, the baud rate for the two serial channels can be
hardware-selected independently by means of the baud rate jumper (J7). This 7-pole
jumper is located between U70 and U68 and is divided into two sets of jumpers containing
four and three pins for 510 channels A and B, respectively. Pins 7, 6, 5, and 4 set the baud
rate for 510 channel A and are designated as A, 5, C, and D, respectively; pins 3, 2, and I
set the baud rate for 510 channel B and are designated as A, B, and C, respectively.
Because this jumper comprises of only seven pin sets, SIO channel B has a hardware
limitation of 1200 baud; by means of port 18 the software may be set to allow up to 19.2K
baud for
channel B. The baud rate settings, as determined by this jumper, are shown in
Table 2-1, below. Once the SUPER SIX is initialized, I/O port 18 is used to modify the
baud rate. Port 18 is described in subsection 3.2.21.
BIT
BIT BIT BIT BAUD
D C B A RATE
0 0 0 0 50
0 0 0 I 75
0 0 I 0 110
0 0 I I 134.5
0 I 0 0 150
0 I 0 I 300
0 I I 0 600
0 I I 1 1200
I 0 0 0 1800
I 0 0 I 2000
1 0 I 0 2400
I 0 1 I 3600
1 1 0 0 4800
I I 0 I 7200
I I I 0 9600
I I I I 19,200
Table 2-1. SUPER SIX Baud Rate Jumper Settings
2.9 EPROM AND MONITOR
OPERATION
The on-board EPROM occupies addresses FOOO-FFFF (hex). This EPROM is switched ON
automatically during RESET or POWER-ON. It contains the serial input/output (510) and
floppy disk controller (FDC) initialization code along with a simple debugger and floppy
disk
cold-start loader. After the operating system is loaded the EPROM can be turned
OFF to allow access to the RAM at address FOOOH-FFFFH. The EPROM can be enabled
or disabled at any time to permit the calling of hardware dependant lio routines.
2.9.1 EPROM
Enable/Disable
A listing of· the program required to enable and disable the EPROM is provided below
/
-7-

BAUD RATE JUMPERS
ADVANCED DIGITAL CORPORATION SUPER SIX SUPPLEMENT
Update for Page 7
With the Super Six component side facing you and the S-100 cunnector down there
are 7 jumpters between U68 and U70 aligned vertically. There are assigned as
follows:
<I III
bit
A
1111
bit
B
JUMPER INSTALLED 1
1111 bit
C
1111 bit
D
JUMPER OFF = 0
console -SIO CR. A=
-SIO CR. B=
~III1
bit
A
1111 bit
B
1111 bit
C
Bit D for SIO CR. B is not available as a jumper and must be set in software.
Bit 7 of this input port (port 15) is instead used to sense double sided drives.
Some software reads this bit and sends it to the SIO CR. B baud rate anyway. If
you have double sided drives, this will make the bit a 0 thru creating baud rates
from 50 to 1200. If you have single sided drives, this will make the bit a 1
and create baud rates from 1800 to 19.2K. If you experience a problem with this
you can make a file under cpm to correctly assign the baud rate to SIO CH. B
(used for serial printer and/or modem) as follows:
Console
SIO CR. B
(ON )
(ON )
(ON )
(ON )
(ON )
(off)
(ON )
19.2k
= 300
A)ddt
-a100
in 150100
0102
ani 7f (for 50 to 1200 baud. for 1800 to
19.2k type ori 80)
0104
0106
0109
-gO
out 18
jmp 0
(CR)
A)save 1 setbaud.com
A}setbaud
COMMON BAUD RATE SETTINGS
Console
SIO CR. B
(ON )
(ON .)
(ON )
(ON )
(ON )
(ON )
(ON )
19.2k
=1200
7A
Console
(off)
(ON )
(ON)
(ON)
9600
Console
(ON )
(ON )
(ON)
(off)
12

2.9~1.1 Enabling'the EPROM:
·F03J 3E4F
MVI A,OIOOIIIIB
F035 0316
OUT 16H
2.9.1.2 .
Disabling the EPROM: .
F0333E4F
MVI A,O 110 IIII B
F035 0316
OUT 16H
;RESET POWER
ON JUMp· AND
ENABLE MEMORY, EPROM ON
;WRITE TO CONTROL PORT
;RESET POWEl{ ON JUMP AND
ENABLE MEMORY, EPROM OFF
;WRITE.TO CONTROL PORT
Jumper R25 configures the board to accept a 2716 or 2732 EPROM (as described in
section IV).
2.9.2
. NOTE: The EPROM is always dooressed at
location F800 (hex) and can not be moved.
Since the 2716 EPROM is 2K long it appears
twice, at location F800-FCOO (hex) and at
location FBFF-FFFF (hex).
Moni tor· Sign-on
The
monitor signs-on with the following messages:
2.9.3
, . .
ADVANCED DIGITAL CORP.
Monitor Version 3.6
. April -1983
Press "H'"
for help
Monitor Commands
The
monitor commands are shown in table 2-2.
-8-

COMMAND
B
D ssss qqqq
F ssss qqqq
bb
GAAAA
I pp
L
aaaa
M ssss qqqq dddd
o pp dd
ESC
FUNCTION
Loads
the disk-boot loader
Dumps memory in hex starting at user-specified address
ssss and ending at user-specified address qqqq
Fills
memory from user-specified address ssss to
user-specified address qqqq with bb
Goes
to address AAAA
Input
to user-specified port pp
Load~ memory starting at user-specified address aaaa
Moves the contents of user-specified starting address
ssss through user-specified ending address qqqq to the
user-specifiea starting address of dddd
Output user-specified data dd to port pp
Terminates any command
Table 2-2. Monitor Commands For the SUPER SIX
The cold-start loader will select and home drive O. 1 rack 0 sector 1 will be read into
memory at location o. Single density is assumed for track O. If an error occures an error
code will be printed. The error code must be translated using the table in appendex G.
-~- .

2.9.4 Cold Start Program
The cold start program is listed below.
F4B53EOD
F4B7D30C
F4B900
F4BA DBOC
F4BC OF
F4BD DABAF4
F4CO 00
F4Cl 00
F4C200
F4C300
F4C43E03
F4C6030C
F4C800
F4C9DB14
F4CB 00
F4CC OBOC
F4CE E604
F4DO CACCF4
F4D3 AF
F4D46F
F4D567
F4D63C
F4D7 D30E
F4D93E8C
F4DB D30C
F4DD 00
F4DE DB14
F4EO B7
F4El F2EBF4
F4E4
DBOF
F4E677
F4E723
F4E8 C3DEF4
BOOT 5:
MVI A,018H
;i<EAO 1
HACK 0 SECTION I INTO
ME.MOHY
OWT WAIT ;set double for 5 inch
BOOT:
MVI
A,ODH ;RESET
FDe
OUT
FDC
;ISSUE COMMAND
NOP
FOCW 1:
IN FOC
;CHECK BUSY
RRC
JC
FDCWI
NOP
;KILL TIME
NOP
NOP
NOP
MVI
A,3
;GET A RESTORE
OUT FDC
;lSSUI; COMMAND
NOP
IN
WAIT
;WAIT~FOR
NOP
;INTRQ
TKO:
IN
FDC
ANI
4 ;CHECK TRACK 0
JZ
TKO
XRA A
MOV L,A
;POIN1 AT LOC 0
MOV
H,A
INR
A
OUT
FDCSEC ;SET SECTOR
MYI
A,08CH ;GET
READ COMMAND
OUT
FDC
;lSS':LECOMMAND
NOP
.~
I
FDCRD:
IN
WAIT ;WAIT FOR
Il'ITRQ
.ORA-
A ;Orr-DR0
JP
BOOTDN
JE~Jt IF IN TRQ
IN FDCOA T A= ;GE:r DATA
MOV M,A
;STG)Rt.
INX H ;PO)NT NEXT
JMP
FDC~D
-
-10-

F4EB OBOC
F4EO 87.
F4EE CAOOOO
F4F 1 F5
F4F2210FF6
F4F5 COE6FO
F4F8 Fl
F4F9 C021Fl
2.10
IN
ORA
JZ
PUSH
LXI
CALL
POP
CALL
BOOTON:
Foe ;CHECK ~ lA TUS
A
;0 =NO ERROR
o ;OK, GO
PSW ;SAVE ERROR
H,BTERR ;PRINT
MSG ;OISK ERROR
PSW ;GET ERROR
THXB ;PRINT IT
RAM ORGANIZATION
The SUPER SIX 128K RAM is configured as shown in Figure 2-2.
U55
U46
U47
U57
U4B
U56
U5B U49 U50
U60
U51
U59
U61 U52
U53
U63
U54
U62
Figure 2-2. SUPER SIX RAM Configuration
The first 64K bank of RAM comprises of U46, U47, U48, U49, U51, U52, U54, U53, and
U50; U46 is
the parity chip.
2.11 Z80A OMA FEATURES
The Z80A
DMA performs transfers, searches and search/transfers on a full-byte basis in
burst or continuous modes. The cycle length and edge timing can be programmed to
match the speed of any port. A bit maskable byte search can be performed either
concurrently with transfers or as an operation itself.
2.12
PSNET/IOPERATION
This paddle card converts TTL to RS232 levels. Pin 6 of the 14 pin connector on the card
represents TXD; pin 7 is R TS*; pin 8 is OTR*; pin 5 is CTS*; 1 is DCD* (normally GND); 3
is RNG* optional; 2 is OSR*; 4 is RXO. Only pins 3, 5, 20, 2, and I are required for most
printers or CRT's. Printers employing the BUS Y line must be tied to pin 20 of the OB-25
connector on PSNET/1. A PSN ET /1 schematic is provided in Appendix L.
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2.13 PSNET/PAR
This paddle card connects the SUPER SIX parallel 1/0 to a Centronics printer or any other
device that requires buffered signals. Note that a DB-25 connector is used to simplify the
connection for the back panel of the 5-100 system. Thirteen wires are required between
the OB-25 and the printer. A PSN ET IPAR schematic is provided in Appendix M.
2.14 SYNCHRONOU!) OPERATIONS
If synchronous operation is required, the CTC channels (all four) are unused; the jumper
option on Hand T can be used to bring external clock into the SlOe The 14 pinconn~ctors
(J4 and J5), pins J and 11, are not used and can be employed for RNG. SIO pins 13 and 14
are connected 01) the SUPER ~IX board and must be cut for synchronous operation.
2.15 POWER C0f'.45UMPTION
+8V
+/-16V
2.8 Amp typical
250 rna
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3.1
SECTION III
INPUT/OUTPUT PORTS
INPUT/OUTPUT PORT ASSIGNMENTS
Input/Output port assignments are shown in Table 3-1:
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
15
16
17
18
19
lA
IB
ADDRESS FUNCTION
Read/Write
SIO channel A Data port
Read/Write
SIO channel A status/control port
Read/Write
SIO channel B Data port
Read/Write
SIO channel B status/control port
Read/Write
PIO cha~nel A Data port
Write PIO channel B Data port
Read/Write
PIO channel A control port
Write PIO
channel B control port
Read/Write
CTC channel 0 control port
Read/Write
CTC channell control port
Read/Write
CTC channel 2 control port
Read/Write
CTC channel 3 control port
Read/Write
FOC command/status port
Read/Write
FDC Track register
Read/Write
FOe sector register
Read/Write
FOC data port
Read/Write
OM A control port
Read/Write
Same as port 10
Read/Write
Same as port 10
Read/Write
Same as port 10
Read/Write FOe synchronization/Drive/Density
Write
S-IOO bus extended address A16-A23
Read
On-board Baud Rate jumpers
Write On-board memory
control port 110
Write On-board memory control port III
Write
Set Baud Rate
Write
Same as port 18
Write ,
Same as port 18
Write
Same as port 18
Table 3-1. I/O Port Assignments for the SUPER six Board
Note: All Address in
table 3-1 are listed in Hex.
The unused
input/output ports are internally
decoded and should ntit be used by external S-IOO
I/O boards.
The individual
ports are described in detail in the following subsection.
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3.2
I/O POR T DESCRIPTIO NS
This subsection discribes the function of all SUPER SIX I/O ports.
3.2.1
Port 00
This read/write port acts as the serial input/output channal A data port and is described in
de"tail in Appendix A.
3.2.2
Port 01
This read/write port acts as the serial input/output channel A status/control port and is
discribed in Appendix A.
3.2.3
Port 02
This
read/write port acts as the serial input/output channel B data port and is discribed in
detail in Appendix A.
3.2.4
Port 03
This read/write port acts as the serial input/output channel B status/control port and is
described in detail in Appendix A.
3.2.5
Port 04
This read/write port acts as the parallel input/output channel A data port and is discribed
in detail in Appendix B.
3.2.6
Port 05
This
write-only port acts as the parallel input/output channel:g data po~t and is
described in detail in Appendix B. This port can be jumpered to the S-IOO vectored
intercept lines onto connector J2 (refer to Section IV).
3.2.7
Port 06
This
read/write port acts as the parallel input/output channel A control. is discribed
in detail i~ Appendix B.
3.2.8
Port 07
This
write-only port acts as the parallel input/output channel B control port and is
described. in detail in Appendix B. This port can be jumpered to the S-IOO vectored
interrupt lines onto connector J2 (refer to ~ection IV).
3.2.9
Port 08
This
read/write port acts as the counter/timer circuit channel zero control port and is
discribed in detail in Appendix C.
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