Advanced Micro Computers Am96/4116A User manual

Advanced
Micro
Computers
Asubsidiary of
Advanced Micro Devices
Am96/4116A
AmZ8000 16-Bit
MonoBoard™ C~omputer
User's Manual
059910090-001
$10.00

REVISION RECORD
REVISION DESCRIPTION
01 Preliminary Issue
(8/28/81)
AManual Released
(10101/81)
-----
------
--
.-
Publication No.
059910090-001
Address comments concerning
this manual
to:
REVISION l.ETTERS I, 0, aAND xARE NOT USED
© 1981 Advanced Micro Computers
Printed
in U.S.A.
ii
ADVANCED MICRO COMPUTERS
Publications Department
3340 Scott Boulevard
Santa Clara, CA
95051

PREIFACE
This manual provides general information, an installation and interface
guide, programming information, principles of operation, and service
information for the Advanced Micro Computers Am96/4116A MonoBoard
Computer. Additional information concerning components of the
Am96/4116A is available in the following documents:
•
AmZ8001/2 Processor Instruction Set
•Zilog, Z80Dl CPU/Z8002 CPU Product Spec.
•
AMD Shottky and Low Power Shottky Data Book
• Am8251-Am9551 Data Sheet
• Am8255A/Am8255A-5 Data Sheet
•
Am9513 Data Sheet
•
Am9513 Application Brief
• 8259A Data Sheet (Intel)
•Multibust Interfacing (Intel Application
Note AP-28J\)
In this manual, both active-high (positive true) and active-low
(negative
true) signals appear in the text. To eliminate confusion and
simplify presentation, the following convention is used throughout this
manual·: The mnemon'ic for asignal that is active-low is followed by an
asteri sk (i. e. MEM:R*) • The mnemon ic for an act ive-h i gh signal is
denoted without the asterisk suffix.
Common mnemonics and acronyms are used without additional explanation.
The fi rst time anon-standard or uncommon acronym is used, its full
name wi 11 be spe 1"1 ed out and the acronym enclosed in parenthes is.
Following references will use the acronym without further explanation.
The information in this manual is believed to be accurate and complete
at the time it was printed. AMC reserves the right to change
specifications without notice. No responsibility is assumed for errors
that might appear in this manual.
No part of this manual may be copied or reproduced in any form without
prior written permission from AMC.
tMultibus' a registered trademark of Intel Corporation
iii/iv

TABLE OF ~CONTENTS
1. GENERAL INFORMATION ••••••••••••• l-l
Introduction •••••• ~ ••••••••••••• I-1
Physical Description
•••••••••••• l-l
Functional Description •••••••••• 1-2
Specifications •••• G ••••••••••••• 1-5
2.
INSTALLATION AND INTERFACE •••••• 2-1
Introduction •••••• G ••••••••••••• 2-1
Unpacking and Inspection •••••••• 2-1
Power Requirements~ ••••••••••••• 2-1
Cooling Requirements •••••••••••• 2-1
User Selectable Options ••••••••• 2-2
Memory Expansion ..... '" ••••••••• 2-2
Starting Address of
On-Board RAM ••• o ••••••••••••• 2-3
Wait State for Slow ROMs •••••• 2-3
Serial I/O Peripheral
Interface Clock Select ••••••• 2-4
Baud Rate Selecto ••• ~ ••••••••• 2-4
Customizing
Data Set
Operation
•••••••••• ~ ••••••••• 2-4
Auxiliary Connector
P2 •••••••• 2-5
Interrupt Jumpers ••• ~ ••••••••• 2-6
Parallel I/O Interface •••••••• 2-7
Enable Real-Time
Clock •••••••• 2-9
On-board
ROM Type Se'lection•••2-9
System Bus Priority.G ••••••••• 2-9
Initialize/Power Up Reset ••••• 2-9
Bus Clock (BCLK) and
Constant Clock (CCLK)
Jumpers •••••••••••• o ••••••••• 2-9
Dual Port RAM Access •• ~ •••••••• 2-10
Interface Requirementso •••••••• 2-10
Bus Interface ••••••••• G •••••••• 2-10
DC Bus Characteristicso •••••••• 2-10
3.
OPERATION AND PROGRAMMING ••••••• 3-1
.Introduction •••••••••• o ••••••••• 3-1
I/O Address AssignmentG ••••••••• 3-1
Shared
Memory and the r1ul t i bus ••3-1
Block-Select Memory Expansion•••3-2
ROM Addressing •••••••• o ••••••••• 3-2
Serial I/O Interface
Programming •••••••••• o ••••••••• 3-4
Am9551 Initialization ••••••••• 3-4
Am9551 Mode Instruction Word
Format ••••••••••••••••••••••• 3-5
Am9551 Sync Characters •••••••• 3-5
Command Instruction Word
Format •••••••• ~ •••••••••••••• 3-5
Am9551 Status Read •••••••••••• 3-6
Parallel I/O Interface
Programming •••••••••••••••••••• 3-8
Am8255A Addressing •••••••••••• 3-8
Am8255A Initialization •••••••• 3-8
Am8255A Operation Control
Word Format ••••••••••••••••• 3-11
Am8255A Bit Set/Reset Control
Word •••••••••••••••••••••••• 3-11
Interrupt Control Programming •• 3-12
Initialization ••••••••••••••• 3-12
Operation Control
•••••••••••• 3-14
System
Timing Controller
Programming ••••••••••••••••••• 3-17
Command Register ••••••••••••• 3-17
Status Register •••••••••••••• 3-18
Master
Mode Register ••••••••• 3-19
Time of Day •••••••••••••••••• 3-20
Comparator Enable
•••••••••••• 3-21
FOUT Source •••••••••••••••••• 3-22
FOUr Divider ••••••••••••••••• 3-22
FOUT Gate •••••••••••••••••••• 3-22
Bus Width •••••••••••••••••••• 3-22
Data
Pointer Sequencing •••••• 3-22
Scaler Ratios •••••••••••••••• 3-23
Frequency Scaling Counter
•••• 3-23
FOUr Divider Counter ••••••••• 3-24
Data Pointer Counter ••••••••• 3-24
Prefetch Latch
••••••••••••••• 3-25
Counter Logic
Groups ••••••••• 3-26
Counter
Load Register •••••••• 3-26
Counter
Hold Register •••••••• 3-27
Counter Mode Register •••••••• 3-27
Output Control
••••••••••••••• 3-28
Count Control •••••••••••••••• 3-29
Count Source Selection ••••••• 3-30
Gating Control
••••••••••••••• 3-31
Alarm Registers and
Comparators ••••••••••••••••• 3-31
Output Control Bit ••••••••••• 3-32
Baud Rate Programming •••••••••• 3-32
v

4. THEORY OF OPERATION ••••••••••••• 4-1
Introduction •••••••••••••••••••• 4-1
Central Processing Unit
(CPU) ••• 4-1
Random Access Memory •••••••••• 4-5
ROM/EPROM ••••••••••••••••••••••• 4-5
Memory Expansion •••••••••••••••• 4-5
Serial
I/O Interface •••••••••••• 4-6
Parallel I/O Interface •••••••••• 4-8
Interrupt Controller •••••••••••• 4-9
System Timing Controller ••••••• 4-10
5. SERVICE INFORMATION ••••••••••••• 5-1
Introduction •••••••••••••••••••• 5-1
Service
and Repair Assistance••• 5-1
Service Diagrams •••••••••••••••• 5-1
FIGURES
1-1. Am96/4116A MonoBoard Computer,
Block Diagram ••••••••••••••• 1-3
2-1.
Off-Boa rd Memory Expans i on
Using Normal/System and
Code/Data Signals ••••••••••• 2-3
2-2.
Parallel I/O Line
Terminator
•••••••••••••••••• 2-7
3-1.
Am96/4116A to Multibus
Interface ••••••••••••••••••• 3-3
3-2.
Memory Expansion ••••••••••••• 3-3
3-3.
Am9551 Synchronous Mode
Control Code •••••••••••••••• 3-6
3-4.
Am9551 Asynchronous Mode
Control Code •••••••••••••••• 3-6
3-5.
Am9551 Command Instruction
Word Format ••••••••••••••••• 3-7
3-6.
Am9551 Status Word Format •••• 3-8
3-7. Am8255A Operation Control
Word Format •••••••••••••••• 3-11
3-8. Bit Set/Reset Control
Word
Format ••••••••••••••••••••• 3-12
3-9.
Initialization Control Word
(ICW) Formats •••••••••••••• 3-13
3-10. Operation Control
Word
(OCW) Formats •••••••••••••• 3-15
3-11. Rotating
Priority Mode A
(Automatic Rotation)
••••••• 3-16
3-12. Status Register Bits •••••••• 3-18
3-13. Master
Mode Register Bits•••3-20
3-14. Time-of-Day Configurationo •• 3-21
3-15. Frequency Scaler Ratios ••••• 3-23
3-16. Data Pointer Counter
•••••••• 3-24
vi
3-17. Counter Mode Register Bit
Assignments
•••••••••••••••• 3-28
3-18.
TC Waveform Format •••••••••• 3-29
4-1.
Am96/4116A MonoBoard
Computer, Block Diagram ••••• 4-2
4-2. CPU Memory Operations •••••••• 4-4
4-3. Processor-to-Processor
Transfer via
Memory ••••••••• 4-5
5-1.
Am96/4116A MonoBoard
Computer, Component
Locations ••••••••••••••••••• 5-2
5-2.
Am96/4116A MonoBoard
Computer, Schematic
Di agram ••••••••••••••••••••• 5-3
5-3.
Am96/4116A MonoBoard
Computer, Schematic
Diagram ••••••••••••••••••••• 5-4
5-4.
Am96/4116A MonoBoard
Computer, Schematic
Diagram ••••••••••••••••••••• 5-5
5-5.
Am96/4116A MonoBoard
Computer, Schematic
Diagram ••••••••••••••••••••• 5-6
5-6.
Am96/4116A MonoBoard
Computer, Schematic
Diagram ••••••••••••••••••••• 5-7
5-7.
Am96/4116A MonoBoard
Computer, Schematic
Di ag ram ••••••••••••••••••••• 5-8
5-8.
Am96/4116A MonoBoard
Computer, Schematic
Diagram ••••••••••••••••••••• 5-9
5-9.
Am96/4116A MonoBoard
Computer, Schematic
Diagram •••••••••••••••••••• 5-10
5-10.
Am96/4116A MonoBoard
Computer, Schematic
Diagram •••••••••••••••••••• 5-11
5-11.
Am96/4116A MonoBoard
Computer, Schematic
Diagram •••••••••••••••••••• 5-12
5-12.
Am96/4116A MonoBoard
Computer, Schematic
Diagram •••••••••
o
•••••••••• 5-13
5-13.
Am96/4116A MonoBoard
Computer, Schematic
Diagram •••••••••••••••••••• 5-14

TABLES
1-1. Specifications ••••••••••••••• 1-5
2-1. Address Paging Jumpers ••••••• 2-2
2-2.
Serial I/O Jumpers ••••••••••• 2-4
2-3. ConneGtor
P4 and P5 to
Terminal Connector Pin
Assignments ••••••••••••••••• 2-5
2-4.
P2 Connections ••••••••••••••• 2-5
2-5.
Non-Maskable Interrupts •••••• 2-6
2-6.
Priority Interrupt Jumpers •••2-6
2-7. Parallel I/O Port A and B
Jumpers ••••••••••••••••••••• 2-7
2-8.
Parallel I/O Socket
Compatible Line Drivers
••••• 2-8
2-9.
2-10.
2-10.
2-11.
2-12.
3-1.
3-2.
3-3.
3-4.
3-5.
Parallel I/O Connector P3 ••••• 2-8
ROM Type Jumper Selection ••••• 2-9
Am96/4116A Connectors ••••••••• 2-10
System Bus Connector PI
Pin Assignments ••••••••••••• 2-11
Am96/4116A Bus DC
Characteristics ••••••••••••• 2-12
I/O Port Address •••••••••••••• 3-2
Parallel I/O Port
Configuration
Summary •••••••• 3-9
Control Element
Summary •••••• 3-17
Command Summary •••••••••••••• 3-19
Baud Rate Selection •••••••••• 3-32
vii

CHAF)TER 1
GENERAL INFORMATION
INTRODUCTION
The Am96/4116A MonoBoard Computer (MBC) is acomplete, AmZ8002 based,
16-bit, microcomputer on a single board. It is plug compatible with
the Intel Multibus board product interface. The Am96/4116A offers the
following features:
• High performance, AmZ8002, 16-bit microprocessor.
•Supports up to ei ght ki 1obytes of on-board RO~1. Two sockets are
provided with jumper selectable addressing for 2K, 4K, or 8K
bytes.
• Under software control, addresses for on-board shadow RO~1 are
mapped to off-board RAM.
•Supports up to 32 k i"\ obytes of on-board dynami cRAM.
•Two-port confl! gurat i on of RAM. RAM can be si mul taneous1y
accessed by the AmZ8000 and the Multibus. If both are
attempting continuous access, 50% interleave results.
•Eight fully-programmable, vectored, priority interrupt channels
wi th provi sions for software generated interrupts. 24 source s.
• Two Ser;a1 Communi cat ions Interfaces, one wi th full RS232C
support and the other with modified RS232C support.
• A parallel I/O interface with two 8-bit ports and two 4-bit
ports socketed for drivers or receivers.
•Programmable Timer for on-board time-of-day clock and delayed
interrupts.
PHYSICAL DESCFIIPTION
The Am96/4116A MonoBoard Computer (MBC) is a four-layer printed circuit
board with MSI TTL and LSI MOS circuits. Five edge connectors provide
bus
and peripheral interface capabilities. Physical characteristics of
the Am96/4116A are:
1-1

Board Dimensions:
Width
Depth
Thickness
30.48
cm (12.00 inches)
17.15
cm (6.75 inches)
1.50
cm (0.60 inches)
Environmental Requirements:
Operating Temperature
O°C to 55°C
Relative Humidity Up to 90% without condensation
Storage Temperature
-40°C to +75°C
FUNCTIONAL DESCRIPTION
The Arn96/4116A 'MonoBoard Computer contai ns an ArnZ8002 CPU, two Arn9551
serial ports, one Am8255A parallel I/O port, an Am9513 timer, an 8259A
interrupt contro 11 er, 32 k il ob.ytes of RAM, two sockets for 2K, 4K, or
8K of ROM, and various TTL circuits. The board is compatible with the
Multibus
interface requirements. The ArnZ8002 CPU is an advanced
architecture, 16-bit microprocessor with an instruction set more
powerful than many minicomputers. There are sufficient resources, such
as sixteen 16-bit general purpose registers, seven data types, eight
addressing modes, and 110 distinct instruction types. The 110 distinct
instructions can be combined with the various data types and addressing
modes to expand the instruction set to 414 instructions. Most
instructions can use any of the five addressing modes and can operate
on byte (8-bit), word (16-bit), and long-word (32-bit) data, types.
Figure 1-1 is ablock diagram of the Am96/4116A.
Selection of ROM is optional. Two sockets are provided to accommodate
ROM" The ROM type can be Arn2708 or Arn2758 (2 ki1 obytes), Arn2716 or
Am9218 (4 kilobytes), or Arn2732 or Am9233 (8 kilobytes). Jumpers are
provided to select the correct ROM addressing scheme to accommodate the
various
ROMs. Addresses for the Am2708 range from 0through 07FFH; the
Am2716 addresses range from 0through OFFFH; and the Arn2732 addresses
range
from 0through 1FFFH.
The ROM addressing range is 8,192 bytes. If 2kilobyte or 4kilobyte
ROM is impl emented, the unused address space, from 0800 to 1FFFH or
1000 to 1FFFH, for 2kilobyte or 4kilobyte ROM, respectively, will be
mapped to off-board RAM.
A'll ROM on the Arn96/4116A MonoBoard Computer is Shadow ROM. AWrite
instruction addressed to port FFFOH disables on-board ROM and causes
memory access to addresses 0through 1FFFH to be mapped to off-board.
Either ROM or RAM can be used as off-board memory; both read and write
operations at the off-board memory are allowed, even though a wri te
operation when ROM is used is meaningless. AWrite instruction
addressed to port FFF1H enables the on-board ROM. When first
powered-up, ROM is enabled. Shadow ROM and RAM can occupy the same
1-2

P3
P4 P5
+.
+.
+. +.
II
BIDIRECTIONAL IBIDIRECTIONAL DRIVER ANDlOR RS232C RS232C
BUFFER BUFFER TERMINATION INTERFACE INTERFACE
i
f8
844I
PA0-7
PBO-7 PC0-3 PC4-7
Am9S55A Am9551
Am9S51
PARALLEL 110
SERIAL 110
SERIAL 110
CLOCK
I--
t
,v 8t ,v 8I
... "" 816-BIT
16 16 ADDRESS
•
r-f-
ADDRESS
~ ADDRESS
RESET BUFFER ,BUFFER
t----
CIRCUITS
r--
I I
MULTI-
AmZ8002 MASTER
CONTROL
t16-BIT
16
DATA DATA DATA
~
~
BUFFER
f16
+ 16
+16
f8
BUFFER
RAM 32K ROM Am9513 8259A
BYTES SYSTEM TIMING INTERRUPT
DUAL-ACCESS
21418 KBYTES CONTROLLER CONTROLLER
f8
I ..... I
INTERRUPT
JUMPER PINS
P2
P1
Figure 1-1.
Am96/4116A MonoBoard Computer, Block Diagram

physical address space. It is possible to write to RAM, but RAM can
only be accessed for read when the shadow ROM is disabled. This
permi ts all or portions of ROM to be copi ed to RAM and then the ROM
turned off.
There are 32K bytes of dynamic RAM included on the Am96/4116 board,
configured as two-port (dual access) memory. Sixteen 16,384 by 1,
N-channel dynamic R/W RAMs are used. With 200 nanosecond RAMs, no watt
state is needed.
RAM can be simultaneously accessed from the Multibus interface and the
AmZ8002 CPU. Access arbi trat i on for two-port operati on provides 50
percent interleave of ArnZ8002 and Multibus access. Control defaults to
the
AmZ8002 if no Multibus requests are active.
An 8259A provides an eight channel vectored priority interrupt system.
The eight channels can be programmed to perform priority resolution on
either afixed or rotating basis in either an interrupt or polled mode,
allowing the user flexibility to establish interrupt service priorities
based upon individual requirements.
The eight inputs to the 8259A are jumper selectable from an interrupt
matrix. Selection can be from eight gated Multibus interrupts, four
serial port (Am9551) interrupts, one parallel port (Am8255A) interrupt,
and interrupts from the timer chip (Am9513).
Non-maskable interrupts are also produced and are, Multibus power fail,
timeout for AmZ8002 access to Multibus, selected interrupt from
interrupt matrix, and odd word trap.
The system contains one Arn8255A Programmable Peripheral Interface
containing three parallel I/O ports. Two 8-bit ports are buffered with
bidirectional buffers. The buffer direction for each port is selected
by jumper to provide either input, output or dynamic direction control
using a bit from one of the two 4-bit ports. The remaining port on the
Am8255A is configured as two 4-bit ports socketed for drivers or
receivers (optional). Signals from each 4-bit port are used as
interrupt signals at the interrupt matri x. The I/O 1i nes are brought
out
at the 50 pin connector P3 at the top of the board.
Two Am9551 Programr.1able Communications Interfaces provide two serial
I/O ports. One of these ports supports a full RS232C interface. The
other supports amodified RS232C interface where, Data Set Ready, and
Clear to Send signals ar'e omitted. The Am9551 provides full duplex,
buffered transmi t
and recei ve capabi 1 it i es. A programmable baud rate
generator provides baud rates between 50 and 9 ,600 baud for
asynchronous data transmission, and up to 38,400 baud for synchronous
operation. Each communications interface can be programmed to
implement the desired synchronous or asynchronous serial data protocol.
Data format, control character format, and pari ty are under program
control. Parity, overrun, and framing error detection are all
incorporated on the programmable communications interface. Command and
control lines, serial data lines, and signal ground lines are brought
out
to P4 and P5 at the top the board.
1-4

The system includes an Am9513 System Timing Controller to enhance
system
capability with respect to counting and timing operations. It
provides the capability for programmable frequency synthesis, complex
waveform
generation including programmable duty cycles, digital
one-shots, time-of-day clocking including alarms, pulse generation,
baud rate generat ion" frequency shi ft keyi ng, stop watch t imi ng, event
count accumulation,
and many more applications. The Am9513 can be
dynamically reconfigured under program control. Source, gate, and
output 1ines are brought out to connector P2 at the bottom of the
board.
SPECIFICATIONS
Specifications for the Am96/4116 MonoBoard Computer are listed in table
1-1.
TABLE 1-1. SPECIFICATIONS
Word Size I nstruct I on:
Data:
1 word (16 bits) to 4 words (64 bits)
byte (8 bits), word (16 bits), or long word
(32 bl ts)
Memory Addressing
On-board ROM/EPRa.1: Q-7FFH (2708 chips)
O-OFFFH (2716 chips)
0-1 FFFH (2732 ch Ips)
On- board RAM:
Of f- boa rd Memory:
800o-FFFFH
or 000Q-7FFFH
0000-7FFFH or 8000-FFFA-f
Any 32K
space not occupied by on-board RAM.
Memory Capacity
On- board ROM/EPRa.1: 2 sockets for up to 8K bytes
2708 E-PRa.1 or 2758 ROM
2716 E-PROM or 9218 Mask ROM
2732 E-PROM or 9233 Mask ROM
2K bytes
4K bytes
8K bytes
On- board RAM: Dynaml c, 32K bytes
1-5

TABLE 1-1. SPECIFICATIONS (continued)
Shadow ROM A Wr Ite canmand to I/O port FFFOH dI sab les
address I ng on-board Rav1 and causes ROM ad-
dresses 0 to 8K to be mapped to of f- board
RAM. AWrite to I/O port FFF1 enables on-
board
RQ\1.
RAM Access Type of Access:
2-port (Dual Access)
Walt
States: No wait states for access from Aml8002
Access Time from 1350-3275 nanoseconds
Multlbus, Command to
XACK Time:
w/2
port RAM lock: First Access:
Subsequent Access:
1350-3275 ns
737-1087 ns
Multlbus Interface Clocks:
BCLK and CCLK jumperable
Exchange Capability: Serial priority on-board
Paral lei pr lorlty off-board
Bus Lock: Wr Ite to I/O port FFF9H locks the bus to
exclude other access. Write to I/O port FFF8H
un locks the bus.
Multibus Interrupts: Non-bus vectored Interrupts are supported and
may be Implemented with the following
options:
Interrupts are always
jumpered.
recognized
when
J.L9 Port Functions Single Step Enable:
Bus
vectored Interrupts are not supported.
FFCOH
1-6
Interrupt Contro II er Data:
FFC8H
Control: FFCAH
(Am8259A) :
Timer (Am9513):
Data:
FFDOH Control: FFD2H
Serl"al I/O Port
#1
Data:
FFD8H Control ::
FFDAH
(Am9551 ):
Serial
I/O
Port
#2
Data:
FFEOH
Control: FFE2H
(Am9551):'
----_ .. - ..

TABLE 1-1. SPECIFICATIONS (continued)
I/O Pc~t Functions
Pa r aI Ia I I /0
(Am8;255A) :
RO'1 Enable:
RO'1 Di sab Ie:
Multlbu5 Lock:
Multlbus Unlock:
Port Chan A:
Chan
B:
Shad~ On:
Shad
C1N Of f :
FFE8H
FFEAH
FFF1H
FFFOH
FFF9H
FFF8H
Chan C:
Control:
FFECH
FFEEH
Serial I/O Capacl!y' Synchronous:
As yn chron ous:
Baud Rate:
5 to 8 bl t characters
I nterna I or external syn chron I zatl on
Automatic sync Insertion
5 to 8 bi t characters
Break character generation
1, 1 1/2, or 2 stop bits
False start bit detector
Programmab Ie
Power Requirements
En vi ronmenta I
Characteristics
Paral lei
Ity:
+ 5V DC
+12V DC
-12V DC
I/O Capac- Two 8 bl t ports (A and B)
Two 4
bl t ports (C even and Codd) socketed
for drivers or receivers
Typical (With E-PROM devices Instal lad)
3.80A
0.10A
0.03A
0° to 55°C up to 90% without condensation
Physl~
Length:
304.80 mm
<12.00
Inches)
Character I st Ics
He I gth:
171.50 mm
( 6.57 Inches)
Thickness:
12.70 mm ( 0.50
Inches)
We I ght:
0.45 Kg (
1.00
pounds)
Sh Ipp Ing We I ght:
1.36 Kg ( 3.00
pounds)
1-7

CHAp·TER 2
IN~)TALLATION AND INTERFACE
INTRODUCTION
This chapter pY'ovides information to install an Arn96/4116A MonoBoard
Computer (MBC) in a user1ssystem. The information includes unpacking
and
inspection, and user' design information such as interface data,
power requirements, cooling requirements, bus interface
characteristics, and connector pin assignments.
UNPACKING ANCt INSPECTION
Inspect the shipping carton immed~iately upon receipt for evidence of
mishandling during transit. If the shipping carton is severly damaged
or water st'ai ned, Irequest the carri er' sagent to be present \\/hen the
carton is opened. If the carri er' sagent is not present when the
carton is opened and the contents of the carton are damaged, keep the
carton and packing material for the agent's inspection. Shipping
damages should
be immediately reported to the carrier.
NOTE
Do not attempt to service the board yourself as this
will void the warranty.
It is suggested that salvageable shipping cartons and packing ~atcrials
be saved for use in case the product must be shipped in the future.
POWER REQUIRE~MENTS
The Arn96/4116A requires +5 Vdc and ±12 Vdc power inputs. The power
supply must
be capable of supplying at least 3.8A to accommodate the
Am96/4116A requirements.
COOLING REQUIIREMENTS
The Am96/4116 di SS"j pates approximately 30 ~1 (typical). Adequate air
circulation must be provided to prevent a temperature rise above 55°C
(131°F).
2-1

USER SELECTABLE OPTIONS
The Am96/4116A is designed as ageneral purpose 16 bit micro computer;
opti
ona 1j umperi ng fac i1i ty is prov i ded to ta i1or board operati on to
specific use. Jumpers must be in the correct positions prior to bOard
operation. The following paragraphs provide instructions for optional
jumper configurations.
MEMORY EXPANSION
The Am96/4116A has the capability of bank selecting up to sixteen 32k
byte blocks of off-board memory, for a maximum of 152k bytes of
external
RAM and/or ROM. Parallel I/O port C bits 0 to 3, are used to
select the off-board memory. However, off-board memory must not occupy
the same logical address space as the on-board RAM. If on-board RAM is
in the upper 32k (8000 to FFFF hex), then off-board memory must occupy
the space from 0000 to 7FFF hex. Table 2-1 lists the jumpers
available.
TABLE 2-1. MEMORY EXPANSION JUMPERS
SIGNAL JUMPER PIN
(s)
PCO*
10
PCl*
12
PC2*
14
PC4*
16
ADRF*
62-63
ADI0*
65, 36-37
ADll*
68, 38-39
ADI2*
58, 40-41
ADI3*
59,42-43
N/S* 66
I-FETCH*
69
For exampl e, to connect PCO* to the Mul ti bus ADI0* pi n, connect a
jumper from pin 10 to 65, and ajumper from 36 to 37. To connect PCl*
to ADll*, connect ajumper from 12 to 68 and another from 38 to 39.
Two addi tiona 1 1i nes, defi ned by the CPU, are a va i1 ab 1e at jumper pi ns
. to expand the memory to a maximum of 160K bytes. The signals are
I-FETCH* (code) and N/S* (Normal/System). The I-FETCH* signal provides
the capability of having two separate areas of memory one for code and
one for data. The N/S*signal provides for two additional areas of
memory, one for system use and one for normal (user) functions. The
functions of I-FETCH* and N/S* can be combined as shown in figure 2-1.
The blocks shown in figure 2-1 can occupy the same logical area of
memory, though the physical locations will be different.
2-2

.------------,--------------------------,
U
':~2K
Normal
Code
32K
Normal
Data
32K
Normal
Code
32K
System
Data
System/Normal and Code/Data Lines
32K
Normal
Code
Data
32K
System
Code
Data
System/Nolrma 1Lines
B
32K
Norma 1
System
Code
32K
Normal
System
Data
Code/Data Lines
C
Figure 2-1. Off-Board Memory Expansion Using
Normal/System and Code/Data Signals
STARTING ADDRI:SS OF ON-BOARD RAM
On-board RAM can be located in ei ther the upper or lower 32K of the
Am96/4116 memory space. For the upper 32K byte space, connect ajumper
between
pi n 192 and 193. To locate RAM in the lower 32K byte area
reconnect the jumper between pi n 192 and 193. To locate RAM in the
lower 32K byte area reconnect the jumper between pins 193 and 194.
WAIT STATE FOI~ SLOW ROM!;
One wait state is l"equired for Rm1s with cycle time slower than 400
nanoseconds. Instaillation of jumper 186 to 187 introduces the wait
state.
2-3

SERIAL 1/0 PERIPHERAL INTERFACE CLOCK SELECT
The Recei ve Clock (RxC) and Transmi t Clock (TxC) for the two Am9551
serial I/O devices are jumper selectable. The clock inputs for serial
port 1can be jumpered together to the on-board clock source, or
separately connected to external
RxC and TxC. The clock source for
serial port 2 is on-board onlye Table 2-2 lists the jumper locations.
TABLE 2-2e SERIAL I/O JUMPERS
SIGNAL FUNCTION
JUMPER I/O CONNECTIONS
RxC-1
Ext"
Rcv Clk #1 147-161
P4-22
TxC-1
Ext"
Xmit Clk 111 146-160
P4-14
RTS-1
Request to Send #1 132-134 (Active)
P4-9
130A-134
(Ground) None
CTS-1 Clear to Send #1
133-135 (Active)
P4-7
131-133
(Ground) None
CTS-2
Clear to Send #2 180-181
(Active)
P5-7
181-179
(Ground) None
CLK-1
Baud Rate Clk #1 141-143 (9600 Baud)
None
142-143 (Prog.)
None
CLK-2
Baud Rate Clk #2 39-140 (9600 Baud)
None
138-139 (Prog.)
None
P4 is Serial Port #1.
P5
is Serial Port #2, (Modified RS232C)
BAUD RATE SELECT
The Am96/4116A baud rate is programmable us i ng two of the counters in
the
Am9513 System Timing Controller. As shipped from the factory, the
baud rate is set at 9600. Table 2-2 lists the clock source jumpers.
Tab 1e3-5 1i sts the va 1 ues for programmi ng other baud rates, us i ng
asynchronous communications mode.
CUSTOMIZING DATA SET OPERATION
The Cl ear to Send and Request to Send signa1 s, between adata set or
data terminal can be jumpered to external signals or can be jumpered to
ground (to be continuously active). Table 2-2 lists these jumpers.
Table 2-3
lists pin assignments for the serial I/O connectors, P4 (port
1) and P5 (port 2), serial port 2 is the modified RS232C port.
2-4