General Automation SPC-16/40 User manual

SPC-16/40, SPC-16/60, SPC-16/80
SPC-16/45,SPC -16/65, SPC-16/85
.maintenance manual

SPC-16/40, SPC-16/45,
. SPC-1616O, SPC-16/65,
SPC-16/80 SPC-16/85
maint nance
GENERAL AUTOMATION, INC.
1055 East Street
Anaheim, California 92805
[phone]
© 1973, 1974, General Automation, In c.
88A00234A-C

88A00234A-C
REVI
1
ION
Manager
Symbol
Description
Publications
Approved Date
A Or
igi nal Issue
~
JC·7/
:/
Oc ;: •
73
B
Ad d ed RCSR/RCSM
tiiP
/[7/
Mar. 74
Ins tructions •
C Major Revision ~
~>c ~lI
Aug. 74

SUPPORTING DOCUMENTS AND PROGRAMS
Title Number
SPC-16/40+ System Reference Manual 88A00243A
128K
Extended Memory Option Technical Manual 88A00432A
SPC-16 Processor T&V Program 6TOOO
SPC-16 Memory ' Test Programs 6T500, 6T020
SPC-16 Teletype T&V Program 6TIOO
SPC-16 Processor and Memory T&V Program Manual 88A00184A
SPC-16 Teletype T&V Program Manual 88A00185A
SPC-16 Power Supply Function Test Specification 83S0036A
...... / .

Section
1
2
3
CONTENTS
Title
PREFACE
INTRODUCTION
1.1 System Organization
1.2 General Specifications
COMPONENT IDENTIFICATION
FUNCTIONAL DESCRIPTION OF THE SPC-16 PROCESSOR
3.1 Elements of the Central Processing Unit
3.2 Console Board
3.2.1 Display Register (K)
3.2.2 Operating Indicators
3.2.3 Digital to Analog Converter (VU)
3.2.4 Data/Sense Switches
3.2.5 Control Switches
3.2.6 Register Data Entry Switches
3.2.7 Console Interrupt
3.2.8 Key Lock
3.2.9 MIB Interface Plugs
3.3 Arithmetic Board
3.3.1 Micro/Macro Selects and Sets
3.3.2 Augend Bus (AU)
3.3.3 Addend Bus (AD)
3.3.4 Arithmetic/Logic Unit and D Bus
3.3.5 General Purpose Registers Select
3.3.6 General Purpose Registers
3.3.7 P and W Registers
3.3.8 Bit Select Logic
3.3.9 Relative Time Clock (RTC)
3.3.10 Operations Monitor Alarm (O}~)
3.3.11 Q and R Registers
3.4 Master Interconnect Board (MIB)
3.5
3.4.1 SPC-16/40/60/80 MIB Connectors
3.4.2 SPC-16 45/65/85 Main MIB Connectors
3.4.3 SPC-16 45/65/85 Expanded Memory MIB
Connectors
Macro Control Board (MAC)
3.5.1 Instruction (I) Register
3.5.2 Instruction Register Decode
3.5.3 Indicators
i
33A00234--C
Page
ix
1-1
1-1
1-3
2-1
3-1
3-1
3-9
3-10
3-10
3-10
3-10
3-10
3-10
3-10
3-10
3-11
3-11
3-12
3-12
3-12
3-12
3-12
3-12
3-12
3-12
3-13
3-13
3-13
3-13
3-15
3-15
3-15
3-16
3-17
3-17
3-17

Section
4
3.6
3.7
3.8
Title
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
Timing
3.6.1
3.p.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.9
3.6.10
3.6.11
3.6.12
3.6.13
Memory
3.7.1
3. , 7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
Memory
Contents ( ontinued)
Au g end-Adde ~ d Select Functions
Register Se cl Functions
Shift Count ,r
Combination Timing
MIB Interfaae Plugs
Control Board J
Master C1oc 1
DO Clock (D I C) Timing
DO Timing
Sequence Control
Sequence Ti l ing
Combination Timing
Memory Timirrg
Programmed
Input/Output (PIO) , DMA,
I I
To °
nterrup ~ lmlng
Register Ad1ress Bus
Augend-Addefd Selects
Register Set s
Priority Interrupt Expander
MIB Interfa ! e Plugs
and I- nput/Out ut Board (MIO)
Memory Data (M) Register
Memory Addr ss (L) Register
I/O Drivers Receivers and Termination
Memory Stac f Select
System Rese and Memory Guard Relays
Serial (Te1 , type) Controller
~~~i~!t~~~~ f ~1;~:g~Ptica1 Computers
Board (MEM)
DAT.j\ F LOW
4.1 Data Flow Organizati r n
4.1.1 Arithmetic/Logic Unit (ALU)
4.1.2 Augend Bus
4.1.3 Addend Bus
4.1.4 Data Bus
4.1.5 I/O Bus
4.1.6 General Pur ose Registers
°i
Page
3"'::17
3-17
3-17
3-17
3-17
3-18
3-18
3-18
3-19
3-19
3-19
3-19
3-19
3-19
3-20
3-20
3-20
3-20
3-20
3-21
3-21
3-22
3-22
3-22
3-22
3-22
3-23
3-23
3-23
4-1
4-1
4-1
4-5
4-5
4-7
4-9
4-9

Section
5
6
TIMING
5.1
5.2
Title
. Basic
5.1.1
5.1.2
5.1.3
5.1.4
Contents (Continued)
Processor Timing
Master Clock
DO Clocks
Sequence States
Combination Timing
Operations Timing
5.2.1 Memory Timing
5.2.2 Systems Console
5.2.3 Direct Memory Access/Arithmetic
5.2.4
5.2.5
5.2.6
Control I/O
Serial I/O Interface
Priority Interrupt
Power Fail/Automatic Restart
INSTRUCTION SEQUENCING
6.1 Basic Decode
6.2 Instruction Sequence Charts
6.3 Memory Reference Instructions (MR)
6.3.1 Load Register A (LDA)
6.3.2 Store Register A (STA)
6.3.3 Jump to Subroutine (JSR)
6.3.4 Jump Unconditional (JMP)
Logic
6.4 Memory Reference with Indexing Instructions (HRX)
6.4.1 Load Register (LDR)
6.4.2 Stor~ Register (STR)
6.4.3 Compare Memory with Register (CMR)
6.4.4 Bit/Byte Mode Addressing
6.4.5 Load Byte (LDBY)
6.4.6 Store Byte (STBY)
6.4.7 Set Bit (SBIT)
6.4.8 Reset Bit (RBIT)
6.4.9 Test Bit (TBIT)
6.4.10 Increment Memory (INCM)
6.4.11 Decrement Memory (DECM)
6.4.12 Load All Registers and Status (LARS)
6.4.13 Store All Registers and Status (SARS)
6.5 Skip Instructions
6.6 Input/Output Instructions (XIO)
6.6.1 XIO Control and Test Instructions (CTRL,
TEST)
6.6.2
XIO Data Transfers
iii
Pa ge
5-1
5-1
5-2
5-2
5-2
5-9
5-10
5-10
5-10
5-12
5-12
5-13
5-13
6-1
6-1
6-1
6-10
6-10
6-13
6-14
6-16
6-17
6-18
6-20
6-21
6-22
6-23
6-24
6-24
6-27
6-28
6-28
6-2 8
6-32
· 6-34
6-36
6-38
6-3R
6- 40

Section
7
8
9
Contents (Continued)
Title
6.7 Register Operate and Reg ister Operate
6.8
6.9
6.10
6. 11
6. 12
6. 13
6. 14
6. 1, 5
Compare Instructions
Register Operate Li ~ eral and Register
Compare Literal Instructions
Register Change Instructions
Shift Instructions
Control Instructions
Wait Instruction
Multiply, MPY (Opti n)
Divide, DIV (Option)
Interrupt (S7) and ycle-Steal (S8)
Sequence States
SPC-16 MEMORY
7.1 Introduction
7.2 Magnetic Core Opera ion
7. 3
7. 4
7. 5
7. 6
7. 7
7.2.1 Memory cor, 1 Control Wires
7.2.2 Memory Cycl es
Decoder and Drive S ~ itches
Regulator and Curre d t Source~
7.4.1 Regulator 1-
7.4.2 Current So ~ rces
7.4.3 Quiescent onditions - Current Source Off
7.4.4 Current Tu ~ n On
7.4.5 Current Tu ~ n Off
7.4.6 Memory Gua d
Sense Amplifier and Inhibit Drivers
T~ming and Control
Memory Logic Signal Mnemonics
SP C -16 POWER SUPPLY
8.1 Power Fail Detect Ci rcuit
PREVENTIVE MAINTENANCE PRO q EDURES .
9.1 CPU Preventive Main tt enance
9.1.1 Fan Removal and Replacement
I I 9.1.2 Cleaning t Ae CPU
9. 4 Power Supply Output Check and Adjustment
l V
Pa ge
6-42
6-44
6-47
6-53
6-57
6-60
6-61
6-67
6-70
7-1
7-1
7-1
7-4
7-4
7-6
7-6
7-6
7-10
7-10
7-10
7-10
7-10
7-12
7-12
7-12
8-1
8-1
9-1
9-1
9-1
9- 3
9-3

Section
10
Appendix A
Appendix B
Appendix C
Appendix D
Index
Figures
1-1
1-2
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
Contents (Continued)
Title
CORRECTIVE MAINTENANCE PROCEDURES
10.1 U~ing the Diagnostic Programs
10.2
10.3
10.4
10.5
10.6
10.1.1 Program Loaders
10.1.2 Diagnostic Test Programs
Verification of Data Channel Operation
Operational Check-Out of SPC-16 Processor
Display Console
10.3.1 Loading Registers from Console
10.3.2 Loading Memory from Console
Check of Power Supply Voltages
Processor Board Substitution
Removal and Replacement of CPU Subassemblies
10.6.1 CPU, Memory and Controller Boards
10.6.2 Console Board
10.6.3 Master Interconnect Board(s)
Signal Mnemonic Definition
Component Interchangeahility
Parts List, Computer Mainframe Assembly
SPC-16 Console
SPC-16 40/60/80 Typical System
SPC-16 45/65/85 System with Fully Expanded Memory
Installation Drawing SPC-16 40/60/80 Model 1640 (or 60 or 80)
SPC-16 40/60/80 Internal Board Arrangement
Installation Drawing SPC-16 45/65/85 with 0 - 32K
Memory Capability
Installation Drawing SPC-16 45/65/85 with Extended
32 - 64K Memory
SPC-16
45/65/85 Internal Board Arrangement
Internal Arrangement of the CPU
Console Board Functional Arrangement
Arithmetic Board Functional Arrangement
SPC-16 40/60/80 Master Interconnect Board
Functional Arrangement
SPC-16 45/65/85 Master Interconnect Boards
Functional Arrangement
v
10-1
10-4
10-4
10-9
10-11
10-12
10-13
10-17
10-25
10-25
10":"26
10-26
10-27
10-27
A-I
B-1
C-l
D-l
1
1-2
1-2
2-2
2-3
2-4
2-5
2-6
3-2
3-9
3-11
3-14
3-14 ..

Figures
3-6
3-7
3-8
3-9
3-10
3-11
4-1
4-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
Contents (Continued)
Title
Macro Control Board Functio al Arrangement
Timing Control Board Functional Arrangement
Memory and Input/Output Boa~d Functional Ar~angement
LowrProfile Planar Array 4K Memory Board
Low-Profile Planar Array 8K Memory Board
Planar Array 16K Memory BOa r d
SPC~16 Block Diagram
Operational Register Organi r ation
Basic Timing
Basic Timing of Processor ( OC and DO Worst Case)
DO Timing Flowchart
Sequence State Timing Flowc art
Sequence Advance Counter at D04 (Worst Case Timing)
SPC-16 Read/Write Memory .
SPC~l~ Step Timing - Idle Mode
SPC-16
Auto Restart Timing ~ Run Mode
I Register General Decode
SPC-16 Instruction Summary exadecimal Coding
LDA Instruction Sequence Ch 1 art
STA Instruction Sequence Ch 1 art
JSR Instruction Sequence Ch 1 art
JMP Instruction Sequence Ch 1 art
LDR Instruction Sequence Chart
STR Instruction Sequence Ch l art
CMR Instruction Sequence c ~ art
LDBY Instruction Sequence Chart
STgy Instruction Sequence Chart
SBIT Instruction Sequence Chart
RBIT Instruction Sequence Chart
TBIT Instruction Sequence
INCM Instruction Sequence
DEeM Instruction Sequence
LARS Instruction Sequence
SARS Instruction . Sequence
SKIP Instruction Sequence
XIO Control and Test Sequence Chart
XIa Data Transfer sequenCe ~ Chart
Register Operate Instructi n Sequence Chart
Register Operate Literal I struction Sequence Chart
RLK, ADDS, INCR, DECR, CMP Instruction Sequence Chart
ZR BY, ZLBY, RCSW, TSR, EXB Instruction Sequence Chart
vi
Page
3-16
3-18
3-21
3-24
3-25
3-26
4-2
4-10
5-3
5-4
5-5
5-7
5-10
5-11
5-12
5-14
6-2
6-3
6-11
6-14
6-15
6-16
6-18
6-20
6-21
6-23
6-25
6-26
6-27
6-29
6-30
6-31
6-33
6-35
6-37
6-39
6-41
6-43
6-46
6-49
6-50

Figures
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
8-1
9-1
9-2
9-3
10-1
10-2
10-3
10-4
10-5
D-l
Tables
1-1
1-2
1-3
4-1
4-2
4-3
Contents (Continued)
Title
DSPL, TRS, RISE, TRP, XEC Sequence Chart
Shift Instruction Flowchart
Shift Instruction Sequence Chart
SYNC, PMA, LKR, LKS, BMS, FMS, INH, INE
Instruction Sequence Chart
Wait Instruction Sequence Chart
MPY Instruction Sequence Chart
Multiply Example
DIV Instruction Sequence Chart
Interrupt and Cycle-Steal Sequencing
Functional Block Diagram of Memory
Ferrite Core Hysteresis Loop
Memory Core",Mat
Typical X o'r Y Drive Line
Source Switch Schematic
Regulator Schematic
X Current Source Schematic
Sense Amplifier and Inhibit Driver Schematic
Memory Timing Diagram
Timing Diagram
of Power Fail/Automatic Restart
Removing Fans
Pin Assignments; DC Power Input Connector
Power Supply Adjustment Potentiometers
Timing Diagram - WAIT
Memory Allocation for Base-Relative Indirect LDR
Instruction with Indexing
Removing Console Board
Removing
MIB (40/60/80)
Removing MIB's (45/65/85)
SPC-16 Computer Console
SPC-16 Summary
DC Requirements of CPU and Memory Boards
DC Requirements of General Automation Controller Boards
Table of Arithmetic Operations
Table of Logic Functions
I Register Decode
vii
Page
6-52
6-55
6-55
6-58
6-60
6-62
6-66
6-68
6-70
7-2
7-3
7-5
7-7
7-8
7-9
7-11
7-13
7-14
8-1
9-2
9-3
9-5
10-10
10-21
10-27
10-28
10-31
D-2
1-3
1-8
1-9
4-3
4-4
4-8

Tables
6-1
6-2
7-1
9-1
10-1
B-1
B-2
B-3
B-4
B-5
B-6
C-l
C-2
C-3
C-4
C-5
C-6
C-7
Contents (Oontinued)
Title
Symbol Definition
Term Definition
Memory Board Signal Mnemonic List
Power Verification Points
Timing Board Pin Assignments
Component Compatibility
Component Compatibility
Component Compatibility
Component Compatibility
Component Compatibility
Component Compatibility
Computer Mainframe Assembly
Computer
Mainframe Assembly
Computer
Mainframe Assembly
Computer
Mainframe Assembly
Computer
Mainframe Assembly
Computer
Mainframe Assembly
MIB!Memory Compatibility Chart
I
viii
Page
6-6
6-7
7-15
9"';4
10-11
B-1
B-2
B-3
B-4
B-5
B-6
C-2
C-3 "
C-4
C-5
C-6
C-7
C-8

PREFACE
This document is a maintenance manual for use with General Automation's SP C -1 6 Auto-
mation Computer models 40/45, 60/6~, 80/85. The included material is intended t o guid2
both the General Automation field service representative and the customer in th e pr o-
per procedures of on-site fault isolation and correction and preventive maintenan c e.
All procedures are given in an easily followed step-by-step format. Fault isolation is
to the processor board level.
Usefulness of this manual is enhanced by a previous reading of the SPC-·1 6 /40 seri es
Reference Manual (G8A00243A).
The
SPC-16/40 series Maintenance Manual is organized as follows:
o Section I includes a general description of the SPC-16/40 series system.
o Section 2 presents drawings intended to give the reader a basic orientati on
as to the physical layout of the computer.
o Section 3 describes the functional organization of the SPC-16 Central Proces sing
Un i t.
o Section
4
describes data flow
within
the computer.
o Section
5
describes
the basic
timing
signals
in the
SPC-16 processor.
o Section
6
presents
sequence diagrams
for
the
SPC-16
instruction set.
o Section
7
describes
the SPC-16 memory.
o
Section
8
describes
the SPC-16
processor power
supply.
o Section
9
discusses
preventive
maintenance procedures.
o Section 10 presents procedures to isolate an existing malfunction in the
SPC-16 processor and Input/Output system.
o Appendix A gives the definitions of signal mnemonics.
o Appendix B is a guide to processor board interchangeability.
o Appendix C includes lists of parts used in the computers mainframe assembl y.
o
Appendix D is a description of the switches and indicators on the SPC-16
console.
ix

I
,
SECTION 1
INTRnnUCTION
The SPC-16 computer is a stored-program digital computer with l6-bit word length
organization, a high-speed memory, and a versatile arithmetic and control unit.
/
1.1 SYSTEM ORGANIZATION
The SPC-16 processor family consists of six different computers offering a choice
of three memory cycle speeds and two packaging configurations:
Packaging
Model Ntnnber
Memory Cycle Time
Configuration
SPC-16/40 1440
Nanoseconds Internal
I/O
SPC-16/45 1440
Nanoseconds
External I/O
SPC-16/60 960 Nanoseconds
Internal
I/O
SPC-16/65 960 Nanoseconds
External I/O
SPC-16/80 800
Nanoseconds Internal I/O
SPC-16/85 800
Nanoseconds
External I/O
All models of the SPC-16 utilize the same efficient modular concept which enables the
user to maintain, troubleshoot and remove and replace subassemblies with ease.
SPC-16/40, 60, 80
In the SPC-16/40, 60 and 80 models the I/O logic is housed in the computer mainframe.
This configuration provides eight card slots for peripheral controller boards, four
card slots for memory logic boards and four card slots for processor logic boards.
A memory slot will accept any of the following memory modules:
eA Read/Write Memory module with 4K, 8K or 16K word capacity.
e If 4K, 8K and/or 16K modules are intermixed, the 4K must be in highest
address slot.
eA Read-Only Memory (ROM) module with 512-, 1024-, 2048- or 4096-word capacity.
e A Read/Write Memory module that also includes a 32- or 64-word ROM or a
Memory Protect unit (option).
This series of computer utilizes the integral I/O packaging .configuration, which is
arranged as shown in Figure 1-1.
SPC-16/45, ' 65, 85
The
SPC-16/45, 65 and 85 model computers are designed for users with applications
requiring more than 32K of memory. These models provide optionally up to l28K of
memory. In these models the I/O controller modules are housed in an external I/O
enclosure, which allows the mainframe to accommodate the additional memory modules. '
1-1

MIB :
1/0 . {
CO. NTROLLERS
{
~.--r-o-~-:_-:~_-_-_-_-_-_-_-_-_-_-~o~
C.P.U. g g
o 0
01-----o
C 0
o 0
o 0
o a
t 0 0
SPC-16 (FRONT VIEW)
PERIPHERAL
CABLING
,
PERIPHERAL
DEVICE
Figure 1-1. SPC-16 4
/60/80 Typical System
As shown in Fig~re 1-2, the mainframe contains the four basic CPU boards and up to
eight memory boards. The external I/O bJs is cabled to the external I/O enclosure,
which contains the controllers. The extJrnal I/O enclosure has 18 card slots avail-
~ I
able for peripheral controller cards an one slot reserved for a cable interface
card.
MIB
c
0 !.
__ ~~~------~o
c
c
c---------------~c
c---------------~o
0 c
~------------~o
c
o---------------~D
0
----------------0
c
--------------~c
c
----------------0
0
0
C
0----------------0
--------------~O
~------------~a
0
SPC-16 (FRONT VIEW)
EXTERNAL
I/O BUS
' [11111111[[[[11[[11
EXTERNAL I/O
ENCLOSURE
PERIPHERAL
DEVICE
PERIPHERAL
CABLING
Figure 1-2. SPC-16/45/65/85 iyste m with 64K Expanded Memory
, j -2

1.2 GDJERAL SPECIFICATIONS
General specifications for the SPC-16 40/45, 60/65 and BO/8S series are summarized
in Table 1-1.
Table 1-1. SPC-16 Specification Summary
Characteristic
Memory
Specification
o Random access
o l6-bit word organization.
o Expandable to 32K l6-bit words (using
8K memory m9dules).
o Extendable to 128K 16- bit words
(Models 45, 65, 85 only).
o Interchangeable Read/Write and Read
Only Memory boards.
o Read--Only Memory modules available in
512-, 1024-, 2048- and 4096- word
increments.
",
o Read/Write Memory module available in
4096- and 8192- word sizes.
o Read/Wri~e Memory module may include
32- or 64-- word ROM.
o Lithium ferrite core stacks (with
wide temperature tolerance) used on
Read/Write Memory; each stack has an
independent current regulator.
o Metal-oxide semiconductor rcs used on
~~~~~~~~~~~~~~~~~~~~ ~~_ . _ _ Rea~ . onlY Memory boards. I
Address;ing
o Single and double-word addressing.
o
1-3
Eleven addressing schemes, includin g : I
Direct and direct indexed; indirect
and indirect indexed; program
relative and program relative in-
direct; base relative and base
relative indexed; base relative
indirect and base relative indirect
indexed; literal.
I

Table l-~. (continued)
Characteristic
Arithmetic
Instructions
Instruc~ion Rxecution Time
Specification
o Bit, byte and word operations (lo g ic al
and arithmetic).
o Parallel, binary, fixed point two's
complement.
o There are 9 standard instruction
groups and one optional group (number
of instructions in a group is shown in
parentheses following group name):
-Memory reference (4)
-Memory reference, indexed (12)
- Skip (±256 locations on 8 condi-
tions) (8) . -"
- Register operate and compare (11)
-
Register operate literal and
compare (11)
- Register change (16)
- Shift (0 to 16 bits) (4)
- Control (9)
- Input/Output for up to 64 devices
(single word instruction addressin g)
(6)
- Hardware Multiply and Divide
(optional) (2)
o All instructions may be stored in
either Read/Write or Read Only Memory
modules.
o Execution times vary ' with the complexit y
of the instruction and are a multiple
o
o
o
1 4
of memory cycle time. Values below
are execution times for a one-cycle
instruction.
SPC-16/40& 45
1440 ns (Read/Write Memory)
720
ns
(Read Only Memory)
SPC-16/60 & 65 · 960 ns (Read/Hrite Hemory)
480
ns
(Read Only Memory)
SPC-16/80 & 85 800
ns
(Read/Write Memory)
400
ns
(Read Only Memory)
0
j