AKM AK4633 User manual
ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 1 -
GENERAL DESCRIPTION
The AK4633 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a
Speaker-Amplifier and Mono Line Output. The AK4633 suits a moving picture of Digital Still Camera and
etc. This speaker-Amplifier supports a Piezo Speaker. The AK4633 is housed in a space-saving 24-pin
QFN package.
FEATURE
1. 16-Bit Delta-Sigma Mono CODEC
2. Recording Function
•1ch Mono Input
•1st MIC Amplifier: 0dB, 6dB, 10dB, 14dB, 17dB, 20dB, 26dB or 32dB
•2nd Amplifier with ALC: +36dB ∼-54dB, 0.375dB Step, Mute
•ADC Performance (MIC-Amp= +20dB): S/(N+D): 84dB, DR, S/N: 85dB
•Wind Noise Reduction
•Notch Filter
3. Playback Function
•Digital ALC (Automatic Level Control): +36dB ∼-54dB, 0.375dB Step, Mute
•Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB
•Mono Speaker-Amp
- Speaker-Amp Performance: S/(N+D): 60dB (150mW@ 8Ω)
Output Noise Level: -87dBV
-BTLOutput
-OutputPower:400mW@8
Ω
•Beep Input
4. Power Management
5. Flexible PLL Mode:
•Frequencies:
11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (FCK pin)
16fs, 32fs or 64fs (BICK pin)
6. EXT Mode:
•Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
7. Sampling Rate:
•PLL Slave Mode (FCK pin) : 7.35kHz ~ 48kHz
•PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz
•PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
•PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
•EXT Slave Mode/EXT Master Mode:
7.35kHz~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)
8. Output Master Clock Frequency: 256fs
9. Serial µP Interface: 3-wire
10.Master / Slave Mode
AK4633
16-Bit ∆Σ Mono CODEC with ALC & MIC/SPK-AMP
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11.Audio Interface Format: MSB First, 2’s compliment
•ADC: DSP Mode, 16bit MSB justified, I2S
•DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S
12.Ta = -40 ∼85°C
13.Power Supply
•AVDD: 2.2 ∼3.6V (typ. 3.3V)
•DVDD: 1.6 ∼3.6V (typ. 3.3V)
•SVDD: 2.2 ∼4.0V (typ. 3.3V)
14.Power Supply Current: 12mA (All Power ON)
15.Package: 24pin QFN(4mmx4mm)
Block Diagram
MIC Power
Supply
A/D HPF
PMMP
PMADC
Audio
I/F
D/A
PMDAC
Line Out
PMSPK
Speaker
PLL
PMBP
PMPLL
Control
Register
MPI
MIC/MICP
SPP
SPN
SVDD SVSS BEEP/MICN
AVDD
A
VSS VCOM DVDD
CSN
PDN
CCLK
CDTI
BICK
FCK
SDTO
SDTI
MCKO
MCKI
VCOC
PMAO
AOUT
DVSS
MIC-Amp
0dB /+6dB/+10dB/+14dB/+17dB
+20dB / +26dB / +32dB
Mic
HPF
2 Band
EQ
VOL
(ALC)
PMPFIL
Figure 1. AK4633 Block Diagram
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Ordering Guide
AK4633VN −40 ∼+85°C 24pin QFN (0.5mm pitch)
AKD4633 Evaluation board for AK4633
Pin Layout
SVSS
SVDD
A
OUT
BEEP/MICN
MPI
MIC/MICP
SPN
SPP
MCKO
MCKI
DVSS
DVDD
VCOM
A
VSS
AVDD
VCOC
PDN
CSN
BICK
FCK
SDTO
SDTI
CDTI
CCLK
AK4633VN
Top View
19
20
21
22
23
24
18
17
16
1
12
11
10
9
8
7
15
14
13
2
3
4
5
6
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Interchange with AK4631
1. Function
Function AK4631 AK4633
AVDD 2.6V ∼3.6V 2.2V ∼3.6V
DVDD 2.6V ∼3.6V 1.6V ∼3.6V
SVDD 2.6V ∼5.25V 2.2V ∼4.0V
MIC Input Single-end Single-end / differential
MIC Power Output Voltage 0.75 x AVDD 0.8 x AVDD
MIC-Amp 0dB/+20dB/+26dB/+32dB 0dB/+6dB/+10dB/+14dB
+17dB/+20dB/+26dB/+32dB
HPF for Wind Noise Reduction No Yes
Notch Filter No Yes
ALC for Input Signal Analog ALC Digital ALC (Note 1)
Input Volume +27.5dB ∼-8dB, 0.5dB Step +36dB ∼-54dB, 0.375dB Step
(Note 1)
ALC for Output Signal Speaker-Amp block Digital Block (Note 1)
Output Volume +12dB ∼-115dB, 0.5dB Step +36dB ∼-54dB, 0.375dB Step
(Note 1)
Maximum Output for SPK-Amp
(using Piezo Speaker)
8.5Vpp@SVDD=5V 6.33Vpp@SVDD=3.8V
MCKI Pull-down Resistance Yes No (Delete MCKPD bit )
Package 28pin QFN 5.2mm x 5.2mm
41pin BGA 4.0mm x 4.0mm
24pin QFN 4.0mm x 4.0mm
Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume
function at same time for both recording and playback mode.
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2. Register Map
(1) AK4631
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Power Management 1 0 PMVCM PMBP PMSPK PMAO PMDAC PMMIC PMADC
01H Power Management 2 0 0 0 0 M/S MCKPD MCKO PMPLL
02H Signal Select 1 SPPS BEEPS ALC2S DACA DACM MPWR MICAD MGAIN0
03H Signal Select 2 0 AOPSN MGAIN1 SPKG1 SPKG0 BEEPA ALC1M ALC1A
04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO1 BCKO0 DIF1 DIF0
05H Mode Control 2 0 0 FS3 MSBS BCKP FS2 FS1 FS0
06H Timer Select DVTM ROTM ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0
07H ALC Mode Control 1 0 ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH
08H ALC Mode Control 2 0 REF6 REF5 REF4 REF3 REF2 REF1 REF0
09H Input PGA Control 0 IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0
0AH Digital Volume Control OVOL7 OVOL6 OVOL5 OVOL4 OVOL3 OVOL2 OVOL1 OVOL0
0BH ALC2 Mode Control 0 0 RFS5 RFS4 RFS3 RFS2 RFS1 RFS0
(2) AK4633
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Power Management 1 PMPFIL PMVCM PMBP PMSPK PMAO PMDAC 0 PMADC
01H Power Management 2 0 0 0 0 M/S 0 MCKO PMPLL
02H Signal Select 1 SPPSN BEEPS DACS DACA 0 PMMP MGAIN2 MGAIN0
03H Signal Select 2 PFSDO AOPS MGAIN1 SPKG1 SPKG0 BEEPA PFDAC ADCPF
04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO1 BCKO0 DIF1 DIF0
05H Mode Control 2 ADRST FCKO FS3 MSBS BCKP FS2 FS1 FS0
06H Timer Select 0 0 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0
07H ALC Mode Control 1 0 ALC2 ALC1 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0
08H ALC Mode Control 2 IREF7 IREF6 IREF5 IREF4 IREF3 IREF2 IREF1 IREF0
09H Digital Volume Control IVOL7 IVOL6 IVOL5 IVOL4 IVOL3 IVOL2 IVOL1 IVOL0
0AH Digital Volume Control OVOL7 OVOL6 OVOL5 OVOL4 OVOL3 OVOL2 OVOL1 OVOL0
0BH ALC Mode Control 3 RGAIN1 LMTH1 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0
0DH ALC LEVEL VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0
0EH Signal Select 3 DATT1 DATT0 SMUTE MDIF EQ2 EQ1 HPF HPFAD
10H - 1FH Digital Filter Setting
hatching Register bits changed from the AK4631.
Bold Register bits added from the AK4631.
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3. Register Setting
(1) When PLL reference clock is input from FCK or BICK pin, the setting of FS3-0 bits is changed as shown in the
following table.
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency
Range
0 0 0
Don’t care Don’t care 7.35kHz ≤fs ≤12kHz
1 0 1
Don’t care Don’t care 12kHz < fs ≤24kHz
2 1 0
Don’t care Don’t care 24kHz < fs ≤48kHz
Others Others N/A
ALL of modes are changed from AK4631.
(2) In EXT Slave Mode, the setting of FS3-0 bits is changed as shown in the following table.
.
Mode FS3-2 bits FS1 bit FS0 bit MCKI Input
Frequency
Sampling Frequency
Range
0 Don’t care 0 0 256fs
7.35kHz ≤fs ≤48kHz
1 Don’t care 0 1 1024fs
7.35kHz < fs ≤13kHz
2 Don’t care 1 0 512s 7.35kHz < fs ≤26kHz
3 Don’t care 1 1 256fs 7.35kHz ≤fs ≤48kHz
Hatching parts are the setting changed from AK4631.
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PIN / FUNCTION
No. Pin Name I/O Function
1 VCOM O Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of ADC inputs and DAC outputs.
2 AVSS - Analog Ground Pin
3 AVDD - Analog Power Supply Pin
4 VCOC O
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AVSS with one resistor and capacitor in series.
5 PDN I
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initialize the control register.
AK4633 should always be reset upon power-up.
6 CSN I Chip Select Pin
7 CCLK I Control Data Clock Pin
8 CDTI I/O Control Data Input Pin / Output pin
9 SDTI I Audio Serial Data Input Pin
10 SDTO O Audio Serial Data Output Pin
11 FCK I/O Frame Clock Pin
12 BICK I/O Audio Serial Data Clock Pin
13 DVDD - Digital Power Supply Pin
14 DVSS - Digital Ground Pin
15 MCKI I
External Master Clock Input Pin
16 MCKO O Master Clock Output Pin
17 SPP O Speaker Amp Positive Output Pin
18 SPN O Speaker Amp Negative Output Pin
19 SVSS - Speaker Amp Ground Pin
20 SVDD - Speaker Amp Power Supply Pin
21 AOUT O Mono Line Output Pin
22 BEEP I Beep Signal Input Pin (MDIF bit = “0”)
MICN I Microphone Negative Input Pin for Differential Input (MDIF bit = “1”)
23 MPI O MIC Power Supply Pin for Microphone
24 MIC I Microphone Input Pin for Single Ended input (MDIF bit = “0”)
MICP I Microphone Positive Input Pin for Differential Input (MDIF bit = “1”)
Note: All input pins except analog input pins (MIC/MICP and BEEP/MICN pins) should not be left floating.
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Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification Pin Name Setting
Analog MIC/MICP, BEEP/MICN, MPI, AOUT,
SPP, SPN, VCOC
These pins should be open.
MCKI, SDTI These pins should be connected to DVSS.
FCK, BICK (Note) These pins should be connected to DVSS, or should
be pulled-down/pulled-up by about 100kΩresister .
Digital
MCKO, SDTO These pins should be open.
(Note) When the AK4633 is used by the slave mode (M/Sbit=“0”), these pins should be connected to DVSS. When the
AK4633 is used by the master mode (M/Sbit=“1”), these pins should be pulled-down or pulled-up by about 100kΩ
resistor.
ABSOLUATE MAXIMUM RATING
(AVSS, DVSS, SVSS=0V; Note 2)
Parameter Symbol min max Units
Power Supplies:
Analog
Digital
Speaker-Amp
|AVSS – DVSS| (Note 3)
|AVSS – SVSS| (Note 3)
AVDD
DVDD
SVDD
∆GND1
∆GND2
−0.3
−0.3
−0.3
-
-
4.6
4.6
4.6
0.3
0.3
V
V
V
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Analog Input Voltage (Note 5) VINA −0.3 AVDD+0.3 V
Digital Input Voltage (Note 6) VIND −0.3 DVDD+0.3 V
Ambient Temperature (powered applied) Ta −40 85
°C
Storage Temperature Tstg −65 150
°C
Maximum Power Dissipation (Note 4) Pd - 650 mW
Note 2. All voltages with respect to ground.
Note 3. AVSS, DVSS and SVSS must be connected to the same analog ground plane.
Note 4. In case that PCB wiring density is 100%. This power is the AK4633 internal dissipation that does not include
power of externally connected speaker.
Note 5. BEEP/MICN, MIC/MICP pins
Note 6. PDN, CSN, CCLK, CDTI, SDTI, FCK, BICK, MCKI pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
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RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, SVSS=0V; Note 2)
Parameter Symbol min typ max Units
Power Supplies
(Note 7)
Analog
Digital
Speaker-Amp
Difference
AVDD
DVDD
SVDD
DVDD - AVDD
DVDD - SVDD
2.2
1.6
2.2
-
-
3.3
3.3
3.3
-
-
3.6
3.6
4.0
0.3
0.3
V
V
V
V
V
Note 2. All voltages with respect to ground.
Note 7. The power up sequence between AVDD, DVDD and SVDD is not critical. It is not permit to power DVDD off
only when AVDD or SVDD is powered up. When the power supplies except DVDD are partially powered OFF,
the AK4633 must be reset by bringing PDN pin “L”after these power supplies are powered ON again. If AVDD is
powered off when DVDD is powered up, the PMADC bit should be set to “0”before AVDD is powered off.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ANALOG CHRACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz;
16bit Data; Measurement frequency=20Hz ∼3.4kHz; EXT Slave Mode; unless otherwise specified)
Parameter min typ max Units
MIC Amplifier : MDIF bit = “0”; (Single-ended input)
Input Resistance 20 30 40 kΩ
Gain (MGAIN2-0 bits = “000”) - 0 - dB
(MGAIN2-0 bits = “001”) - 20 - dB
(MGAIN2-0 bits = “010”) - 26 - dB
(MGAIN2-0 bits = “011”) - 32 - dB
(MGAIN2-0 bits = “100”) - 6 - dB
(MGAIN2-0 bits = “101”) - 10 - dB
(MGAIN2-0 bits = “110”) - 14 - dB
(MGAIN2-0 bits = “111”) - 17 - dB
MIC Amplifier : MDIF bit = “1”; (Full-differential input)
Input Voltage (MGAIN2-0 bits = “001”) - - 0.228 Vpp
(Note 8) (MGAIN2-0 bits = “010”) - - 0.114 Vpp
(MGAIN2-0 bits = “011”) - - 0.057 Vpp
(MGAIN2-0 bits = “100”) - - 1.14 Vpp
(MGAIN2-0 bits = “101”) - - 0.721 Vpp
(MGAIN2-0 bits = “110”) - - 0.455 Vpp
(MGAIN2-0 bits = “111”) - - 0.322 Vpp
MIC Power Supply: MPI pin
Output Voltage (Note 9) 2.38 2.64 2.90 V
Load Resistance 2 - - kΩ
Load Capacitance - - 30 pF
ADC Analog Input Characteristics: MIC ÆADC, MIC Gain=20dB, IVOL=0dB, ALC1bit = “0”
Resolution - - 16 Bits
Input Voltage (MIC Gain=20dB,Note 10) 0.168 0.198 0.228 Vpp
S/(N+D) (−1dBFS) (Note 11) 72 84 - dB
D-Range (−60dBFS) 75 85 - dB
S/N 75 85 - dB
DAC Characteristics:
Resolution 16 Bits
Mono Line Output Characteristics: AOUT pin, DAC →AOUT, RL=10kΩ
Output Voltage (Note 12) 1.78 1.98 2.18 Vpp
S/(N+D) (0dBFS) (Note 11) 73 85 - dB
D-Range (-60dBFS) 83 93 - dB
S/N 83 93 - dB
Load Resistance 10 - -
kΩ
Load Capacitance - - 30 pF
Speaker-Amp Characteristics: DAC ÆSPP/SPN pins, ALC2 bit = “0”, RL=8Ω, BTL, SVDD=3.3V
SPKG1-0 bits = “00”(-4.1dBFS) 2.54 3.17 3.80 Vpp
Output Voltage SPKG1-0 bits = “01”(-4.1dBFS) 3.20 4.00 4.80 Vpp
S/(N+D) As 150mW output power 40 60 - dB
As 400mW output power - 20 - dB
Output Noise SPKG1-0 bits = “00”- -87 - dBV
Level SPKG1-0 bits = “01”-75 -85 - dBV
SPKG1-0 bits = “10”- -83 - dBV
Load Resistance 8 - - Ω
Load Capacitance - - 30 pF
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Parameter Min typ max Units
Speaker-Amp Characteristics: DAC ÆSPP/SPN pins, ALC2=OFF, CL=3µF, Rserial=10Ωx 2, BTL, SVDD=3.8V
Output Voltage SPKG1-0 bits = “11”
(-4.1dBFS) - 6.33 - Vpp
S/(N+D) (Note 13) SPKG1-0 bits = “11”
(-4.1dBFS) - 60 - dB
Output Noise Level (Note 13) SPKG1-0 bits = “11”- -81 - dBV
Load Impedance (Note 14) 50 - - Ω
Load Capacitance - - 3
µF
BEEP Input: BEEP pin, External Input Resistance= 20kΩ
Maximum Input Voltage (Note 15) - 1.98 - Vpp
Output Voltage (Input Voltage=0.6Vpp)
BEEP ÆSPP/SPN (SPKG1-0 bits = “00”) 0.625 1.25 1.875 Vpp
BEEP ÆAOUT 0.25 0.50 0.75 Vpp
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 17)
AVDD+DVDD
fs=8kHz - 8 - mA
fs=48kHz - 11 17 mA
SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output)
SVDD=3.3V - 4 12 mA
Power Down (PDN = “L”) (Note 18)
AVDD+DVDD+SVDD - 1 100
µA
Note 8. It is a differential value of plus and minus input pin. Each input pins should be connected to the AC coupling
capacitance serially. The differential input is not permission when MGAIN2-0 bits are “000”. The Maximum
input voltage of MICP and MICN pins are proportional to AVDD voltage. Vin= |(MICP) −(MICN)| = 0.069 x
AVDD (max)@MGAIN2-0 bits = “001”,
0.035 x AVDD (max)@MGAIN2-0 bits = “010”, 0.017 x AVDD (max)@MGAIN2-0 bits = “011”,
0.346 x AVDD (max)@MGAIN2-0 bits = “100”, 0.218 x AVDD (max)@MGAIN2-0 bits = “101”,
0.138 x AVDD (max)@MGAIN2-0 bits = “110”, 0.098 x AVDD (max)@MGAIN2-0 bits = “111”,
ADC function is not assumed for using the exceeded input voltage.
Note 9. Output Voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).
Note 10. Input Voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ).
Note 11. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D):MICÆADC is 75dB (typ) and
S/(N+D):DACÆAOUT is 75dB(typ).
Note 12. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 13. In case of measuring between SPP pin and SPN pin directly.
Note 14. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 41. Load
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ωor more series resistors should be
connected at both SPP and SPN pins, respectively.
Note 15. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance (Rin).
Vout = 0.6 x AVDD x Rin/20kΩ(max).
Note 16. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 17. In case of PLL Master Mode (MCKI=12.288MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK =
PMVCM = PMPLL = MCKO = PMAO = PMBP = PMMP = M/S =“1”. In this case, the output current of MPI
pin is 0mA.
When the AK4633 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD”is typically 6mA@fs=8kHz,
9mA@fs=48kHz.
Note 18. All digital inputs pins are fixed to DVDD or DVSS.
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FILTER CHRACTERISTICS
(Ta = 25°C; AVDD =2.2 ∼3.6V, DVDD =1.6 ∼3.6V, SVDD =2.2 ∼4.0V; fs=8kHz)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 19)
±0.16dB
−0.66dB
−1.1dB
−6.9dB
PB
0
-
-
-
-
3.5
3.6
4.0
3.0
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 19) SB 4.7 - - kHz
Passband Ripple PR - - ±0.1 dB
Stopband Attenuation SA 73 - - dB
Group Delay (Note 20) GD - 16 - 1/fs
Group Delay Distortion ∆GD - 0 - µs
DAC Digital Filter (Decimation LPF):
Passband (Note 19)
±0.16dB
−0.54dB
−1.0dB
−6.7dB
PB
0
-
-
-
-
3.5
3.6
4.0
3.0
-
-
-
Stopband (Note 19) SB 4.7 - - kHz
Passband Ripple PR - - ±0.1 dB
Stopband Attenuation SA 73 - - dB
Group Delay (Note 20) GD - 16 - 1/fs
Group Delay Distortion ∆GD - 0 - µs
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼3.4kHz FR - ±1.0 - dB
Note 19. The passband and stopband frequencies are proportional to fs (system sampling rate).
For example, ADC is PB=3.6kHz (@-1.0dB)= 0.45 x fs. A reference of frequency response is 1kHz.
Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data of a channel from the input register to the output register of the ADC.
For the DAC, this time is from setting the 16-bit data of a channel from the input register to the output of analog
signal.
In case of selected the path through the programming filter (1st HPF + 2-band Equalizer + ALC), the Group
Delay should be increased to 2/fs without the phase changing by IIR filter.
DC CHRACTERISTICS
(Ta = 25°C; AVDD =2.2 ∼3.6V, DVDD =1.6 ∼3.6V, SVDD =2.2 ∼4.0V)
Parameter Symbol min typ max Units
High-Level Input Voltage (DVDD ≥2.2V)
(DVDD < 2.2V)
Low-Level Input Voltage (DVDD ≥2.2V)
(DVDD < 2.2V)
VIH
VIL
70%DVDD
80%DVDD
-
-
-
-
-
-
-
-
30%DVDD
20%DVDD
V
V
V
V
High-Level Output Voltage (Iout=−80µA)
Low-Level Output Voltage (Iout= 80µA)
VOH
VOL
DVDD−0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - - ±10 µA
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SWITING CHARACTERISTICS
(Ta = 25°C; AVDD =2.2 ∼3.6V, DVDD =1.6 ∼3.6V, SVDD =2.2 ∼4.0V; CL=20pF)
Parameter Symbol min typ max Units
PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27.0
-
-
MHz
ns
ns
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz,32kHz
fs=29.4kHz, 32kHz (Note 21)
fMCK
dMCK
dMCK
-
40
-
256 x fFCK
50
33
-
60
-
kHz
%
%
FCK Output: Frequency
Pulse width High
(DIF1-0 bits = “00”and FCKO bit = “1”)
Duty Cycle
(DIF1-0 bits ≠“00”or FCKO bit = “0”)
fFCK
tFCKH
dFCK
8
-
-
-
tBCK
50
48
-
-
kHz
ns
%
BICK: Period (BCKO1-0 = “00”)
(BCKO1-0 = “01”)
(BCKO1-0 = “10”)
Duty Cycle
tBCK
tBCK
tBCK
dBCK
-
-
-
-
1/16fFCK
1/32fFCK
1/64fFCK
50
-
-
-
-
ns
ns
ns
%
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑”to BICK “↑”(Note 22)
FCK “↑”to BICK “↓”(Note 23)
BICK “↑”to SDTO (BCKP = “0”)
BICK “↓”to SDTO (BCKP = “1”)
SDTI Hold Time
SDTI Setup Time
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK -40
0.5 x tBCK -40
-70
-70
50
50
0.5 x tBCK
0.5 x tBCK
-
-
-
-
0.5 x tBCK + 40
0.5 x tBCK +40
70
70
-
-
ns
ns
ns
ns
ns
ns
Except DSP Mode: (Figure 5)
BICK “↓”to FCK Edge
FCK to SDTO (MSB)
(Except I2S mode)
BICK “↓”to SDTO
SDTI Hold Time
SDTI Setup Time
tBFCK
tFSD
tBSD
tSDH
tSDS
-40
-70
-70
50
50
-
-
-
-
-
40
70
70
-
-
ns
ns
ns
ns
ns
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ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 14 -
Parameter Symbol min typ max Units
PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6,Figure 7)
FCK: Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
fFCK
tFCKH
duty
7.35
tBCK-60
45
8
-
-
48
1/fFCK-tBCK
55
kHz
ns
%
BICK: Period
Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
1/64fFCK
0.4 x tBCK
0.4 x tBCK
-
-
-
1/16fFCK
-
-
ns
ns
ns
PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6,Figure 7)
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
fFCK
tFCKH
duty
7.35
tBCK-60
45
8
-
-
48
1/fFCK-tBCK
55
kHz
ns
%
BICK: Period (PLL3-0 = “0001”)
(PLL3-0 = “0010”)
(PLL3-0 = “0011”)
Pulse Width Low
Pulse Width High
tBCK
tBCK
tBCK
tBCKL
tBCKH
-
-
-
0.4 x tBCK
0.4 x tBCK
1/16fFCK
1/32fFCK
1/64fFCK
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)
MCKI Input: Frequency
Pulse Width Low
Pulse Width High
fCLK
fCLKL
fCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27.0
-
-
MHz
ns
ns
MCKO Output:
Frequency
Duty Cycle except fs=29.4kHz, 32kHz
fs=29.4kHz, 32kHz (Note 21)
fMCK
dMCK
dMCK
-
40
-
256 x fFCK
50
33
-
60
-
kHz
%
%
FCK: Frequency
DSP Mode: Pulse width High
Except DSP Mode: Duty Cycle
fFCK
tFCKH
duty
8
tBCK-60
45
-
-
-
48
1/fFCK-tBFCK
55
kHz
ns
%
BICK: Period
Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
1/64fFCK
0.4 x tBCK
0.4 x tBCK
-
-
-
1/16fFCK
-
-
ns
ns
ns
Audio Interface Timing
DSP Mode: (Figure 9, Figure 10)
FCK “↑”to BICK “↑”(Note 22)
FCK “↑”to BICK “↓”()
BICK “↑”to FCK “↑”(Note 22)
BICK “↓”to FCK “↑”()
BICK “↑”to SDTO (BCKP = “0”)
BICK “↓”to SDTO (BCKP = “1”)
SDTI Hold Time
SDTI Setup Time
tFCKB
tFCKB
tBFCK
tBFCK
tBSD
tBSD
tSDH
tSDS
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
-
-
50
50
-
-
-
-
-
-
-
-
-
-
-
-
80
80
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Except DSP Mode: (Figure 12)
FCK Edge to BICK “↑”(Note 24)
BICK “↑”to FCK Edge (Note 24)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓”to SDTO
SDTI Hold Time
SDTI Setup Time
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
-
-
50
50
-
-
-
-
-
-
-
-
80
80
-
-
ns
ns
ns
ns
ns
ns
Downloaded from Elcodis.com electronic components distributor
ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 15 -
Parameter Symbol min typ max Units
EXT Slave Mode (Figure 11)
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
2.048
4.096
8.192
-
-
12.288
13.312
13.312
-
-
MHz
MHz
MHz
ns
ns
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
fFCK
fFCK
fFCK
duty
7.35
7.35
7.35
45
8
8
8
-
48
26
13
55
kHz
kHz
kHz
%
BICK Period
BICK Pulse Width Low
Pulse Width High
tBCK
tBCKL
tBCKH
312.5
130
130
-
-
-
-
-
-
ns
ns
ns
Audio Interface Timing (Figure 12)
FCK Edge to BICK “↑”(Note 24)
BICK “↑”to FCK Edge (Note 24)
FCK to SDTO (MSB) (Except I2S mode)
BICK “↓”to SDTO
SDTI Hold Time
SDTI Setup Time
tFCKB
tBFCK
tFSD
tBSD
tSDH
tSDS
50
50
-
-
50
50
-
-
-
-
-
-
-
-
80
80
-
-
ns
ns
ns
ns
ns
ns
Downloaded from Elcodis.com electronic components distributor
ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 16 -
Parameter Symbol min typ max Units
EXT Master Mode (Figure 2)
MCKI Frequency: 256fs
512fs
1024fs
Pulse Width Low
Pulse Width High
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
2.048
4.096
8.192
-
-
12.288
13.312
13.312
-
-
MHz
MHz
MHz
ns
ns
FCK Frequency (MCKI = 256fs)
(MCKI = 512fs)
(MCKI = 1024fs)
Duty Cycle
fFCK
fFCK
fFCK
dFCK
7.35
7.35
7.35
-
8
8
8
50
48
26
13
-
kHz
kHz
kHz
%
BICK: Period (BCKO1-0 bit= “00”)
(BCKO1-0 bit= “01”)
(BCKO1-0 bit= “10”)
Duty Cycle
tBCK
tBCK
tBCK
dBCK
-
-
-
-
1/16fFCK
1/32fFCK
1/64fFCK
50
-
-
-
-
ns
ns
ns
%
Audio Interface Timing
DSP Mode: (Figure 3, Figure 4)
FCK “↑”to BICK “↑”(Note 22)
FCK “↑”to BICK “↓”(Note 23)
BICK “↑”to SDTO (BCKP bit= “0”)
BICK “↓”to SDTO (BCKP bit= “1”)
SDTI Hold Time
SDTI Setup Time
tDBF
tDBF
tBSD
tBSD
tSDH
tSDS
0.5 x tBCK -40
0.5 x tBCK -40
-70
-70
50
50
0.5 x tBCK
0.5 x tBCK
-
-
-
-
0.5 x tBCK + 40
0.5 x tBCK +40
70
70
-
-
ns
ns
ns
ns
ns
ns
Except DSP Mode: (Figure 5)
BICK “↓”to FCK Edge
FCK to SDTO (MSB)
(Except I2S mode)
BICK “↓”to SDTO
SDTI Hold Time
SDTI Setup Time
tBFCK
tFSD
tBSD
tSDH
tSDS
-40
-70
-70
50
50
-
-
-
-
-
40
70
70
-
-
ns
ns
ns
ns
ns
Note 21. Duty Cycle = (the width of “L”) / (the period of clock) ×100
Note 22. MSBS, BCKP bits = “00”or “11”
Note 23. MSBS, BCKP bits = “01”or “10”
Note 24. BICK rising edge must not occur at the same time as FCK edge.
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ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 17 -
Parameter Symbol min typ max Units
Control Interface Timing:
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H”Time
CSN “↓“to CCLK “↑“
CCLK “↑“to CSN “↑“
CCLK “↓“to CDTI (at Read Command)
CSN “↑“to CDTI (Hi-Z) (at Read Command)
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
40
40
150
150
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 25)
PMADC “↑“to SDTO valid (Note 26)
ADRST bit = “0”
ADRST bit = “1”
tPD
tPDV
tPDV
150
-
-
-
1059
291
-
-
-
ns
1/fs
1/fs
Note 25. The AK4633 can be reset by the PDN pin = “L”.
Note 26. This is the count of FCK “↑“from the PMADC = “1”.
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ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 18 -
Timing Diagram
FCK
1/fCLK
MCKI
tCLKH tCLKL
VIH
VIL
1/fMCK
MCKO
tMCKOH tMCKOL
50%DVDD
1/fFCK
dFCK dFCK
50%DVDD
dMCK = tMCKOL x fMCK x 100%
Figure 2. Clock Timing (PLL/EXT Master mode) (MCKO isn’t available at EXT Master Mode)
FCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI VIL
tSDH
VIH
dBCK
tDBF
50%DVDD
tBCK
MSB
MSB
BICK 50%DVDD
(BCKP = "0")
(BCKP = "1")
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
Downloaded from Elcodis.com electronic components distributor
ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 19 -
FCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI VIL
tSDH
VIH
dBCK
tDBF
50%DVDD
tBCK
MSB
BICK 50%DVDD
(BCKP = "1")
(BCKP = "0")
MSB
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)
FCK 50%DVDD
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI VIL
tSDH
VIH
tBFCK dBCK
tFSD
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
Downloaded from Elcodis.com electronic components distributor
ASAHI KASEI [AK4633]
MS0447-E-03 2006/04
- 20 -
1/fFCK
FCK VIH
tFCKH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
tBFCK
BICK VIH
VIL
(BCKP = "0")
(BCKP = "1")
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 0)
1/fFCK
FCK VIH
tFCKH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
tBFCK
BICK VIH
VIL
(BCKP = "1")
(BCKP = "0")
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1)
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