Altera Enpirion EN63A0QI User manual

Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
Enpirion EN63A0QI 12A DC/DC Converter
w/Integrated Inductor Evaluation Board
Introduction
Thank you for choosing Altera®Enpirion power products!
This user guide should be used together with the latest device datasheet.
•The EN63A0QI features integrated inductor, power MOSFETS, controller,
bulk of the compensation network, and protection circuitry against system
faults. This level of integration delivers a substantial reduction in footprint
and part count over competing solutions. This evaluation board is
optimized for ease of use through programming options, clip leads, test
points, etc.
•The EN63A0QI features a customer programmable output voltage by
means of a resistor divider. The resistor divider allows the user to set the
output voltage to any value within the range 0.6V to (VIN-VDROPOUT). The
Dropout voltage is ~0.05*ILOAD (see Figure 1). The evaluation board, as
shipped is populated with a single RA, and three possible RBresistors. The
RBresistors can be chosen by jumper settings to achieve several output
voltages.
•The EN63A0QI includes the bulk of the compensation network internally.
However, an external phase-lead (zero) capacitor and resistor is required
as part of the feedback. This network is shown in Figure 1. Appropriate
component values allow for optimum compensation for a given Input
voltage and choice of loop bandwidth. The equations in Figure 1 provide
the details to calculate the component values.
•A footprint is provided for a SMC connector (not populated) for S_IN. A
clock source may be applied to S_IN to synchronize the device switching
frequency to the external source. Please see the datasheet for the
frequency lock frequency range. S_OUT will output a clock signal
synchronous with the switching frequency. S_OUT of one EN63A0QI may
be connected to S_IN of another EN63A0QI device.
•Jumpers are provided for logical programming of the following signals:
oENABLE (ENA)
oMaster/Slave ternary input (M/S)
oEnable Pre-Bias Input (SEL)
Enable may also be controlled using an external switching source by
removing the jumper and applying the enable signal to the connector
middle pin and ground.
oJumpers are also provided for getting various output voltages.
•The board comes with input decoupling and reverse polarity protection to
guard the device against commonsetup mishaps.
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
•The board also has soldermask openings for 0805 ceramic capacitors at
the input and output edges. If you are planning to do radiated any EMI
testing on this board, place a 10uF, 0805, X7R or X5R capacitor at each
board edge. The added capacitor at the input edge is for high-frequency
decoupling of the input cables. The added capacitor at the output edge is
meant to represent a typical load decoupling capacitor.
V
OUT
R
A
C
A
R
B
V
FB
R
1
Figure 1: Output voltage programming and loop compensation.
Quick Start Guide
Figure 2: J2 allows control of the Enable pin.
The jumper on Enable pin as shown is in disable mode. When jumper is between
the middle and right pins the signal pin is connected to ground or logic low. When
the jumper is between the left and middle pins, the signal pin is connected to VIN
or logic High.
WARNING: complete steps 1 through 4 before applying power to the EN63A0QI
evaluation board.
STEP 1: Set the “ENA” jumper to the Disable Position.
STEP 2: Set the output voltage by putting a jumper in the desired positions for
connector header J5 as shown below. In order for this board to work,
VIN
SIDE
GND
SIDE
Ω=








−
×
=
Ω
×
=
Ω×=
−
kR
V
VV RV
R
R
C
VR
FB
FBOUT
AFB
B
A
A
A
12
106.4
/400,48
1
6
nominal
0.6Vis
value.calculatedthe thanlowervalueavailable closesttodownCRound
)F/in/R(C
V)in/V(R
A
AA
INAIN
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
you always need a jumper in the leftmost position of J5 as shown in
Figure 3. If all other jumper positions are left open, then RBwill be
open, and VOUT will be 0.6V nominal. The other positions will select the
three possible RBresistors. Table 1 shows the RAand all possible RB
values, and the resulting VOUT for each combination of RAand single
RB. Please see Figures 1 and 5. It is possible to use parallel
combinations of the three RBresistors to get other output voltages.
Please note the RA, CA, and RBvalues for this board have been
optimized for an input voltage of around 6V using the equations in
Figure 1. The part will be stable for lower VIN values, but to get
optimum transient response, new RA, CA, and RBvalues have to be
calculated and installed.
Figure 3: Shows the voltage selection jumpers
The leftmost position has to always have a jumper in it. Nominal
output voltages, from left to right, for second through fourth positions
are 1.80V, 1.20V, and 1.02V. Jumpers as shown, select 1.20V output.
CAUTION:Except ENA, no other jumpers can be changed while the
EN63A0QI is enabled. Doing so could result in damage to the part.
Always disable part when changing output voltage setting.
Reference Designator
Nominal Value
Nominal VOUT
R3 (RAin Figure 1)
301kΩ
0.6V with no RB
R8 (RBin Figure 1)
150kΩ
1.80V
R7 (RBin Figure 1)
301kΩ
1.20V
R6 (RBin Figure 1)
430kΩ
1.02V
Table 1 – VOUT resistor divider values and the resulting output voltages if only
a single RBis used. You could use more than one RBand get other output
voltages. Use the third equation in Figure 1, and solve for VOUT.
STEP 3: Assuming parallel operation is not needed, leave the M/S jumper not
populated (floating).
STEP 4:The SEL jumper controls the EN_PB pin. If left floating, this pin is
pulled high internally, and the device will support monotonic startup under pre-
biased load. To pull this pin low, put the jumper between the middle and right
pins just as shown in Figure 2 for the ENABLE pin.
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
STEP 5:Connect Power Supply to the input power connectors, VIN (J7) and
GND (J11) as indicated in Figure 4 and set the power supply to the desired
voltage (≤6.6V.)
CAUTION:Be mindful of the polarity. Even though the evaluation board
comes with reverse polarity protection diodes, it may not protect the
device under all conditions.
STEP 6:Connect the load to the output connectors VOUT (J6) and GND (J10),
as indicated in Figure 4.
STEP 7:Power up the board and move the ENA jumper to the enabled position.
The EN63A0QI is now powered up and generating the desired output. You are
free to make Efficiency, Ripple, Line/Load Regulation, Load transient, Power OK,
over current limit and temperature related measurements.
STEP 7A: Power Up/Down Behavior – Remove ENA jumper and connect a
pulse generator (output disabled) signal to the middle pin of ENA and Ground.
Set the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to
10msec., duty cycle to 50% and fast transition (<1usec.) Hook up oscilloscope
probes to ENA, POK and VOUT with clean ground returns. Enable pulse generator
output. Observe the VOUT voltage ramps as ENA goes high and again as ENA
goes low.
STEP 8: Phase Lock – Disable device by moving ENA jumper. Power down the
device. Connect a pulse generator (properly terminated and output disabled)
signal between S_IN and GND, preferably using an SMC connector. Set the
pulse amplitude to swing from 0 to 2.5 volts. Set the pulse frequency to the
converter’s free running frequency. Connect oscilloscope probes to S_IN and
S_OUT. Power up device. Enable device. Note S_OUT – it is the free running
switching frequency. Now enable the pulse generator output. S_OUT should be
locked to S_IN with a fixed delay. Sweep the clock frequency within the External
Sync Clock Frequency Lock Range as specified in the datasheet, and note the
lock range at both extremes.
ALWAYS power down device before changing board level components!
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
Figure 4: Evaluation Board Layout Assembly Layer.
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
D1
S2A
+C14
VIN
TP27
J7
J6
J11
1206
1210
1210
1206
C1
FB1
C4
0805
0805
0805
0805
0805 0805
C8
C9
R11
VFB
J2
1
2 3
J3
1
2 3
TP6
0805
0805
J10
VOUT
M/S
ENA
J4
TP9
1
2
C3
TP15
TP14
R2
1206
C2
VIN
PGND
ENA
M/S
POK
VOUT PGND
C15
0805
0805
C5
C6
R8
R7
R3
R6
C7
AVIN
0402
0402
TP30
TP31
J1
1 2
3
R13
VFB
R14
VFB
R4
SEL
TP3
0805
SEL
TP5
FADJ
XREF
0805 0805
R5
TP21
TP22
TP32
0805
SIN
SOUT
SCH 04696
PCB 04697
Provision for Implementing
Adaptive Voltage Scaling
0402
1210
C10
C12
C11
C13
TP19
1 2
TP20
1
2
C16
R10
VIN
VOUT
R1
TP10
0402
TP8
TP7
J5
1 3
5
2 4
6
87
D2
TP28
BF_IN
0805
TP29
TP17
1
2
TP18
1
2
R9
TP11
U1
EN63A0Q
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
NC19
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
VOUT
25
VOUT
26
VOUT
27
VOUT
28
NC29
29
NC(SW)30
30
NC(SW)31
31
PGND
32
PGND
33
PGND
34
PGND
35
PGND
36
PGND
37
S_IN 56
PGND 55
VDDB 54
NC53 53
NC52 52
PVIN 51
PVIN 50
PVIN 49
PVIN 48
PVIN 47
PVIN 46
PVIN 45
PVIN 44
PVIN 43
NC76 76
NC75 75
NC74 74
NC73 73
NC72 72
NC(SW)71 71
NC(SW)70 70
EN_PB 69
FQADJ 68
EXTREF 67 VSENSE 66
SS 65
EAOUT 64
VFB 63
M/S 62
AGND 61
AVIN 60
ENABLE 59
POK 58
PGND
38 S_OUT 57
PVIN 42
PVIN 41
PVIN 40
PVIN 39
NC15
15
NC16
16
NC17
17
NC18
18
TP12
Short across R9
when all other
routing completed
TP4
TP1
VIN
TP23
TP2
TP16
TP24
TP25
TP13
TP26
U2
Figure 5: Evaluation Board Schematic
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
Test Recommendations
Recommendations
To guarantee measurement accuracy, the following precautions should be
observed:
1. Make all input and output voltage measurements at the board using the
surface-mount test points provided. This will eliminate voltage drop
across the line and load cables that can produce false readings.
2. Measure input and output current with series ammeters or accurate
shunt resistors. This is especially important when measuring efficiency.
3. Use a low-loop-inductance probe tip shown below to measure VOUT
and switching signals to avoid noise coupling into the probe ground
lead. Output ripple and load transient deviations are conveniently
measured at TP19. For more accurate ripple measurement, please
refer to Enpirion App Note regarding this subject.
4. The board includes a pull-up for the POK signal and ready to monitor
the power OK status.
5. A soft-start capacitor is populated on the board to provide a reasonable
soft-start time. It can be changed as needed.
6. The over-current protection circuit typically limits the maximum load
current to approximately 14.5A.
Input and Output Capacitors
Please refer to the BOM section for the value of input caps and output caps used
on this evaluation board, which is the result of combination for better
performance and smaller footprints.
NOTE: Capacitors must be X5R or X7R dielectric formulations to ensure
adequate capacitance over operating voltage and temperature ranges.
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Enpirion®Power EvaluationBoardUser Guide
EN63A0QI PowerSoC
Bill of Materials
Designator
Qty
Description
C1
1
CAP, 10uF 0805 X7R 10% 10V CERAMIC
C2
1
CAP, 15000pF 10% 50V SMD 0805 X7R CERAMIC
C3, C10-C13
5
CAP, CER 47UF 10V X5R 1206
C5
1
CAPACITOR CER .10UF 25V X5R 0402
C7
1
CAP, 15pF 50V CERM CHIP 0805 SMD
C14
1
CAP, SMTELECTROLYTIC, 150uF, 20%, 10V
C4, C6, C8,
C9, C15,
C16, J4, R2,
R9, R11,
R13, R14,
TP30-TP32
15
NOT USED
D1, D2
2
S2A DIODE
FB1 1
MULTILAYERSMDFERRITE BEAD4000MA 0805 L=TYPICAL
(NOT GUARANTED)
J1, J3
2
CONN, VERTICAL, 3 POSITION, SMT
J5
1
CONNECTOR HEADER 8 POS .100" STR TIN
J6, J7, J10,
J11
4
BANANA JACK
R1
1
RES 100K OHM 1/16W 1%0402 SMD
R3, R7
2
RES 301K OHM 1/8W 0.1%0805 SMD
R4
1
RES 12.1K OHM 1/8W 1% 0805 SMD
R5
1
RES 64.9K OHM 1/8W 0.1% 0805 SMD
R6
1
RES 430K OHM 1/8W 0.1%0805 SMD
R8
1
RES 150K OHM 1/8W 0.1%0805 SMD
R10
1
RES 4.42K OHM 1/8W 1% 0805 SMD
TP1-TP5,
TP13-TP16,
TP21, TP22
11 TESTPOINT SURFACE MOUNT
U1
1
EN63A0QI QFN 12A
U2 1
TRANSIENTVOLTAGE SUPPRESSOR,6.5V, BIDIRECTIONAL,
SMT
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: [phone]
www.altera.com
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