Ultra High Performance Audio ADC
384kHz, 24-Bit Conversion
Evaluation Kit User’s Guide AT1201EVK–R3.0
Rev. 1.1 Arda Technologies, Inc. Page 5 of 14
Clocking Modes
The AT1201EVK supports several mechanisms for providing a master clock to the device under test:
an external MCLK clock via BNC connector J7, on-board crystal oscillators Y1 and Y2, and an optional
phase-locked loop, which may be specified at the time of ordering. Source selection is performed by
using switches SW3:1..3 to select each of the MCLK sources, respectively. Note that only one of these
switches should be in the HIGH position at any time, and SW5:10 should be in the LOW position as
well. By default, the evaluation kit comes with a 24.576 MHz crystal oscillator in position Y2 and no
PLL oscillator.
The default 24.576 MHz crystal oscillator provides an on-board low jitter source for operating the
AT1201 at 48 kHz, 96 kHz, 192 kHz, and 384 kHz PCM modes in addition to MBO and DSD modes. For
clock rates at multiples of 44.1 kHz, an oscillator can be added at position Y1; this is also available
upon request from Arda.
PLL configuration
If your EVK is supplied with a phase-locked loop VCXO, it can be used by introducing a base-rate (PCM
mode) clock at the BNC connector, choosing the desired VCXO at SW5:8 or 9, and enabling the
external clock using SW5:10. The three MCLK sources at SW4 should be disabled, and only one VCXO
should be enabled at a time. The clock supplied to the BNC input should be within approximately 200
ppm above or below the desired base rate, and the AT1201 must have PCM mode enabled (SW4:8
HIGH) and be in Master mode (SW4:5 HIGH) for the PLL to lock. DSD and MBO modes can also be
used, though the MCLK is supplied by the EVK and locking to an external MCLK is not supported.
Overflow
The overflow indicator output from the IC carries overflow information for both channels as a time
multiplexed signal. The indicator drives an LED directly and is demuxed to drive two other LEDs
representing each channel.
Buffer Gain & Bandwidth
The analog input buffers, U2 and U3, have been designed for a 110 kHz -3dB, single pole roll-off. The
buffer bandwidth can be altered by changing passives around the operational amplifiers. This is a
complicated process that can have a significant impact on the performance of the DUT. Arda
Technologies will provide assistance if a different bandwidth is desired.
The signal gain through the input buffers is approximately 0.3 V/V, making the full-scale input level
+23dBu. As with the buffer bandwidth, the gain can be altered by changing passives. Arda
Technologies will provide assistance if a different gain is desired.
Digital Highpass Filter
A first-order IIR highpass filter is present in the PCM signal path. The -3dB frequency is 0.47Hz at Fs =
48kHz and scales with Fs. The filter is activated using SW3:7.
The highpass filter can be turned on for a few seconds to acquire the signal path offset and then
disabled. Once disabled, the offset continues to be subtracted from the signal, but the filter’s
frequency response is no longer present. Alternatively, the filter can be left enabled to operate
continuously.
