ARM Cortex-R4 Product manual
Copyright © 2006-2011 ARM Limited. All rights reserved.
ARM DDI 0363G (ID073015)
Cortex™-R4 and Cortex-R4F
Revision: r1p4
Technical Reference Manual
ARM DDI 0363G Copyright © 2006-2011 ARM Limited. All rights reserved. ii
ID073015 Non-Confidential
Cortex-R4 and Cortex-R4F
Technical Reference Manual
Copyright © 2006-2011 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM®in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Some material in this document is based on ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point
Arithmetic. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described
manner.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
15 May 2006 A Confidential First release for r0p1
22 October 2007 B Non-Confidential First release for r1p2
16 June 2008 C Non-Confidential Restricted Access First release for r1p3
11 September 2009 D Non-Confidential Second release for r1p3
20 November 2009 E Non-Confidential Documentation update for r1p3
12 February 2010 F Non-Confidential Documentation update for r1p3
04 April 2011 G Non-Confidential First release for r1p4
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Contents
Cortex-R4 and Cortex-R4F Technical Reference
Manual
Preface
About this book .............................................................................................................. viii
Feedback ........................................................................................................................ xii
Chapter 1 Introduction
1.1 About the processor ...................................................................................................... 1-2
1.2 Compliance ................................................................................................................... 1-3
1.3 Features ........................................................................................................................ 1-4
1.4 Interfaces ...................................................................................................................... 1-5
1.5 Configurable options ..................................................................................................... 1-6
1.6 Test features ............................................................................................................... 1-10
1.7 Product documentation, architecture and design flow ................................................ 1-11
1.8 Product revisions ........................................................................................................ 1-13
Chapter 2 Functional Description
2.1 About the functions ....................................................................................................... 2-2
2.2 Interfaces ...................................................................................................................... 2-9
2.3 Clocking and resets .................................................................................................... 2-11
2.4 Operation .................................................................................................................... 2-15
Chapter 3 Programmers Model
3.1 About the programmers model ..................................................................................... 3-2
3.2 Modes of operation and execution ................................................................................ 3-3
3.3 Memory model .............................................................................................................. 3-4
3.4 Data structures ............................................................................................................. 3-5
3.5 Registers ....................................................................................................................... 3-6
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3.6 Program status registers 3-9
3.7 Exceptions 3-14
3.8 Acceleration of execution environments 3-25
3.9 Unaligned and mixed-endian data access support 3-26
3.10 Big-endian instruction support 3-27
Chapter 4 System Control
4.1 About system control 4-2
4.2 Register summary 4-7
4.3 Register descriptions 4-9
Chapter 5 Prefetch Unit
5.1 About the prefetch unit 5-2
5.2 Branch prediction 5-3
5.3 Return stack 5-5
5.4 Controlling instruction prefetch and program flow prediction 5-6
Chapter 6 Events and Performance Monitor
6.1 About the events 6-2
6.2 About the PMU 6-6
6.3 Performance monitoring registers 6-7
6.4 Event bus interface 6-19
Chapter 7 Memory Protection Unit
7.1 About the MPU 7-2
7.2 Memory types 7-7
7.3 Region attributes 7-8
7.4 MPU interaction with memory system 7-9
7.5 MPU faults 7-10
7.6 MPU software-accessible registers 7-11
Chapter 8 Level One Memory System
8.1 About the L1 memory system 8-2
8.2 About the error detection and correction schemes 8-4
8.3 Fault handling 8-7
8.4 About the TCMs 8-13
8.5 About the caches 8-18
8.6 Internal exclusive monitor 8-34
8.7 Memory types and L1 memory system behavior 8-35
8.8 Error detection events 8-36
Chapter 9 Level Two Interface
9.1 About the L2 interface 9-2
9.2 AXI master interface 9-3
9.3 AXI master interface transfers 9-7
9.4 AXI slave interface 9-20
9.5 Enabling or disabling AXI slave accesses 9-23
9.6 Accessing RAMs using the AXI slave interface 9-24
Chapter 10 Power Control
10.1 About power control 10-2
10.2 Power management 10-3
Chapter 11 FPU Programmers Model
11.1 About the FPU programmers model 11-2
11.2 General-purpose registers 11-3
11.3 System registers 11-4
11.4 Modes of operation 11-11
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11.5 Compliance with the IEEE 754 standard 11-12
Chapter 12 Debug
12.1 Debug systems 12-2
12.2 About the debug unit 12-3
12.3 Debug register interface 12-5
12.4 Debug register descriptions 12-10
12.5 Management registers 12-35
12.6 Debug events 12-42
12.7 Debug exception 12-44
12.8 Debug state 12-47
12.9 Cache debug 12-53
12.10 External debug interface 12-54
12.11 Using the debug functionality 12-57
12.12 Debugging systems with energy management capabilities 12-74
Chapter 13 Integration Test Registers
13.1 About Integration Test Registers 13-2
13.2 Summary of the processor registers used for integration testing 13-3
13.3 Processor integration testing 13-4
Appendix A Signal Descriptions
A.1 About the processor signal descriptions A-2
A.2 Global signals A-3
A.3 Configuration signals A-4
A.4 Interrupt signals, including VIC interface signals A-7
A.5 L2 interface signals A-8
A.6 TCM interface signals A-13
A.7 Redundant processor signals A-16
A.8 Debug interface signals A-17
A.9 ETM interface signals A-19
A.10 Test signals A-20
A.11 MBIST signals A-21
A.12 Validation signals A-22
A.13 FPU signals A-23
Appendix B AC Characteristics
B.1 Processor timing B-2
B.2 Processor timing parameters B-3
Appendix C Cycle Timings and Interlock Behavior
C.1 About cycle timings and interlock behavior C-3
C.2 Register interlock examples C-6
C.3 Data processing instructions C-7
C.4 QADD, QDADD, QSUB, and QDSUB instructions C-9
C.5 Media data-processing C-10
C.6 Sum of Absolute Differences (SAD) C-11
C.7 Multiplies C-12
C.8 Divide C-14
C.9 Branches C-15
C.10 Processor state updating instructions C-16
C.11 Single load and store instructions C-17
C.12 Load and Store Double instructions C-20
C.13 Load and Store Multiple instructions C-21
C.14 RFE and SRS instructions C-24
C.15 Synchronization instructions C-25
C.16 Coprocessor instructions C-26
C.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions C-27
C.18 Miscellaneous instructions C-28
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C.19 Floating-point register transfer instructions C-29
C.20 Floating-point load/store instructions C-30
C.21 Floating-point single-precision data processing instructions C-32
C.22 Floating-point double-precision data processing instructions C-33
C.23 Dual issue C-34
Appendix D ECC Schemes
D.1 ECC scheme selection guidelines D-2
Appendix E Revisions
Preface
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About this book
This book is for Cortex-R4 and Cortex-R4F processors.
Note
• The Cortex-R4F processor is a Cortex-R4 processor that includes the optional Floating
Point Unit (FPU) extension.
• In this book, references to the Cortex-R4 processor also apply to the Cortex-R4F
processor, unless the context makes it clear that this is not the case.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this book, where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written for system designers, system integrators, and programmers who are
designing or programming a System-on-Chip (SoC) that uses the processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the processor and descriptions of the major
functional blocks.
Chapter 2 Functional Description
Read this for a description of the functionality of the processor.
Chapter 3 Programmers Model
Read this for a description of the processor registers and programming
information.
Chapter 4 System Control
Read this for a description of the system control coprocessor registers and
programming information.
Chapter 5 Prefetch Unit
Read this for a description of the functions of the Prefetch Unit (PFU), including
dynamic branch prediction and the return stack.
Chapter 6 Events and Performance Monitor
Read this for a description of the Performance Monitoring Unit (PMU) and the
event bus.
Chapter 7 Memory Protection Unit
Read this for a description of the Memory Protection Unit (MPU) and the access
permissions process.
Preface
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Chapter 8 Level One Memory System
Read this for a description of the Level One (L1) memory system.
Chapter 9 Level Two Interface
Read this for a description of the features of the Level Two (L2) interface not
covered in the AMBA®AXI Protocol Specification.
Chapter 10 Power Control
Read this for a description of the power control facilities.
Chapter 11 FPU Programmers Model
Read this for a description of the Floating Point Unit (FPU) support in the
Cortex-R4F processor.
Chapter 12 Debug
Read this for a description of the debug support.
Chapter 13 Integration Test Registers
Read this for a description of the Integration Test Registers, and of integration
testing of the processor with an ETM-R4 trace macrocell.
Appendix A Signal Descriptions
Read this for a description of the inputs and outputs of the processor.
Appendix B AC Characteristics
Read this for a description of the timing parameters applicable to the processor.
Appendix C Cycle Timings and Interlock Behavior
Read this for a description of the instruction cycle timing and instruction
interlocks.
Appendix D ECC Schemes
Read this for a description of how to select the Error Checking and Correction
(ECC) scheme depending on the Tightly-Coupled Memory (TCM) configuration.
Appendix E Revisions
Read this for a description of the technical changes between released issues of this
book.
Conventions
Conventions that this book can use are described in:
•Typographical
•Timing diagrams on page x
•Signals on page x.
Typographical
The typographical conventions are:
italic Introduces special terminology, denotes cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes signal
names. Also used for terms in descriptive lists, where appropriate.
Preface
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monospace
Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter
the underlined text instead of the full command or option name.
monospace
italic
Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace
bold
Denotes language keywords when used outside example code.
< and > Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing
diagrams. Variations, when they occur, have clear labels. You must not assume any timing
information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the
shaded area at that time. The actual level is unimportant and does not affect normal operation.
Key to timing diagram conventions
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and
they look similar to the bus change shown in Key to timing diagram conventions. If a timing
diagram shows a single-bit signal in this way then its value does not affect the accompanying
description.
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lower-case n At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This section lists publications by ARM and by third parties.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Preface
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See Infocenter,
http://infocenter.arm.com
, for access to ARM documentation.
See the glossary,
http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html
, for
a list of terms and acronyms specific to ARM.
See onARM,
http://onarm.com
, for embedded software development resources including the
Cortex Microcontroller Software Interface Standard (CMSIS).
ARM publications
This book contains information that is specific to the Cortex-R4 processor. See the following
documents for other relevant information:
•AMBA AXI Protocol Specification (ARM IHI 0022)
•AMBA 3 APB Protocol Specification (ARM IHI 0024)
•ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406)
•ARM PrimeCell®Vectored Interrupt Controller (PL192) Technical Reference Manual
(ARM DDI 0273)
•Cortex-R4 and Cortex-R4F Integration Manual (ARM DII 0130)
•Cortex-R4 and Cortex-R4F Configuration and Sign-off Guide (ARM DII 0185)
•CoreSight™Architecture Specification (ARM IHI 0029)
•CoreSight DAP-Lite Technical Reference Manual (ARM DDI 0316)
•CoreSight ETM-R4 Technical Reference Manual (ARM DII 0367)
•RealView®Compilation Tools Developer Guide (ARM DUI 0203)
•Application Note 98, VFP Support Code (ARM DAI 0098)
•ARM Synchronization Primitives (ARM DHT 0008).
Other publications
This section lists relevant documents published by third parties:
• ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic
• JEP106M, Standard Manufacturer Identification Code, JEDEC Solid State Technology
Association.
Preface
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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms and
diagnostic procedures if appropriate.
Feedback on content
If you have comments on content then send an e-mail to
. Give:
• the title
• the number, ARM DDI 0363G
• the page numbers to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.
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Chapter 1
Introduction
This chapter introduces the processor and its features. It contains the following sections:
•About the processor on page 1-2
•Compliance on page 1-3
•Features on page 1-4
•Interfaces on page 1-5
•Configurable options on page 1-6
•Test features on page 1-10
•Product documentation, architecture and design flow on page 1-11
•Product revisions on page 1-13
Introduction
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1.1 About the processor
The Cortex-R4 processor is a mid-range processor for use in deeply-embedded, real-time
systems. It implements the ARMv7R architecture, and includes Thumb-2 technology for
optimum code density and processing throughput. The pipeline has a single Arithmetic Logic
Unit (ALU), but implements limited dual-issuing of instructions for efficient utilization of other
resources such as the register file.
The processor has Tightly-Coupled Memory (TCM) ports for low-latency and deterministic
accesses to local RAM, in addition to caches for higher performance to general memory.
Error Checking and Correction (ECC) is used on the Cortex-R4 processor ports and in Level 1
(L1) memories to provide improved reliability and address safety-critical applications.
Many of the features, including the caches, TCM ports, and ECC are configurable so that a given
processor implementation can be tailored to the application for efficient area usage.
Figure 1-1 shows the processor in a typical system.
Figure 1-1 Example Cortex-R4 system
DMA
Cortex-R4 processor
AXI-M
Peripherals
ROM RAM
AXI-S
CoreSight
debug sub-
system
JTAG
Introduction
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1.2 Compliance
The Cortex-R4 processor complies with, or implements, the specifications described in:
•ARM architecture
•Trace macrocell
•Advanced Microcontroller Bus Architecture
•Debug architecture.
This TRM complements architecture reference manuals, architecture specifications, protocol
specifications, and relevant external standards. It does not duplicate information from these
sources.
1.2.1 ARM architecture
The Cortex-R4 processor implements the ARMv7-R architecture profile that includes the
following architecture extensions:
• Advanced Single Instruction Multiple Data (SIMD) architecture extension for integer and
floating-point vector operations
•Vector Floating-Point version 3 (VFPv3) architecture extension for floating-point
computation that is fully compliant with the IEEE 754 standard
See the ARM Architecture Reference Manual.
1.2.2 Trace macrocell
The Cortex-R4 processor implements the ETM v3.3 architecture profile. See the CoreSight
ETM-R4 Technical Reference Manual.
1.2.3 Advanced Microcontroller Bus Architecture
This Cortex-R4 processor complies with the AMBA 3 protocol. See AMBA AXI Protocol
Specification and AMBA 3 APB Protocol Specification.
1.2.4 Debug architecture
The Cortex-R4 processor implements the ARMv7 Debug architecture that includes support for
CoreSight. See the CoreSight Architecture Specification.
Introduction
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1.3 Features
The features of the processor include:
• A dual-issue integer unit with integral CoreSight logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible
Interfaces (AXI) for master and slave interfaces.
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack.
• Low interrupt latency.
• Non-maskable interrupt.
• Optional Floating Point Unit (FPU). The Cortex-R4F processor is a Cortex-R4 processor
that includes the FPU.
• A Harvard L1 memory system with:
— optional Tightly-Coupled Memory (TCM) interfaces with support for error
correction or parity checking memories
— optional caches with support for optional error correction schemes
— optional ARMv7-R architecture Memory Protection Unit (MPU)
— optional parity and Error Checking and Correction (ECC) on all RAM blocks.
• The ability to implement and use redundant core logic, for example, in fault detection.
• An L2 memory interface:
— single 64-bit master AXI interface
— 64-bit slave AXI interface to TCM RAM blocks and cache RAM blocks.
• A debug interface to a CoreSight Debug Access Port (DAP).
• A trace interface to a CoreSight ETM-R4.
•APerformance Monitoring Unit (PMU).
•AVectored Interrupt Controller (VIC) port.
Introduction
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1.4 Interfaces
The processor has the following interfaces:
• 64-bit AXI master interface, for instruction fetch and data access
• 64-bit AXI slave interface, for external access to TCMs and cache RAMs
• TCM interface, for access to local memory containing instructions and data
• VIC interface, for the connection of a PL192 VIC
• configuration signals for customizing the behavior of the processor, particularly from
reset
• interrupt outputs providing information about the behavior of the processor to the wider
system
• 32-bit APB slave interface and various debug handshake signals, for connection to
CoreSight components providing debug features
• ETM interface, for connection to a CoreSight ETM-R4 providing instruction and data
trace
•Memory Built-In Self Test (MBIST) interface and scan signals, enabling test during
manufacture of local RAMs and logic.
All the processor AMBA interfaces conform to one of the following AMBA 3 specifications:
•AMBA AXI Protocol Specification
•AMBA APB Protocol Specification.
The debug interfaces are CoreSight compliant, see the CoreSight Architecture Specification.
Introduction
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1.5 Configurable options
Table 1-1 shows the features of the processor that can be configured using either
build-configuration or pin-configuration. See Product documentation, architecture and design
flow on page 1-11 for information about configuration of the processor. Many of these features,
if included, can also be enabled and disabled during software configuration.
Table 1-1 Configurable options
Feature Options Sub-options Build-configuration
or pin-configuration
Redundant core Single-core (no redundancy) - Build
Dual-core (redundant) In-phase clocks
Out-of-phase clocks
Build
Instruction cache No Icache - Build
Icache included No error checking
Parity error checking
64-bit ECC error checking
Build
4KB (4x1KB ways)
8KB (4x2KB ways)
16KB (4x4KB ways)
32KB (4x8KB ways)
64KB (4x16KB ways)
Pin
Data cache No Dcache - Build
Dcache included No error checking
Parity error checking
32-bit ECC error checking
Build
4KB (4x1KB ways)
8KB (4x2KB ways)
16KB (4x4KB ways)
32KB (4x8KB ways)
64KB (4x16KB ways)
Pin
ATCM No ATCM ports - Build and pin
One ATCM port No error checking
Parity error checking
32-bit ECC error checking
64-bit ECC error checking
Build
4KB, 8KB, 16KB, 32KB, 64KB,
128KB, 256KB, 512KB, 1MB, 2MB,
4MB, or 8MB
Pin
Introduction
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BTCM No BTCM ports - Build and pin
One BTCM port (B0TCM) No error checking
Parity error checking
32-bit ECC error checking
64-bit ECC error checking
Build and pina
4KB, 8KB, 16KB, 32KB, 64KB,
128KB, 256KB, 512KB, 1MB, 2MB,
4MB, or 8MB
Pin
Two BTCM ports (B0TCM
and B1TCM)
No error checking
Parity error checking
32-bit ECC error checking
64-bit ECC error checking
Build
2x2KB, 2x4KB, 2x8KB, 2x16KB,
2x32KB, 2x64KB, 2x128KB,
2x256KB, 2x512KB, 2x1MB, 2x2MB,
or 2x4MB
Pin
Interleaved on 64-bit granularity in
memory
Adjacent in memory
Pin
Instruction
endianness
Little-endian - Build
Pin-configured Little-endian
Big-endian
Pin
Floating point
(VFP)
No FPU - Build
FPU includedb-
MPU No MPU - Build
MPU included 8 MPU regions
12 MPU regions
Build
TCM bus parity No TCM address and control
bus parity
- Build
TCM address and control
bus parity generated
-
AXI bus parity No AXI bus parity - Build
AXI bus parity generated/
checked
-
Breakpoints 2-8 breakpoint register pairs - Build
Watchpoints 1-8 watchpoint registers - Build
ATCM at reset Disabled - Pin
EnabledcBase address
0x0
Base address configured
Build and pin
Table 1-1 Configurable options (continued)
Feature Options Sub-options Build-configuration
or pin-configuration
Introduction
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Table 1-2 describes the various features that can be pin-configured to be either enabled or
disabled at reset. It also shows which CP15 register field provides software configuration of the
feature when the processor is out of reset. All of these fields exist in either the SCTLR, or one
of the auxiliary control registers.
BTCM at reset Disabled - Pin
EnabledcBase address configured
Base address
0x0
Build and pin
Peripheral ID
RevAnd field
Any 4-bit value - Build
AXI slave
interface
No AXI slave - Build
AXI slave included -
TCM Hard Error
Cache
No TCM Hard Error Cache - Build
TCM Hard Error Cache
included d
-
Non-Maskable
FIQ Interrupt
Disabled. FIQ can be
masked by software.
-Pin
Enabled -
Parity typeeOdd parity - Pin
Even parity -
a. The error scheme is a build option only. The number of BTCM ports (none, one, two) is set by both build and pin configuration.
b. Only available with the Cortex-R4F processor.
c. Only if the relevant TCM port(s) are included.
d. Only if at least one TCM port is included and uses ECC error checking.
e. Only relevant if at least one TCM port is included and uses parity error checking, one of the caches includes parity checking,
or AXI or TCM bus parity is included.
Table 1-1 Configurable options (continued)
Feature Options Sub-options Build-configuration
or pin-configuration
Table 1-2 Configurable options at reset
Feature Options Register field
Exception endianness Little-endian/big-endian data for exception handling SCTLR.EE
Exception state ARM/Thumb state for exception handling SCTLR.TE
Exception vector table Base address for exception vectors:
0x00000000
/
0xFFFF0000
SCTLR.V
TCM error checking ATCM parity check enableaACTLR.ATCMPCEN
BTCM parity check enable, for B0TCM and B1TCM independently aACTLR.B0TCMPCEN/
ACTLR.B1TCMPCEN
ATCM ECC check enableaACTLR.ATCMPCEN
BTCM ECC check enabled, for B0TCM and B1TCM togetheraACTLR.B0TCMPCEN/
ACTLR.B1TCMPCEN
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