ARM Cortex-M4 User manual

Copyright © 2010 ARM. All rights reserved.
ARM DUI 0553A (ID121610)
Cortex™-M4 Devices
Generic User Guide

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ID121610 Non-Confidential
Cortex-M4 Devices
Generic User Guide
Copyright © 2010 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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The product described in this document is subject to continuous developments and improvements. All particulars of the
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This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
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The information in this document is final, that is for a developed product.
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Change history
Date Issue Confidentiality Change
16 December 2010 A Non-Confidential First release

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Contents
Cortex-M4 Devices Generic User Guide
Preface
About this book ........................................................................................................... vi
Feedback .................................................................................................................... ix
Chapter 1 Introduction
1.1 About the Cortex-M4 processor and core peripherals ............................................. 1-2
Chapter 2 The Cortex-M4 Processor
2.1 Programmers model ................................................................................................ 2-2
2.2 Memory model ....................................................................................................... 2-12
2.3 Exception model .................................................................................................... 2-21
2.4 Fault handling ........................................................................................................ 2-29
2.5 Power management ............................................................................................... 2-32
Chapter 3 The Cortex-M4 Instruction Set
3.1 Instruction set summary ........................................................................................... 3-2
3.2 CMSIS functions ...................................................................................................... 3-9
3.3 About the instruction descriptions .......................................................................... 3-11
3.4 Memory access instructions .................................................................................. 3-22
3.5 General data processing instructions .................................................................... 3-39
3.6 Multiply and divide instructions .............................................................................. 3-74
3.7 Saturating instructions ........................................................................................... 3-95
3.8 Packing and unpacking instructions .................................................................... 3-107
3.9 Bitfield instructions ............................................................................................... 3-114
3.10 Branch and control instructions ........................................................................... 3-118
3.11 Floating-point instructions .................................................................................... 3-126
3.12 Miscellaneous instructions ................................................................................... 3-157

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Chapter 4 Cortex-M4 Peripherals
4.1 About the Cortex-M4 peripherals ............................................................................. 4-2
4.2 Nested Vectored Interrupt Controller ....................................................................... 4-3
4.3 System control block .............................................................................................. 4-11
4.4 System timer, SysTick ........................................................................................... 4-33
4.5 Optional Memory Protection Unit ........................................................................... 4-37
4.6 Floating Point Unit (FPU) ....................................................................................... 4-48
Appendix A Cortex-M4 Options
A.1 Cortex-M4 implementation options .......................................................................... A-2
Glossary

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Preface
This preface introduces the Cortex-M4 Devices Generic User Guide. It contains the following
sections:
•About this book on page vi
•Feedback on page ix.

Preface
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About this book
This book is a generic user guide for devices that implement the ARM Cortex-M4 processor.
Implementers of Cortex-M4 designs make a number of implementation choices, that can affect
the functionality of the device. This means that, in this book:
• some information is described as implementation-defined
• some features are described as optional.
In this book, unless the context indicates otherwise:
Processor Refers to the Cortex-M4 processor, as supplied by ARM.
Device Refers to an implemented device, supplied by an ARM partner, that incorporates
a Cortex-M4 processor. In particular, your device refers to the particular
implementation of the Cortex-M4 that you are using. Some features of your
device depend on the implementation choices made by the ARM partner that
made the device.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this book, where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written for application and system-level software developers, familiar with
programming, who want to program a device that includes the Cortex-M4 processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the Cortex-M4 processor and its features.
Chapter 2 The Cortex-M4 Processor
Read this for information about how to program the processor, the processor
memory model, exception and fault handling, and power management.
Chapter 3 The Cortex-M4 Instruction Set
Read this for information about the processor instruction set.
Chapter 4 Cortex-M4 Peripherals
Read this for information about Cortex-M4 peripherals.
Appendix A Cortex-M4 Options
Read this for information about the processor implementation and configuration
options.
Glossary Read this for definitions of terms used in this book.

Preface
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Typographical conventions
The typographical conventions used in this document are:
italic Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
bold Used for terms in descriptive lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as commands, file
and program names, and source code.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
< and > Enclose replaceable terms for assembler syntax where they appear in code
or code fragments. For example:
CMP Rn, <Rm|#imm>

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Additional reading
This section lists publications by ARM and by third parties.
See Infocenter, http://infocenter.arm.com, for access to ARM documentation.
See onARM, http://onarm.com, for embedded software development resources including the
Cortex Microcontroller Software Interface Standard (CMSIS).
ARM publications
This book contains information that is specific to this product. See the following documents for
other relevant information:
•Cortex-M4 Technical Reference Manual (ARM DDI 0439)
•ARMv7-M Architecture Reference Manual (ARM DDI 0403).
Other publications
This guide only provides generic information for devices that implement the ARM Cortex-M4
processor. For information about your device see the documentation published by the device
manufacturer.

Preface
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Feedback
ARM welcomes feedback on this product and its documentation.
Feedback on content
If you have comments on content then send an e-mail to
[email protected] . Give:
• the title
• the number, ARM DUI 0553A
• the page numbers to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

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Chapter 1
Introduction
This chapter introduces the Cortex-M4 processor and its features. It contains the following section:
•About the Cortex-M4 processor and core peripherals on page 1-2.

Introduction
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1.1 About the Cortex-M4 processor and core peripherals
The Cortex-M4 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
• outstanding processing performance combined with fast interrupt handling
• enhanced system debug with extensive breakpoint and trace capabilities
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep mode and an optional deep sleep
mode
• platform security robustness, with optional integrated Memory Protection Unit (MPU).
Figure 1-1 Cortex-M4 implementation
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively
optimized design, providing high-end processing hardware including optional
IEEE754-compliant single-precision floating-point computation, a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements
tightly-coupled system components that reduce processor area while significantly improving
interrupt handling and system debug capabilities. The Cortex-M4 processor implements a
version of the Thumb®instruction set based on Thumb-2 technology, ensuring high code density
and reduced program memory requirements. The Cortex-M4 instruction set provides the
exceptional performance expected of a modern 32-bit architecture, with the high code density
of 8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a
Non Maskable Interrupt (NMI) that can provide up to 256 interrupt priority levels. The tight
integration of the processor core and NVIC provides fast execution of Interrupt Service
Optional
Embedded
Trace Macrocell
NVIC
Optional
Debug
Access Port
Optional Memory
protection unit
Optional
WIC
Optional
Serial Wire
viewer
Bus matrix
Code
interface
SRAM and
peripheral interface
Optional
Data
watchpoints
Optional
Flash
patch
Cortex-M4
processor Optional FPU
Processor
core

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Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to suspend load-multiple and store-multiple
operations. Interrupt handlers do not require wrapping in assembler code, removing any code
overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when
switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that includes an
optional deep sleep function. This enables the entire device to be rapidly powered down while
still retaining program state.
1.1.1 System-level interface
The Cortex-M4 processor provides multiple interfaces using AMBA®technology to provide
high speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 processor has an optional Memory Protection Unit (MPU) that permits control
of individual regions in memory, enabling applications to utilize multiple privilege levels,
separating and protecting code, data and stack on a task-by-task basis. Such requirements are
becoming critical in many embedded applications such as automotive.
1.1.2 Optional integrated configurable debug
The Cortex-M4 processor can implement a complete hardware debug solution. This provides
high system visibility of the processor and memory through either a traditional JTAG port or a
2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package
devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
The optional Embedded Trace Macrocell™(ETM) delivers unrivalled instruction trace capture
in an area far smaller than traditional trace units, enabling many low cost MCUs to implement
full instruction trace for the first time.
The optional Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint
comparators that debuggers can use. The comparators in the FPB also provide remap functions
of up to eight words in the program code in the CODE memory region. This enables applications
stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable
memory, for example flash, is available in the device. During initialization, the application in
ROM detects, from the programmable memory, whether a patch is required. If a patch is
required, the application programs the FPB to remap a number of addresses. When those
addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration, which means the program in the non-modifiable ROM can be patched.
1.1.3 Cortex-M4 processor features and benefits summary
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• optional IEEE754-compliant single-precision FPU
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption

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• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast digital-signal-processing orientated multiply accumulate
• saturating arithmetic for signal processing
• deterministic, high-performance interrupt handling for time-critical applications
• optional Memory Protection Unit (MPU) for safety-critical applications
• extensive implementation-defined debug and trace capabilities:
— Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging, tracing, and code profiling.
1.1.4 Cortex-M4 core peripherals
These are:
Nested Vectored Interrupt Controller
The NVIC is an embedded interrupt controller that supports low latency interrupt
processing.
System Control Block
The System Control Block (SCB) is the programmers model interface to the
processor. It provides system implementation information and system control,
including configuration, control, and reporting of system exceptions.
System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time
Operating System (RTOS) tick timer or as a simple counter.
Memory Protection Unit
The Memory Protection Unit (MPU) improves system reliability by defining the
memory attributes for different memory regions. It provides up to eight different
regions, and an optional predefined background region.
Floating-point Unit
The Floating-Point Unit (FPU) provides IEEE754-compliant operations on
single-precision, 32-bit, floating-point values.

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Chapter 2
The Cortex-M4 Processor
This chapter describes the Cortex-M4 processor. It contains the following sections:
•Programmers model on page 2-2
•Memory model on page 2-12
•Exception model on page 2-21
•Fault handling on page 2-29
•Power management on page 2-32.

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2.1 Programmers model
This section describes the Cortex-M4 programmers model. In addition to the individual core
register descriptions, it contains information about the processor modes and privilege levels for
software execution and stacks.
2.1.1 Processor mode and privilege levels for software execution
The processor modes are:
Thread mode Used to execute application software. The processor enters Thread mode
when it comes out of reset.
Handler mode Used to handle exceptions. The processor returns to Thread mode when it
has finished all exception processing.
The privilege levels for software execution are:
Unprivileged The software:
• has limited access to the
MSR and MRS instructions, and cannot use the
CPS instruction
• cannot access the system timer, NVIC, or system control block
• might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
In Thread mode, the CONTROL register controls whether software execution is privileged or
unprivileged, see CONTROL register on page 2-9. In Handler mode, software execution is
always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for
software execution in Thread mode. Unprivileged software can use the
SVC instruction to make
a supervisor call to transfer control to privileged software.
2.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of
the last stacked item in memory. When the processor pushes a new item onto the stack, it
decrements the stack pointer and then writes the item to the new memory location. The
processor implements two stacks, the main stack and the process stack, with a pointer for each
held in independent registers, see Stack Pointer on page 2-4.
In Thread mode, the CONTROL register controls whether the processor uses the main stack or
the process stack, see CONTROL register on page 2-9. In Handler mode, the processor always
uses the main stack. The options for processor operations are:
Table 2-1 Summary of processor mode, execution privilege level, and stack use options
Processor
mode Used to execute Privilege level for
software execution Stack used
Thread Applications Privileged or unprivilegeda
a. See CONTROL register on page 2-9.
Main stack or process stacka
Handler Exception handlers Always privileged Main stack

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2.1.3 Core registers
The processor core registers are:
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡
Banked version of SP
Table 2-2 Core register set summary
Name Type aRequired privilegebReset value Description
R0-R12 RW Either Unknown General-purpose registers on page 2-4
MSP RW Privileged See description Stack Pointer on page 2-4
PSP RW Either Unknown Stack Pointer on page 2-4
LR RW Either
0xFFFFFFFF Link Register on page 2-4
PC RW Either See description Program Counter on page 2-4
PSR RW Privileged
0x01000000 Program Status Register on page 2-4
ASPR RW Either Unknown Application Program Status Register on page 2-5
IPSR RO Privileged
0x00000000 Interrupt Program Status Register on page 2-6
EPSR RO Privileged
0x01000000 Execution Program Status Register on page 2-6
PRIMASK RW Privileged
0x00000000 Priority Mask Register on page 2-8
FAULTMASK RW Privileged
0x00000000 Fault Mask Register on page 2-8
BASEPRI RW Privileged
0x00000000 Base Priority Mask Register on page 2-9
CONTROL RW Privileged
0x00000000 CONTROL register on page 2-9
a. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
b. An entry of Either means privileged and unprivileged software can access the register.

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General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
•0=Main Stack Pointer (MSP). This is the reset value.
•1=Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address
0x00000000 .
Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function
calls, and exceptions. On reset, the processor sets the LR value to
0xFFFFFFFF.
Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address
0x00000004 .
Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.
Program Status Register
The Program Status Register (PSR) combines:
•Application Program Status Register (APSR)
•Interrupt Program Status Register (IPSR)
•Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are:
Access these registers individually or as a combination of any two or all three registers, using
the register name as an argument to the
MSR or MRS instructions. For example:
• read all of the registers using
PSR with the MRS instruction
• write to the APSR N, Z, C, V, and Q bits using
APSR_nzcvq with the MSR instruction.
25 24 23
Reserved ISR_NUMBER
31 30 29 28 27
NZCV
0
Reserved
APSR
IPSR
EPSR Reserved Reserved
26 16 15 10 9
ReservedICI/IT ICI/ITT
Q
8

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The PSR combinations and attributes are:
See the instruction descriptions MRS on page 3-163 and MSR on page 3-164 for more
information about how to access the program status registers.
Application Program Status Register
The APSR contains the current state of the condition flags from previous instruction executions.
See the register summary in Table 2-2 on page 2-3 for its attributes. The bit assignments are:
Table 2-3 PSR register combinations
Register Type Combination
PSR RWa, b
a. The processor ignores writes to the IPSR
bits.
b. Reads of the EPSR bits return zero, and the
processor ignores writes to the these bits
APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
IAPSR RWaAPSR and IPSR
EAPSR RWbAPSR and EPSR
Table 2-4 APSR bit assignments
Bits Name Function
[31] N Negative flag
[30] Z Zero flag
[29] C Carry or borrow flag
[28] V Overflow flag
[27] Q DSP overflow and saturation flag
[26:20] - Reserved
[19:16] GE[3:0] Greater than or Equal flags. See SEL on
page 3-70 for more information.
[15:0] - Reserved

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Interrupt Program Status Register
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
See the register summary in Table 2-2 on page 2-3 for its attributes. The bit assignments are:
Execution Program Status Register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
•If-Then (IT) instruction
•Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in Table 2-2 on page 2-3 for the EPSR attributes. The bit assignments
are:
Table 2-5 IPSR bit assignments
Bits Name Function
[31:9] - Reserved
[8:0] ISR_NUMBER This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = HardFault
4 = MemManage
5 = BusFault
6 = UsageFault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0.
.
.
.
n+15 = IRQ(n-1)a
see Exception types on page 2-21 for more information.
a. The number of interrupts, n, is implementation-defined, in the range 1-240.
Table 2-6 EPSR bit assignments
Bits Name Function
[31:27] - Reserved.
[26:25], [15:10] ICI Interruptible-continuable instruction bits, see Interruptible-continuable instructions
on page 2-7.
[26:25], [15:10] IT Indicates the execution state bits of the
IT instruction, see IT on page 3-122.

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Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the
MSR instruction in application software
are ignored.
Interruptible-continuable instructions
When an interrupt occurs during the execution of an LDM , STM , PUSH , or POP instruction, and when
an FPU is implemented an
VLDM , VSTM , VPUSH , or VPOP instruction, the processor:
• stops the load multiple or store multiple instruction operation temporarily
• stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
• returns to the register pointed to by bits[15:12]
• resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
If-Then block
The If-Then block contains up to four instructions following an IT instruction. Each instruction
in the block is conditional. The conditions for the instructions are either all the same, or some
can be the inverse of others. See IT on page 3-122 for more information.
Thumb state
The Cortex-M4 processor only supports execution of instructions in Thumb state. The following
can clear the T bit to 0:
• instructions
BLX , BX and POP{PC }
• restoration from the stacked xPSR value on an exception return
• bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See Lockup
on page 2-31 for more information.
Exception mask registers
The exception mask registers disable the handling of exceptions by the processor. Disable
exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the
MSR and MRS instructions, or the CPS instruction to
change the value of PRIMASK or FAULTMASK. See MRS on page 3-163, MSR on page 3-164,
and CPS on page 3-159 for more information.
[24] T Thumb state bit, see Thumb state.
[23:16] - Reserved.
[9:0] - Reserved.
Table 2-6 EPSR bit assignments (continued)
Bits Name Function