ATI Audio DDA124-BNC Operating instructions

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DDA124-BNC
and
DDA224-BNC
AES/EBU DIGITAL AUDIO
DISTRIBUTION AMPLIFIERS
OPERATING AND MAINTENANCE MANUAL
© Copyright 2011, ATI Audio Inc.

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DESCRIPTION
The DDA124-BNC and DDA224-BNC Digital Audio Distribution Amplifiers are
designed to regenerate, isolate and distribute digital audio data formatted in
accordance with specifications AES3-1992 and IEC 958. This is commonly called
AES/EBU formatting.
The DDA124-BNC is a 1X24 unit with one loop-thru input feeding 24 isolated
outputs. The DDA224-BNC is a Dual 1X12 with two separate loop-thru inputs,
each feeding 12 isolated outputs.
These models use BNC connectors and operate from and drive single-ended 75-
ohm coaxial cable per AES-3id-1995 and are designed to integrate easily into
video facilities.
FEATURES
• Accepts sample rates from 27 to 96kHz
• Displays standard sample rates of 32, 44.1, 48, 88.2, 96 kHz
• Status and error LEDs show clock lock and data validity
• Adjustable input cable equalizers compensate for extremely long cable runs
• Data is relocked and regenerated before low-jitter transmission
• Loop thru transformer balanced and isolated inputs
• Switchable input termination resistors
• Individual isolated 75-ohm BNC outputs
• Single or dual inputs
• Up to 24 BNC outputs
• Quiet, internal linear power supplies
• Attractive, one rack unit package
DESCRIPTION
INPUTS
Incoming AES/EBU formatted digital audio data is applied to input transformers
T8 (T9 for second input channel of dual unit). Inputs are balanced and DC
isolated from ground. Input blocking capacitors C22 (C24) prevent accidental DC
inputs from saturating (and perhaps damaging) the input transformers. Input
termination resistors R25 (R26) at 75 ohms for BNC (and SP/DIF) inputs can be
switched in or out of the circuit with rear panel DIP switches S1a (S1b). Inputs
should always be terminated unless they are looped through to another device or
to another DDA input. The last device or input should always terminate the line.

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INPUT EQUALIZERS
The input signals feed cable equalizer circuits U3 (U4) and associated
components. Input equalization should only be necessary for extremely long
input cable lengths and should only be used if proven to be necessary. The
equalizers are adjustable with front panel multi-turn trimpots R63 (R66) so that
only the minimum amount of boost required to compensate for excess cable roll-
off can be added without over-equalization, which can degrade noise margins.
See adjustment instructions in the INSTALLATION section. If input equalization
is not required and you want to protect yourself from random control diddlers, you
may disable the equalizers by removing jumpers E4 (E5).
RECEIVERS
The equalized AES/EBU data stream is applied to the receiver circuit U8 (U17)
that is a Crystal Semiconductor CS8414 96kHz Digital Audio Receiver IC. The
CS8414 receives the data, recovers the clock and synchronization signals and
separates the audio and digital data. The audio data may be 16 to 24 bits at
sample rates from 27 to 96 kHz.
Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA), Channel
status (C), User channel data (U), and data validity information (VERF) are
passed directly to the transmitter IC for reformatting into the output data stream.
VERF is an OR’ing of the validity information from the incoming data (V) with an
internal error flag (ERF) that detects serious transmission errors such as parity
errors, bi-phase coding violations and an out-of-lock PLL receiver. VERF then
becomes the transmitted validity bit (V) and can be used by downstream error
correction devices to interpolate through errors.
Received frequency information is encoded on U8 (U17) pins F0, F1 and F2 and
is decoded by U14 (U19) into two BCD digits for display. Error information is
encoded on pins E0, E1 and E2. It is decoded by 3 to 8 line decoder U20 (U22)
and sent to the front panel display LEDs.
DISPLAYS
The two most significant digits of the sample rate are decoded by U1 AND U4
and displayed if the sample rate is within ±4% of a standard rate. Since only two
digits are displayed, readouts of 32, 44, 48, 88 and 96 correspond to actual
sampling rates within four percent of 32.0, 44.1, 48.0, 88.2 and 96kHz. The
displays are blanked if the detected frequency is out of range.
Data and transmission errors are displayed in priority order of No Lock, BI-
PHASE Coding errors, PARITY errors and CRC errors. The No-Lock signal is

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inverted and lights when the clock recovery PLL is in LOCK. The VALIDITY
indicator shows that the previous received sample was valid when transmitted
from the source device. NO ERROR is the absence of any of the other errors and
is good. The SET indicator, used to tune the equalizer adjustment, lights when
the received data eye opening is greater than half a bit period and the recovered
clock is within range.
TRANSMITTERS
The Frame sync (FSYNC), Serial Clock (SCK), Serial audio data (SDATA),
Channel status (C), User channel data (U), and data Validity information (VERF)
are passed directly to the transmitters U9 (U18) for reformatting into the
AES/EBU output data stream TXPA (TXPB). The transmitters are Crystal
Semiconductor CS8404A devices capable of operation from 27 to 96kHz
equivalent sample rates. The transmitters operate in a transparent mode, which
allows the transmitter block structure (Channel Status, User and Validity bits) to
be slaved to the block structure of the receiver. In the transparent mode the
propagation delay of data through the CS8404A is set so that the total
propagation delay from the receiver inputs to the transmitter outputs is exactly
three sample intervals, which is less than 100 microseconds even at the lowest
sample rate.
OUTPUT DRIVERS
BNC outputs are in accordance with the recommendations of AES-3id-1995.
Each side of the differential line driver output U1 and U2 (U5 and U6) is used to
separately drive a 75-ohm capacitor-coupled BNC output. Each BNC output
provides 4Vp-p open circuit thru 75 ohms for a loaded output of 2Vp-p. Although
the two sides of a differential line driver are out of phase with each other there is
no phase difference in the recovered audio since the AES/EBU digital data is
defined only by the presence or absence of transitions. It makes no difference
whether those transitions are hi to low or low to hi.
REFERENCE OSCILLATORS AND POWER SUPPLIES
U10 generates a 6 MHz reference frequency input to U8 (U17) for determining
the incoming frame (sample) rate. The oscillator is counted down in U11, 12, 15
and 16 to provide a synchronized display reset pulse every 3 seconds. U21
generates a precision 2.5VDC reference for the equalizer circuit. U7 and U13
provide regulated and quiet ±5VDC for all circuits. Power transformer primary
windings are paralleled for 115VAC or wired in series for 230VAC. Jumpers E1
allows field modification if necessary.

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INSTALLATION:
LOCATION
To avoid addition of jitter (timing variations) to the digital bitstream, which could
cause noise and distortion in the recovered audio, avoid locating the DDA in
close proximity to a high energy, high frequency switching type power supply or a
power amplifier that utilizes a switching supply. If possible, do not power both
devices from the same AC power line.
Expensive components start to die at internal temperatures above 70°C (158°F).
We recommend that you maintain rack temperatures below 50°C (122°F) to
prevent excessive internal temperature buildup. This is another good reason not
to mount the DDA directly above that 500W power amplifier. Don’t force the DDA
to support the weight of 28 coax cables (especially when you drop that 500W
power amplifier on the cable bundle); support the cables.
POWER
If it is necessary to convert a unit wired for 115VAC to 230VAC operation, unplug
the unit from the power source, remove the four cover mounting screws and
locate the E1 jumpers next to the power transformer. Clip the jumpers 1-2 and
3-4 (don’t unsolder), jumper from 2-3, carefully soldering together the free ends
of 2-3 previously clipped. This procedure is recommended to avoid soldering
damage to the multi-layer PC board.
WIRING
BNC connections require 75-ohm coax (RG59). Select a cable for losses less
than 20dB at 12MHz (for data rates up to 96kHz) at the maximum distance you
require. Runs up to 1000 meters should be readily achievable with low loss coax.
INPUT CABLE EQUALIZATION
If there is an unusually long (more than a few hundred feet) cable connection
between a particular AES/EBU data source and the DDA, it may be necessary to
equalize the cable response. Equalization would be indicated if it is not possible
to lock onto a known good signal source and obtain a stable reading of the DDA
input sample rate as evidenced by the front panel indicators.
1. Apply a known good AES/EBU digital signal at the source maximum sample
rate of 96, 88.2, 48, 44.1, or 32 kHz to the source end of the cable. (You can
validate the source by temporarily co-locating the DDA with the signal source,

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connecting them together with a short cable and noting that all red LEDs are off,
all green LEDs are on and the correct sample rate is steadily displayed.)
2. The factory default setting for the front panel equalizer control(s) is fully
counterclockwise. With a small screwdriver, slowly turn it clockwise, pausing after
each half turn for three seconds to allow the displays to update. Note the first
position at which all red LEDs are off, all green LEDs are on and the sample rate
is displayed steadily.
3. Continue to turn the control clockwise, counting turns, until the conditions of 2
above are no longer obtained.
4. Turn the control counterclockwise by half the number of turns counted in 3.
above. This is the optimum setting for the installed cable length and sample rate.

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SPECIFICATIONS:
INPUTS
Connectors: BNC, DC isolated from chassis
Input connector pairs are paralleled for loop-thru
Level: 200mVp-p minimum
Impedance: Transformer isolated, capacitor coupled, balanced and
floating, BNC inputs 75 ohms
Terminating resistors may be switched in or out on rear
panel via DIP switch
Cable Length: 1000 m of 75 ohm coax (with equalizer)
Equalizer: Multi-turn panel control, adjust using panel indicators
Sample Rates: Accepts 27kHz to >100kHz
Clock: Regenerated from input signal with dual-mode PLL Clock
Jitter: <3nanoseconds peak-to-peak at 96kHz sample rate
OUTPUTS
Connectors: BNC chassis mount, 12 or 24
Levels: 2Vp-p loaded at 75 ohms
Impedance: 75 ohms, unbalanced, capacitor coupled
Output Jitter: <3 nanoseconds peak-to-peak at 96kHz sample rate
Output Delay: Three frames (sample intervals) at the sample rate

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INDICATORS
Sample Rate: Numeric readout of first two digits of 32, 44.1, 48, 88.2,
96kHz rates if within ±4%; out of range blanks display
Received Signal: Status: NO ERROR, LOCK, VALIDITY, and all Green for
normal Operation
Error: PARITY, CRC, BIPHASE, normally OFF, Red for error
Cable Equalizer: SET indicator, lit Green for normal operation
Power: Lit RED for ON
POWER Internal supply, 115/230VAC ±10%, 50/60Hz, 10VA, IEC320
3 pin connector
SIZE 1 RU, 19” (48.3cm) W x 1 ¾” (4.5cm) H x 7”(19.1cm) D
WEIGHT 7lbs (3.2kg)

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One Year Limited Warranty
ATI warrants this product to be free from defects in materials and workmanship to its original
owner for a period of one year from date of purchase. ATI will repair or replace such product or
part thereof, which upon inspection by ATI, is found to be defective in materials or workmanship.
The Proper Return Authorization Number must be obtained from ATI in advance of return.
Contact ATI at 856-626-3480 or email [email protected] to receive the number and
instructions for return of your unit.
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of the original owner, together with receipt from the original purchase, and a brief description of
any claimed defects, must accompany all returns. Parts or product for which replacement is made
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and shall be required to prepay such costs.
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