Atmel 5.8 GHz WDCT Power Amplifier ATR7040 User manual

Features
•Frequency Range 5 GHz to 6 GHz
•Pout 25 dBm at 5.8 GHz
•Gain Typically 30 dB
•Pin Typically 0 dBm
•VCC 2.7V to 3.8V
•Power Consumption in Power-down Mode Typically < 1 µA
•Package: QFN16 3 mm ×3 mm
Benefits
•Biasing Control Extends Battery Time
•Simple Input and Output Matching
•Only One Single Supply Required
•No High-side Switching Transistor Required
1. Description
1.1 Process
This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe)
process and provides high efficiency.
1.2 Circuitry
The PA, ATR7040, consists of a three-stage amplifier with a typical output power of
25 dBm. The output stage was implemented using an open-collector structure. Power
up, power down, and output level are controlled at bias control pin 6 (Vctl).
5.8 GHz WDCT
Power Amplifier
ATR7040
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ATR7040
Figure 1-1. Block Diagram
Bias control
RFIN
10
RFOUT/VCC3
2
13
VCTL
15
VCC_CTL
VCC1
7
ATR7040
RFOUT/VCC3
3
Matching Matching
VCC2
6
14
GND
PADDLE
GND

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ATR7040
2. Pin Configuration
Figure 2-1. Pinning QFN16
NC
RFOUT/VCC3
RFOUT/VCC3
NC
NC
NC
RFIN
NC
NC
VCC_CTL
GND
VCTL
NC
VCC2
VCC1
NC
16 15 14 13
5 6 7 8
1
2
3
4
12
11
10
9
GND on the
PADDLE
ATR7040
Table 2-1. Pin Description
Pin Symbol Function
1 NC Not connected(1)
2 RFOUT RF output and supply voltage for output amplifier stage
3 RFOUT RF output and supply voltage for output amplifier stage
4 NC Not connected(1)
5 NC Not connected(1)
6 VCC2 Supply voltage for second amplifier stage
7 VCC1 Supply voltage for first amplifier stage
8 NC Not connected(1)
9 NC Not connected(1)
10 RFIN RF input
11 NC Not connected(1)
12 NC Not connected(1)
13 VCTL Control voltage for power ramping
14 GND Ground
15 VCC_CTL Supply voltage for biasing control block
16 NC Not connected(1)
PADDLE – Ground
Note: 1. Pin can be connected to paddle for increased GND area

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ATR7040
Electrostatic sensitive device.
Observe precautions for handling.
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Supply voltage VCC 5V
Supply current Icc 400 mA
Junction temperature Tj150 °C
Storage temperature TStg –40 to +125 °C
Input RF power Pin 10 dBm
Control voltage Vctl 2.5 V
Note: The part may not survive all maximums applied simultaneously.
4. Thermal Resistance
Parameters Symbol Value Unit
Junction ambient package QFN16, 3 × 3,
slug soldered on PCB RthJA 40 K/W
5. Operating Range
Parameters Symbol Value Unit
Supply voltage VCC 2.7 to 3.8 V
Operating frequency range fin 5100 to 5900 MHz
Ambient temperature range Tamb –25 to +75 °C

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7. Application Circuit
Figure 7-1. Application Circuit
6. Electrical Characteristics
Operating conditions: VCC = 3.6V, Vctl = 1.5V, input frequency = 5.8 GHz, input power 0 dBm, pulsed mode, duty cycle 10%, ton = 1 ms,
Tamb = 25°C, unless otherwise specified.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
1.0 Frequency range Depends on external
circuitry 5100 5900 MHz
1.1 Supply voltage Vcc 2.7 3.6 3.8 V
1.2 Input power Pin 0dBm
1.3 Saturated power output Psat 25 dBm
1.4 Output power deviation Pd–2 +2 dB
1.5 Control voltage range PA operating mode Vctl 1.0 1.7 V
Power-down mode Vctl 0.2 V
1.6 Control input current PA on 5 Ictl 90 µA
1.7 Input return loss With external matching 10 –7 –6 dB
1.8 Isolation Vctl ≤0.2V ISOr33 35 dB
1.9 Power added efficiency At power saturation,
Pin =0dBm PA E 3 5 %
1.10 Current consumption For 25 dBm output power Icc 250 mA
1.11 Current consumption in
power-down mode Vctl ≤0.2V Icc 1µA
1.12 Duty cycle of operation At saturated output power 100 %
C1
8
4
1
2
3
9
12
11
10
765
13 14 15 16
VCCVCTL
VCC
slug
L1
C3
C6
RFOU
T
RFIN
TRL2
TRL1
C2

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ATR7040
8. Diagrams
Figure 8-1. Output Power, Efficiency and Supply Currents Versus Input Frequency
Figure 8-2. Output Power, Gain, Efficiency and Supply Currents Versus Input Power
Figure 8-3. Output Power, Efficiency and Supply Currents Versus Operating Voltage
10
15
20
25
30
35
40
56 0 0 56 50 570 0 5750 58 0 0 58 50 59 0 0 59 50 6000
Frequency (MHz)
Pout (dBm), PAE %
0
50
10 0
15 0
200
250
300
350
400
Iges (mA)
Pin = 0 dBm, Vcc = 3.6V, Vctl = 1.4V
PAE (%)
Iges (mA)
Pout (dBm)
-30
-20
-10
0
10
20
30
40
-20 -15 -10 -5 0 5
Pin (dBm)
Pout (dBm), Gain (dB), PAE (%)
0
50
10 0
15 0
200
250
300
350
400
Pout (dBm)
Iges (mA)
Iges (mA)
Freq = 5800 MHz, Vcc = 3.6V, Vctl = 1.4V
PAE (%)
Gain (dB)
Vcc (V)
Pout (dBm), PAE (%)
Iges (mA)
Freq = 5800 MHz, Pin = 0 dBm, Vctl = 1.5V
10
15
20
25
30
35
40
2.5 3.0 3.5 4.0
0
50
10 0
15 0
200
250
300
350
400
450
PAE (%)
Pout (dBm)
Iges (mA)

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10. Package Information
9. Ordering Information
Extended Type Number Package Remarks
ATR7040-PVPG QFN16, 3 ×3 Taped and reeled, MOQ 2000, Pb-free
ATR7040-PVQG QFN16, 3 ×3 Taped and reeled, MOQ 8000, Pb-free
1
4
16
0.25
3
1.7
1613
12 1
58
0.4±0.1
0.9±0.1
0.05
0.5 nom.
1.5
+0
-0.05
2.68
0.15
specifications
according to DIN
technical drawings
Not indicated tolerances ±0.05
Dimensions in mm
Package: QFN 16 - 3x3
Exposed pad 1.7x1.7
(acc. JEDEC OUTLINE No. MO-220)
Drawing-No.: 6.543-5115.01-4
Issue: 1; 07.03.05
Assembly Chip PAC
94

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