Atmel AT86RF232 User manual

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8321A–MCU Wireless–10/11
AT86RF232
Features
•High Performance RF-CMOS 2.4GHz radio transceiver targeted for
IEEE®802.15.4, ZigBee®, RF4CE, 6LoWPAN, and ISM applications
•Industry leading link budget:
- Receiver sensitivity -100dBm
- Programmable output power from -17dBm up to +3dBm
•Ultra-low current consumption:
- SLEEP = 0.4µA
- TRX_OFF = 330µA
- RX_ON = 11.8mA (LISTEN)
- BUSY_TX = 13.8mA (at max. transmit power)
•Ultra-low supply voltage (1.8V to 3.6V) with internal regulator
•Support for coin cell operation
•Optimized for low BoM cost and ease of production:
- Few external components necessary (crystal, capacitors and antenna)
•Easy to use interface:
- Registers, frame buffer and AES accessible through fast SPI
- Only two microcontroller GPIO lines necessary
- One interrupt pin from radio transceiver
- Clock output
•Radio transceiver features:
- 128-byte FIFO (SRAM) for data buffering
- Fully integrated, fast settling PLL to support Frequency Hopping
- Battery monitor
- Fast Wake-Up time < 0.4msec
•Special IEEE 802.15.4™-2011 hardware support:
- FCS computation and Clear Channel Assessment
- RSSI measurement, Energy Detection and Link Quality Indication
•MAC hardware accelerator:
- Automated acknowledgement, CSMA-CA and retransmission
- Automatic address filtering
- Automated FCS check
•Extended feature set hardware support:
- AES 128-bit hardware accelerator
- Antenna Diversity
- True Random Number Generation for security application
•Commercial temperature range:
- 0°C to +70°C
•I/O and packages:
- 32-pin low-profile QFN package 5 x 5 x 0.9mm³
- RoHS/Fully Green
•Compliant to IEEE 802.15.4-2011, IEEE 802.15.4-2006 and IEEE 802.15.4-2003
•Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210
Low Power,
2.4GHz
Transceiver for
ZigBee,
IEEE 802.15.4,
6LoWPAN,
RF4CE and ISM
Applications
AT86RF232
PRELIMINARY
Rev. 8321A–MCU Wireless–10/11
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AT86RF232
1 Pin-out Diagram
Figure 1-1. Atmel AT86RF232 Pin-out Diagram.
32
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
AT86RF232
CLKM
DVSS
AVSS
AVSS
AVSS
AVSS
RFP
RFN
DVSS
/RST
DIG1 DIG2
SLP_TR
DVSS
DVDD DVDD
DEVDD
DVSS
SCLK
MISO
DVSS
MOSI
/SEL
IRQ
XTAL2 XTAL1 AVSS EVDD AVDD AVSS AVSS AVSS
31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
AVSS
exposed paddle
Note:
1. The exposed paddle is electrically connected to the die inside the package. It
shall be soldered to the board to ensure electrical and thermal contact and good
mechanical stability.
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AT86RF232
1.1 Pin Descriptions
Table 1-1. Atmel AT86RF232 Pin Description.
Pins
Name
Type
Description
1
AVSS
Ground
Analog ground
2
AVSS
Ground
Analog ground
3
AVSS
Ground
Ground for RF signals
4
RFP
RF I/O
Differential RF signal
5
RFN
RF I/O
Differential RF signal
6
AVSS
Ground
Ground for RF signals
7
DVSS
Ground
Digital ground
8
/RST
Digital input
Chip reset; active low
9
DIG1
Digital output (Ground)
1. Antenna Diversity RF switch control, see Section 11.3
2. If disabled, pull-down enabled (DVSS)
10
DIG2
Digital output (Ground)
1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.3
2. RX Frame Time Stamping, see Section 11.4
3. TX Frame Time Stamping, see Section 11.4
4. If functions disabled, pull-down enabled (DVSS)
11
SLP_TR
Digital input
Controls sleep, transmit start, receive states; active high, see Section 6.5
12
DVSS
Ground
Digital ground
13, 14
DVDD
Supply
Regulated 1.8V voltage regulator; digital domain, see Section 9.4
15
DEVDD
Supply
External supply voltage; digital domain
16
DVSS
Ground
Digital ground
17
CLKM
Digital output
Master clock signal output; low if disabled, see Section 9.6
18
DVSS
Ground
Digital ground
19
SCLK
Digital input
SPI clock
20
MISO
Digital output
SPI data output (master input slave output)
21
DVSS
Ground
Digital ground
22
MOSI
Digital input
SPI data input (master output slave input)
23
/SEL
Digital input
SPI select, active low
24
IRQ
Digital output
1. Interrupt request signal; active high or active low; configurable
2. Frame Buffer Empty Indicator; active high, see Section 11.5
25
XTAL2
Analog input
Crystal pin, see Section 9.6
26
XTAL1
Analog input
Crystal pin or external clock supply, see Section 9.6
27
AVSS
Ground
Analog ground
28
EVDD
Supply
External supply voltage, analog domain
29
AVDD
Supply
Regulated 1.8V voltage regulator; analog domain, see Section 9.4
30, 31, 32
AVSS
Ground
Analog ground
Paddle
AVSS
Ground
Analog ground; Exposed paddle of QFN package
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AT86RF232
1.2 Analog and RF Pins
1.2.1 Supply and Ground Pins
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the Atmel®AT86RF232
radio transceiver.
AVDD, DVDD
AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage
regulators can be configured for external supply.
For details, refer to Section 9.4.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively. The analog and
digital power domains should be separated on the PCB.
1.2.2 RF Pins
RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the
switching noise of the internal digital signal processing blocks. At board-level, the
differential RF layout ensures high receiver sensitivity by rejecting any spurious
emissions originated from other digital ICs such as a microcontroller.
A simplified schematic of the RF front end is shown in Figure 1-2.
Figure 1-2. Simplified RF Front-end Schematic.
LNA
PA
RXTX
0.9V
TX
RX
CM
Feedback
M0
AT86RF232PCB
The RF port is designed for a 100differential load. A DC path between the RF pins is
allowed. A DC path to ground or supply voltage is not allowed.
The RF port DC values depend on the operating state, see Chapter 7. In TRX_OFF
state, when the analog front-end is disabled (see Section 7.1.2.3), the RF pins are
pulled to ground, preventing a floating voltage.
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In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor
M0 is off, allowing the PA to set the common-mode voltage. The common-mode
capacitance at each pin to ground shall be < 30pF to ensure the stability of this
common-mode feedback loop.
In receive mode, the RF port provides a low-impedance path to ground when transistor
M0, see Figure 1-2, pulls the inductor center tap to ground. A DC voltage drop of 20mV
across the on-chip inductor can be measured at the RF pins.
1.2.3 Crystal Oscillator Pins
XTAL1, XTAL2
The pin 26 (XTAL1) of Atmel AT86RF232 is the input of the reference oscillator
amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal
oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in
Section 9.6.
When using an external clock reference signal, XTAL1 shall be used as input pin. For
further details, refer to Section 9.6.3.
1.2.4 Analog Pin Summary
Table 1-2. Analog Pin Behavior –DC values.
Pin
Values and Conditions
Comments
RFP/RFN
VDC = 0.9V (BUSY_TX)
VDC = 20mV (receive states)
VDC = 0mV (otherwise)
DC level at pins RFP/RFN for various transceiver states.
AC coupling is required if a circuitry with DC path to ground or
supply is used. Serial capacitance and capacitance of each pin
to ground must be < 30pF.
XTAL1/XTAL2
VDC = 0.9V at both pins
CPAR = 3pF
DC level at pins XTAL1/XTAL2 for various transceiver states.
Parasitic capacitance (Cpar) of the pins must be considered as
additional load capacitance to the crystal.
DVDD
VDC = 1.8V (all states, except SLEEP)
VDC = 0mV (otherwise)
DC level at pin DVDD for various transceiver states.
Supply pins (voltage regulator output) for the digital 1.8V
voltage domain, recommended bypass capacitor 100nF.
AVDD
VDC = 1.8V (all states, except P_ON,
SLEEP, RESET, and TRX_OFF)
VDC = 0mV (otherwise)
DC level at pin AVDD for various transceiver states.
Supply pin (voltage regulator output) for the analog 1.8V
voltage domain, recommended bypass capacitor 100nF.
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AT86RF232
1.3 Digital Pins
The Atmel AT86RF232 provides a digital microcontroller interface. The interface
comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals
(CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in
detail in Chapter 6.
Additional digital output signals DIG1 and DIG2 are provided to control external blocks,
that is for Antenna Diversity RF switch control, see Section 11.3.
1.3.1 Driver Strength Settings
The driver strength of all digital output pins (MISO, IRQ, DIG1, and DIG2) and CLKM
pin are fixed. The capacitive load should be as small as possible as, not larger than
50pF.
1.3.2 Pull-up and Pull-down Configuration
All digital input pins are internally pulled-up or pulled-down in radio transceiver state
P_ON, see Section 7.1.2.1. Table 1-3 summarizes the pull-up and pull-down
configuration.
Table 1-3. Pull-up / Pull-Down Configuration of Digital Input Pins.
Pins
H

ˆ
pull-up, L

ˆ
pull-down
/RST
H
/SEL
H
SCLK
L
MOSI
L
SLP_TR
L
In all other radio transceiver states, no pull-up or pull-down circuitry is connected to any
of the digital input pins mentioned in Table 1-3. In RESET state, the pull-up or pull-down
resistors are not enabled.
If the additional digital output signals DIG1or DIG2 are not activated, these pins are
pulled-down to digital ground.
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AT86RF232
2 Disclaimer
Typical values contained in this datasheet are based on simulations and testing.
Minimum and maximum values are available when the radio transceiver has been fully
characterized.
3 Overview
The Atmel AT86RF232 is a low-power 2.4GHz radio transceiver designed for consumer
ZigBee/IEEE 802.15.4, RF4CE, 6LoWPAN, and 2.4GHz ISM band applications. The
radio transceiver is a true SPI-to-antenna solution. All RF-critical components except
the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the
AT86RF232 is particularly suitable for applications like:
2.4GHz IEEE 802.15.4 and ZigBee systems
RF4CE systems
6LoWPAN systems
Wireless sensor networks
Residential and commercial automation
Health care
Consumer electronics
PC peripherals
The AT86RF232 can be operated by using an external microcontroller like Atmel AVR®
microcontrollers. A comprehensive software programming description can be found in
reference [6], AT86RF232 Software Programming Model.
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AT86RF232
4 General Circuit Description
This single-chip radio transceiver provides a complete radio transceiver interface
between an antenna and a microcontroller. It comprises the analog radio, digital
modulation and demodulation including time and frequency synchronization and data
buffering. The number of external components is minimized such that only the antenna,
the crystal and decoupling capacitors are required. The bidirectional differential antenna
pins (RFP, RFN) are used for transmission and reception, thus no external antenna
switch is needed.
The Atmel AT86RF232 block diagram is shown in Figure 4-1.
Figure 4-1. AT86RF232 Block Diagram.
AVREG
LNA
PLLPA
PPF BPF ADC
AGC
PA and Power Control Configuration Registers
SPI
(Slave)
RSSI
IRQ
CLKM
/RST
SLP_TR
/SEL
MISO
MOSI
SCLK
RFP
RFN
TX Data
Control Logic
DIG2
Antenna Diversity
FTN, BATMON
XOSC
XTAL1 XTAL2
Analog Domain Digital Domain
AES
DIG1/2
AD
DVREG
RX BBP
Frame
Buffer
TX BBP
Limiter
The received RF signal at pin 5 (RFN) and pin 6 (RFP) is differentially fed through the
low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the
integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the
succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The
ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to [1] and [2]. The modulation signal
is generated in the digital transmitter (TX BBP) and applied to the fractional-N
frequency synthesis (PLL), to ensure the coherent phase modulation required for
demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power
amplifier (PA).
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AT86RF232
Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital
1.8V supply.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be
transmitted or the received data.
The configuration of the Atmel AT86RF232, reading and writing of Frame Buffer is
controlled by the SPI interface and additional control lines.
The AT86RF232 further contains comprehensive hardware-MAC support (Extended
Operating Mode) and a security engine (AES) to improve the overall system power
efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel
to all PHY operational transactions and states using the SPI interface, except during
SLEEP state.
To improve the reliability of an RF connection the RF performance can further be
improved by using Antenna Diversity.
Additional features of the Extended Feature Set, see Chapter 11, are provided to
simplify the interaction between radio transceiver and microcontroller.
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AT86RF232
5 Application Circuits
5.1 Basic Application Schematic
A basic application schematic of the Atmel AT86RF232 with a single-ended RF
connector is shown in Figure 5-1. The 50Ω single-ended RF input is transformed to the
100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide
AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if
required.
Figure 5-1. Basic Application Schematic.
8
7
6
5
4
3
2
1
910 11 12 13 14 15 16
2526
2728
2930
3132
AT86RF232
AVSS
AVSS
AVSS
AVSS
AVSS
RFP
RFN
AVSS
DVSS
DIG1
DIG2 SLP_TR DVSS DVDD DVDD
XTAL2
DEVDD DVSS
AVSS
AVDD
EVDD
AVSS
XTAL1
17
18
19
20
21
22
23
24
DVSS
CLKM
IRQ
MISO
DVSS
MOSI
SCLK
CB3 CB4
Digital Interface
/RST
/SEL
VDD
XTAL
CX1 CX2
CB1
VDD
CB2
C1
C2
B1
RF
C3
R1
C4
The power supply decoupling capacitors (CB2, CB4) are connected to the external
analog supply pin 28 (EVDD) and external digital supply pin 15 (DEVDD). Capacitors
CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage
regulators to ensure stable operation. All decoupling and bypass capacitors should be
placed as close as possible to the pins and should have a low-resistance and low-
inductance connection to ground to achieve the best performance.
The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry
connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best
accuracy and stability of the reference frequency, large parasitic capacitances should
be avoided. Crystal lines should be routed as short as possible and not in proximity of
digital I/O signals.
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