Avnet Fmc-hdmi-cam Operation instructions

23 February 2016

Version 2015_4

are subject to change without notice.

NOTICE OF DISCLAIMER: Avnet is providing this design, code, or information "as is." By providing the design, code, or information as

one possible implementation of this feature, application, or standard, Avnet makes no representation that this implementation is free from

any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Avnet expressly

disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or

representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a

particular purpose.

FMC-HDMI-CAM + PYTHON-1300-C

Frame Buffer Design Tutorial

Overview

This reference design is the getting started design for the PYTHON-1300-C camera

module. The camera module features ON Semiconductor’s PYTHON-1300 color image

sensor. The PYTHON-1300 is a 1/2 inch Super-eXtended Graphics Array (SXGA) CMOS

image sensor with a pixel array of 1280 by 1024 pixels. Designed to address the needs of

general purpose industrial image sensing applications, the new global shutter image

sensor combines flexibility in configuration and resolution with high speed and high

sensitivity for the industrial imaging market.

Figure 1 –PYTHON-1300-C Camera Module

Objectives

This tutorial will guide the user how to:

Retrieve the design files from the public Avnet git repository

Build the reference design

Execute the reference design on hardware

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Reference Design Overview

The example design uses the Zynq processing system (PS) to initialize the PYTHON-1300-

C camera, the HDMI input interface, as well as the HDMI output interface. The design

also implements a simple image sensor pipeline (ISP) and video frame buffer inside the

programmable logic (PL).

The following figure illustrates the block diagram for the programmable logic (PL)

hardware implementation.

Figure 2 –FMC-HDMI-CAM + PYTHON-1300 Camera Reference Design –

Hardware Block Diagram

Valid licenses (hardware evaluation, or full license) are required for the following video

IP cores:

Color Filter Array Interpolation (CFA) v7.0

Chroma Resampler v4.0

Video On Screen Display (OSD) v6.0

RGB to YcrCb Color-Space Converter v7.1

Video Timing Controller (VTC) v6.1

HDMI

Output

AXI4S

Video

VTC

OSD

PYTHON

Receiver

Video

AXI4S

CFA

RGB

YUV

444

422

AXI

VDMA

Video

AXI4S

AXI

VDMA

HDMI

Input

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Experiment Setup

This tutorial makes use of Xilinx Vivado Design Suite in scripting mode in order to create

a project. The resulting project can be opened with the graphical (GUI) version of the

tools for further analysis and modification.

Software

The software required to build, and execute the reference design is:

Windws-7 64-bit

Terminal Emulator (HyperTerminal or TeraTerm)

Xilinx Vivado Design Suite 2015.4

MicroZed Board Definition Install for Vivado 2015.4

ohttp://www.microzed.org/support/documentation/1519

PicoZed Board Definition Install for Vivado 2015.4

Hardware

The hardware required to build, and execute the reference design is:

Win-7 PC with a recommended 2 GB RAM available for the Xilinx tools to

complete a XC7Z020 design

One of the following supported FMC carriers:

oMicroZed 7020 SOM + FMC Carrier Card

oPicoZed 7030 SOM + FMC Carrier Card V2

oPicoZed 7020 SOM + FMC Carrier Card V2

oZedBoard

oZC702

oZC706

ON Semiconductor PYTHON-1300-C Canera Module (optionnal)

DVI or HDMI video source

HDMI (or DVI-D) monitor (1080P60 capable)

USB cable (Type A to Micro-USB Type B)

4GB MicroSD card

Refer to http://www.xilinx.com/design-tools/vivado/memory.htm

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Experiment 1: Licensing the Video and Image

Processing Pack IP Cores

This reference design uses several of the Xilinx Video and Image Processing Pack IP

cores. In order to build the hardware design, valid licenses (hardware evaluation, or full

license) are required for the following video IP cores:

Color Filter Array Interpolation (CFA) v7.0

Chroma Resampler v4.0

Video On Screen Display (OSD) v6.0

RGB to YcrCb Color-Space Converter v7.1

Video Timing Controller (VTC) v6.1

Follow these steps to request an evaluation license:

1. Navigate to the “Video and Image Processing Pack” product page on the Xilinx

web site :

http://www.xilinx.com/products/intellectual-property/ef-di-vid-img-ip-pack.html

2. Click the Evaluate link located on the right of the web page,

and follow the online instructions

Figure 3 –Video and Image Processing Pack –product page

3. The generated license file is sent by email. Follow the enclosed instructions to

add the evaluation license features for the Video and Image Processing Pack.

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Experiment 2: Retrieve the design files

In this section, the design files for the reference design will be retrieved from the Avnet

git repository.

1. Navigate to the following web site : https://github.com/Avnet/hdl

2. Click the branch:master button

3. Specify the following search criteria : fmchc_python

4. Click the Tags tab

Figure 4 –Avnet GitHub repository –Retrieving specific version with tag

5. Select the fmchc_python1300c_PZ7030_FMC2_20160223_221823 tag

This will retrieve a known working version of the design files for the FMC-HDMI-

CAM + PYTHON-1300-C reference design.

fmchc_python1300c_PZ7030_FMC2_

20160223_221823C_20151209_1542

fmchc_python

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6. Click the Download ZIP file button

Figure 5 –Avnet GitHub repository –Download ZIP

7. Create an “Avnet” directory in your root C:\ drive

8. Save hdl-fmchc_python1300c_PZ7030_FMC2_20160223_221823.zip file to the

C:\Avnet directory, and extract the contents of the zip file in this directory

9. Rename the “hdl-fmchc_python1300c_PZ7030_FMC2_20160223_221823”

directory to “hdl”

You should see the following directory structure

Figure 6 –Extracted C:\Avnet\hdl directory structure

NOTE : the exact directory name is not critical, but it must remain short on Windows

machines, due to the directory length limitation of Windows

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The C:\Avnet\hdl repository contains the following sub-directories:

Directory

Content Description

C:\Avnet\hdl\IP\avnet_hdmi_in

C:\Avnet\hdl\IP\avnet_hdmi_out

IP cores (including HDL source)

for the HDMI input/output interfaces

including embedded sync code

insertion/detection

C:\Avnet\hdl\IP\onsemi_vita_spi

IP core (including HDL source)

for the SPI controller for use with the

VITA/PYTHON image sensors

C:\Avnet\hdl\IP\onsemi_vita_cam

IP core (including HDL source)

for the VITA/PYTHON camera receiver

C:\Avnet\hdl\Projects\

fmchc_python1300c

files for FMC-HDMI-CAM + PYTHON-1300-C

reference design

C:\Avnet\hdl\Scripts\

make_fmchc_python1300c.tcl

script to build FMC-HDMI-CAM + PYTHON-

1300-C reference design

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By default, the script will build the design for all the supported carriers. The script will

need to be modified to only build for your FMC carrier. For example, in order to build

for the MicroZed 7020 + FMC Carrier Card.

10. Edit the make_fmchc_python1300c.tcl script to only build for your FMC carrier.

Figure 7 –Editing the make script to build for your FMC Carrier Card