Avnet FMC-HDMI-CAM Operation instructions

23 February 2016
Version 2015_4
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FMC-HDMI-CAM + PYTHON-1300-C
Frame Buffer Design Tutorial
Overview
This reference design is the getting started design for the PYTHON-1300-C camera
module. The camera module features ON Semiconductor’s PYTHON-1300 color image
sensor. The PYTHON-1300 is a 1/2 inch Super-eXtended Graphics Array (SXGA) CMOS
image sensor with a pixel array of 1280 by 1024 pixels. Designed to address the needs of
general purpose industrial image sensing applications, the new global shutter image
sensor combines flexibility in configuration and resolution with high speed and high
sensitivity for the industrial imaging market.
Figure 1 –PYTHON-1300-C Camera Module
Objectives
This tutorial will guide the user how to:
Retrieve the design files from the public Avnet git repository
Build the reference design
Execute the reference design on hardware

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Reference Design Overview
The example design uses the Zynq processing system (PS) to initialize the PYTHON-1300-
C camera, the HDMI input interface, as well as the HDMI output interface. The design
also implements a simple image sensor pipeline (ISP) and video frame buffer inside the
programmable logic (PL).
The following figure illustrates the block diagram for the programmable logic (PL)
hardware implementation.
Figure 2 –FMC-HDMI-CAM + PYTHON-1300 Camera Reference Design –
Hardware Block Diagram
Valid licenses (hardware evaluation, or full license) are required for the following video
IP cores:
Color Filter Array Interpolation (CFA) v7.0
Chroma Resampler v4.0
Video On Screen Display (OSD) v6.0
RGB to YcrCb Color-Space Converter v7.1
Video Timing Controller (VTC) v6.1
HDMI
Output
AXI4S
To
Video
VTC
OSD
PYTHON
Receiver
Video
To
AXI4S
CFA
RGB
To
YUV
444
To
422
AXI
VDMA
Video
To
AXI4S
AXI
VDMA
HDMI
Input

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Frame Buffer Design Tutorial
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Experiment Setup
This tutorial makes use of Xilinx Vivado Design Suite in scripting mode in order to create
a project. The resulting project can be opened with the graphical (GUI) version of the
tools for further analysis and modification.
Software
The software required to build, and execute the reference design is:
Windws-7 64-bit
Terminal Emulator (HyperTerminal or TeraTerm)
Xilinx Vivado Design Suite 2015.4
MicroZed Board Definition Install for Vivado 2015.4
ohttp://www.microzed.org/support/documentation/1519
PicoZed Board Definition Install for Vivado 2015.4
Hardware
The hardware required to build, and execute the reference design is:
Win-7 PC with a recommended 2 GB RAM available for the Xilinx tools to
complete a XC7Z020 design
1
One of the following supported FMC carriers:
oMicroZed 7020 SOM + FMC Carrier Card
oPicoZed 7030 SOM + FMC Carrier Card V2
oPicoZed 7020 SOM + FMC Carrier Card V2
oZedBoard
oZC702
oZC706
ON Semiconductor PYTHON-1300-C Canera Module (optionnal)
DVI or HDMI video source
HDMI (or DVI-D) monitor (1080P60 capable)
USB cable (Type A to Micro-USB Type B)
4GB MicroSD card
1
Refer to http://www.xilinx.com/design-tools/vivado/memory.htm

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Experiment 1: Licensing the Video and Image
Processing Pack IP Cores
This reference design uses several of the Xilinx Video and Image Processing Pack IP
cores. In order to build the hardware design, valid licenses (hardware evaluation, or full
license) are required for the following video IP cores:
Color Filter Array Interpolation (CFA) v7.0
Chroma Resampler v4.0
Video On Screen Display (OSD) v6.0
RGB to YcrCb Color-Space Converter v7.1
Video Timing Controller (VTC) v6.1
Follow these steps to request an evaluation license:
1. Navigate to the “Video and Image Processing Pack” product page on the Xilinx
web site :
http://www.xilinx.com/products/intellectual-property/ef-di-vid-img-ip-pack.html
2. Click the Evaluate link located on the right of the web page,
and follow the online instructions
Figure 3 –Video and Image Processing Pack –product page
3. The generated license file is sent by email. Follow the enclosed instructions to
add the evaluation license features for the Video and Image Processing Pack.

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Experiment 2: Retrieve the design files
In this section, the design files for the reference design will be retrieved from the Avnet
git repository.
1. Navigate to the following web site : https://github.com/Avnet/hdl
2. Click the branch:master button
3. Specify the following search criteria : fmchc_python
4. Click the Tags tab
Figure 4 –Avnet GitHub repository –Retrieving specific version with tag
5. Select the fmchc_python1300c_PZ7030_FMC2_20160223_221823 tag
This will retrieve a known working version of the design files for the FMC-HDMI-
CAM + PYTHON-1300-C reference design.
1
2
fmchc_python1300c_PZ7030_FMC2_
20160223_221823C_20151209_1542
35
fmchc_python
3
4

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6. Click the Download ZIP file button
Figure 5 –Avnet GitHub repository –Download ZIP
7. Create an “Avnet” directory in your root C:\ drive
8. Save hdl-fmchc_python1300c_PZ7030_FMC2_20160223_221823.zip file to the
C:\Avnet directory, and extract the contents of the zip file in this directory
9. Rename the “hdl-fmchc_python1300c_PZ7030_FMC2_20160223_221823”
directory to “hdl”
You should see the following directory structure
Figure 6 –Extracted C:\Avnet\hdl directory structure
NOTE : the exact directory name is not critical, but it must remain short on Windows
machines, due to the directory length limitation of Windows
6

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The C:\Avnet\hdl repository contains the following sub-directories:
Directory
Content Description
C:\Avnet\hdl\Boards
contains board related files
C:\Avnet\hdl\IP
contains the IP cores used by the ref designs
C:\Avnet\hdl\Projects
contains project related files
C:\Avnet\hdl\Scripts
contains scripts used to automatically build the designs
For the PYTHON-1300-C reference design, the following content is of interest:
Directory
Content Description
C:\Avnet\hdl\IP\avnet_hdmi_in
C:\Avnet\hdl\IP\avnet_hdmi_out
IP cores (including HDL source)
for the HDMI input/output interfaces
including embedded sync code
insertion/detection
C:\Avnet\hdl\IP\onsemi_vita_spi
IP core (including HDL source)
for the SPI controller for use with the
VITA/PYTHON image sensors
C:\Avnet\hdl\IP\onsemi_vita_cam
IP core (including HDL source)
for the VITA/PYTHON camera receiver
C:\Avnet\hdl\Projects\
fmchc_python1300c
files for FMC-HDMI-CAM + PYTHON-1300-C
reference design
C:\Avnet\hdl\Scripts\
make_fmchc_python1300c.tcl
script to build FMC-HDMI-CAM + PYTHON-
1300-C reference design

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By default, the script will build the design for all the supported carriers. The script will
need to be modified to only build for your FMC carrier. For example, in order to build
for the MicroZed 7020 + FMC Carrier Card.
10. Edit the make_fmchc_python1300c.tcl script to only build for your FMC carrier.
Figure 7 –Editing the make script to build for your FMC Carrier Card
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the MicroZed-7020 + FMC Carrier Card
set argv [list board=MZ7020_FMCCC project=fmchc_python1300c sdk=yes
version_override=yes]
set argc [llength $argv]
source ./make.tcl -notrace
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the PicoZed-7030 + FMC Carrier Card V2
#set argv [list board=PZ7030_FMC2 project=fmchc_python1300c sdk=yes
version_override=yes]
#set argc [llength $argv]
#source ./make.tcl -notrace
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the PicoZed-7020 + FMC Carrier Card V2
#set argv [list board=PZ7020_FMC2 project=fmchc_python1300c sdk=yes
version_override=yes]
#set argc [llength $argv]
#source ./make.tcl -notrace
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the ZedBoard
#set argv [list board=ZEDBOARD project=fmchc_python1300c sdk=yes
version_override=yes]
#set argc [llength $argv]
#source ./make.tcl -notrace
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the ZC702 board
#set argv [list board=ZC702 project=fmchc_python1300c sdk=yes
version_override=yes]
#set argc [llength $argv]
#source ./make.tcl -notrace
# Build FMC-HDMI-CAM + PYTHON-1300-C Getting Started design
# for the ZC706 board
#set argv [list board=ZC706 project=fmchc_python1300c sdk=yes
version_override=yes]
#set argc [llength $argv]
#source ./make.tcl -notrace

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Experiment 3: Build the reference design
In this section, the Vivado project will be created and built with TCL scripts,
implementing the FMC-HDMI-CAM + PYTHON-1300-C reference design for the selected
FMC carrier.
1. From the Start menu, open the “Vivado 2015.4 TCL Shell” console
2. Change to the C:\Avnet\hdl\Scripts directory
Figure 8 –Vivado 2015.4 TCL Shell –Changing to C:/Avnet/hdl/Scripts directory
3. Launch the build with the “source ./make_fmchc_python1300c.tcl” command
Figure 9 –Vivado 2015.4 TCL Shell –Launching the build
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
Vivado% cd C:/Avnet/hdl/Scripts
Vivado%
Vivado% source ./make_fmchc_python1300c.tcl
# set argv [list board=MZ7020_FMCCC project=fmchc_python1300c sdk=yes
version_override=yes]
# set argc [llength $argv]
# source ./make.tcl -notrace
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*- -*
*- Welcome to the Avnet Project Builder -*
*- -*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
+------------------+------------------------------------+
| Setting | Configuration |
+------------------+------------------------------------+
| Board | MZ7020_FMCCC |
+------------------+------------------------------------+
| Project | fmchc_python1300c |
+------------------+------------------------------------+
| SDK | yes |
+------------------+------------------------------------+
| Version override | yes |
+------------------+------------------------------------+

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As a convenience, before building the hardware design, the scripts will verify if valid
licenses are installed for the video IP cores used in the design.
Figure 10 –Vivado 2015.4 TCL Shell –Video IP Core license verification
Each of the video IP cores requires a full license or hardware evaluation license in order
to successfully build a bitstream.
The build will perform the following steps, where {BOARD} will be one of
MZ7020_FMCCC , PZ7030_FMC2, ZEDBOARD, ZC702, or ZC706:
Create and build the hardware design with Vivado 2015.4,
including the IP Integrator block design
C:\Avnet\hdl\Projects\fmchc_python1300c\{BOARD}\fmchc_ python1300c.xpr
Create and build the SDK workspace, including board support package (BSP),
software application, and first stage boot loader (FSBL)
C:\Avnet\hdl\Projects\fmchc_python1300c\{BOARD}\fmchc_ python1300c.sdk
Create the SD card image (BOOT.bin)
C:\Avnet\hdl\Projects\fmchc_python1300c\{BOARD}\BOOT.bin
***** Check for Video IP core licenses...
+------------------+------------------------------------+
| Video IP Core | License Status |
+------------------+------------------------------------+
| v_cfa | VALID (Hardware Evaluation) |
+------------------+------------------------------------+
| v_cresample | VALID (Hardware Evaluation) |
+------------------+------------------------------------+
| v_osd | VALID (Hardware Evaluation) |
+------------------+------------------------------------+
| v_rgb2ycrcb | VALID (Full License) |
+------------------+------------------------------------+
| v_tc | VALID (Full License) |
+------------------+------------------------------------+