BBK DW9951S User manual

SERVICE MANUAL
DW9951S
R
Ver 0.0

INDEX
BLOCK DIAGRAM ...................................................................................................................
BLOCK DIAGRAM
PREFACE
FEATURES
FRONT PANEL&REAR PANEL
REMOTE CONTROL ........................................................................................................................
...................................................................................................................................
..................................................................................................
SCHEMATIC DIAGRAM&PCB SILKSCREEN
MAIN BOARD SCHEMATIC AND PCB LAYOUT 25-39
AV BOARD SCHEMATIC AND PCB LAYOUT 40-51
52-56
KEY BOARD SCHEMATIC AND PCB LAYOUT
POWER BOARD SCHEMATIC AND PCB LAYOUT ...........................................................
...............................................................
.................................................................
...............................................................
57-59
PARTS SPECIFICATIONS
SST39VF3201 ..................................................................................................................................
HY5DU561622CT .............................................................................................................................
TSB41AB1
..........................................................................................................
TVP5146
...........................................................................................................................
CS4360 ...................................................................................................................
CS5333 .............................................................................................................................................
74HC/HCT14 ..................................................................................................................................
74ALVT16373...........................................................................................................................
MM1221~MM1228 .................................................................................................................................
LP2995 .......................................................................................................................
PQXXXEZ02Z ..................................................................................................................................
MSP 34x5G ................................................................................................................
TUNER ...................................................................................................................
PARTSLIST
MAIN BOARD..................................................................................................................................
.......................................................................................................................................
.........................................................................................................................
..............................................................................................................
60-62
MAIN KEY BOARD ......................................................................................................................................
63
POWER BOARD ................................................................................................................ 64-65
AV BOARD ............................................................................................................................................ 66-67
POWER SWITCH BOARD 68
DV BOARD 69
..............................................................................................................................
EXPLODED VIEW
EXPLODED VIEW
BLOCK DIAGRAM
6
7
8
9-12
13-14
15-16
17
18
19-20
21
22
23
24
1
2
3
5
4
BLOCK DIAGRAM
FRONT AV BOARD 70

1

2

3

BLOCK DIAGRAM
4

5
EXPLODED VIEW

© 1998 Silicon Storage Technology, Inc.329-09 11/98
6
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48-Pin Standard TSOP

HY5DU561622CT
HY5DU28822ET
HY5DU281622ET
Rev. 0.4 /Aug. 2004
PIN CONFIGURATION(TSOP)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x16 x8 x4x4 x8 x16
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
ROW AND COLUMN ADDRESS TABLE
ITEMS 32Mx4 16Mx8 8Mx16
Organization 8M x 4 x 4banks 4M x 8 x 4banks 2M x 16 x 4banks
Row Address A0 - A11 A0 - A11 A0 - A11
Column Address A0-A9, A11 A0-A9 A0-A8
Bank Address BA0, BA1 BA0, BA1 BA0, BA1
Auto Precharge Flag A10 A10 A10
Refresh 4K 4K 4K
7


   

SLLS423D –JUNE 2000 –REVISED SEPTEMBER 2002
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
description (continued)
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to notify
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high
when the TSB41AB1 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON
to be active.
PHP package terminal diagram
14 15
AGND
AVDD
R1
R0
AGND
TPBIAS
TPA+
TPA–
TPB+
TPB–
AGND
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
SYSCLK
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
17 18 19 20
47 46 45 44 4348 42 40 39 3841
21 22 23 24
37
13
PHP PACKAGE
(TOP VIEW)
TSB41AB1
PLLGND PLLV FILTER1 FILTER0 LREQ DGND DGND DV
TESTM
SE
SM
C/LKON
PC1 PC2
ISO
CPS
DV
RESET XO XI
DGND
LPS
PC0 DD
DVDD
DD
DD
8