4 BRUKER BIOSPIN Technical Manual Version 001
Contents
Features .................................................................................. 19
5.3 LVDS Data Structure ........................................................................ 19
5.4 Software Interface ............................................................................ 21
PCI Bus Interface ......................................................................... 21
PCI Software Interface .................................................................. 22
Local Bus Interface .................................................................. 24
Local Bus Configuration Registers ................................................ 24
................................................................................................ 24
Local Bus Address Map ................................................................ 26
Flash Prom at the Local Bus ......................................................... 26
Registers at the Local Bus ............................................................ 27
Pipeline Register ..................................................................... 28
DSP Reset ............................................................................... 29
Local Address Layout ................................................................... 29
Local Bus Chip Select Usage ................................................... 29
The DSP 6713 .............................................................................. 29
DSP Boot Mode and Configuration ........................................... 29
DSP Defined Address Ranges ................................................. 30
The DSP External Memory Interface (EMIF) ............................. 32
The DSP PLL Register ............................................................. 33
Configuration of Interrupts ............................................................ 35
Interrupts from Logic or DSP to Host ........................................ 35
Configuration of the External Memory Interface (EMIF) ............ 36
Content of EMIF Register and Resulting Memory Allocation ..... 36
Description of the Global Control Register ............................... 37
Description of the Global Control Register ............................... 38
DSP Address Map ........................................................................ 41
................................................................................................ 41
Registers at the EMIF Bus ............................................................ 41
5.5 Functionality of Devices ................................................................... 44
Digital Preemphasis ................................................................. 44
DPP Pipeline ................................................................................ 44
Detailed Procedure .................................................................. 44
Functional Coordination between the Hardware and Software .. 45
Serial Gradient Cycle, Serial Processing by the DSP ................ 46
Description .............................................................................. 47
Description ............................................................................. 48
5.6 Engineering Design .......................................................................... 49
Dimensions .............................................................................. 49
JTAG Structure ........................................................................ 49
Figures ............................................................................. 51
Tables ............................................................................... 53
