Bruker DPP1 User manual
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Bruker BioSpin
Digital Preemphasis Processor
001
NMR Spectroscopy
DPP1
Technical Manual
This manual was written by
Bernd Jennissen
© October 7, 2008: Bruker Biospin GmbH
Rheinstetten, Germany
P/N: Z31844
DWG-Nr.: Z4D10609 - 001
For further technical assistance on the Digital Preemphasis
Processor unit, please do not hesitate to contact your nearest
BRUKER dealer or contact us directly at:
BRUKER BioSpin GMBH
am Silberstreifen
D-76287 Rheinstetten
Germany
Phone: + 49 721 5161 0
FAX: + 49 721 5171 01
E-mail: service@bruker.de
Internet: www.bruker.com
Copyright © by Bruker BioSpin NMR GmbH
All rights reserved. No part of this publication
may be reproduced, stored in a retrieval
system, or transmitted, in any form, or by any
means without the prior consent of the
publisher. Product names used are
trademarks or registered trademarks of their
respective holders.
Technical Manual Version 001 BRUKER BIOSPIN 3
Contents
Contents ............................................................................ 3
1 Introduction ........................................................................ 5
1.1 Scope of this Manual .......................................................................... 5
1.2 Disclaimer .......................................................................................... 6
1.3 Safety Issues ...................................................................................... 6
Special Safety Symbols ...................................................................7
1.4 Intended Use ...................................................................................... 7
1.5 Contact for Technical Assistance ........................................................ 7
2 Installation and Handling ................................................... 9
2.1 Product Requirements and Handling ................................................... 9
PCI Requirements ..........................................................................9
2.2 Handling ............................................................................................ 9
2.3 Mounting the DPP1 PCI Board .......................................................... 10
2.4 Booting the DPP1 ............................................................................. 10
2.5 Ports ................................................................................................ 11
Connectors ...................................................................................12
Currents and Voltages ..................................................................12
3 Reference Numbers .......................................................... 13
4 Product Status and Modifications ................................... 15
4.1 Introductory Status ........................................................................... 15
Program File ............................................................................15
4.2 Configuration and Settings ................................................................ 15
Jumper Setting .........................................................................15
PCI Bus ....................................................................................15
LVDS Configuration ..................................................................16
Firmware ..................................................................................16
4.3 Modification History .......................................................................... 16
5 Description ....................................................................... 17
5.1 Versions ........................................................................................... 17
5.2 Structure .......................................................................................... 17
The PCI Interface ..........................................................................18
Bus Structure ...........................................................................18
DSP .........................................................................................18
LVDS .......................................................................................19
FIFO’s ......................................................................................19
Memory ....................................................................................19
Operation .................................................................................19
4 BRUKER BIOSPIN Technical Manual Version 001
Contents
Features .................................................................................. 19
5.3 LVDS Data Structure ........................................................................ 19
5.4 Software Interface ............................................................................ 21
PCI Bus Interface ......................................................................... 21
PCI Software Interface .................................................................. 22
Local Bus Interface .................................................................. 24
Local Bus Configuration Registers ................................................ 24
................................................................................................ 24
Local Bus Address Map ................................................................ 26
Flash Prom at the Local Bus ......................................................... 26
Registers at the Local Bus ............................................................ 27
Pipeline Register ..................................................................... 28
DSP Reset ............................................................................... 29
Local Address Layout ................................................................... 29
Local Bus Chip Select Usage ................................................... 29
The DSP 6713 .............................................................................. 29
DSP Boot Mode and Configuration ........................................... 29
DSP Defined Address Ranges ................................................. 30
The DSP External Memory Interface (EMIF) ............................. 32
The DSP PLL Register ............................................................. 33
Configuration of Interrupts ............................................................ 35
Interrupts from Logic or DSP to Host ........................................ 35
Configuration of the External Memory Interface (EMIF) ............ 36
Content of EMIF Register and Resulting Memory Allocation ..... 36
Description of the Global Control Register ............................... 37
Description of the Global Control Register ............................... 38
DSP Address Map ........................................................................ 41
................................................................................................ 41
Registers at the EMIF Bus ............................................................ 41
5.5 Functionality of Devices ................................................................... 44
Digital Preemphasis ................................................................. 44
DPP Pipeline ................................................................................ 44
Detailed Procedure .................................................................. 44
Functional Coordination between the Hardware and Software .. 45
Serial Gradient Cycle, Serial Processing by the DSP ................ 46
Description .............................................................................. 47
Description ............................................................................. 48
5.6 Engineering Design .......................................................................... 49
Dimensions .............................................................................. 49
JTAG Structure ........................................................................ 49
Figures ............................................................................. 51
Tables ............................................................................... 53
Technical Manual Version 001 BRUKER BIOSPIN 5 (55)
1
Introduction 1
Scope of this Manual 1.1
The DPP1 (Digital Pre-emphasis Board 1) is a Customer Replaceable Unit (CRU)
used with Bruker AQS/3 type spectrometers with IPSO. This manual is intended
for trained service and technical personnel and includes instructions on the instal-
lation and handling of the DPP1, as well as other detailed technical specifications
and information.
The DPP1, is a standard PCI expansion card. It modifies the data stream sent by
the gradient controller (G–Controller) to the gradient amplifier. The DPP1 is super-
vised by a software driver running under LINUX and has to be mounted in an PCI
environment (see "Installation and Handling" on page 9).
Figure 1.1. Top View of the DPP1
1. Input from the Gradient Controller
2. Output to the Gradient Amplifier
3. Next Value Clock Input
4. Reset Button
1
2
3 4 5 6
7
5. DSP Emulation Switch
6. DSP JTAG Connector
7. JTAG Programming/Test Connector
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Introduction
Disclaimer 1.2
The DPP1 should only be used for its intended purpose as described in this man-
ual. Use of the DPP1 for any purpose other than that for which it is intended is tak-
en only at the users own risk and invalidates any and all manufacturer warranties.
Read this manual and pay particular attention to any safety related information
before working with the DPP1.
Safety Issues 1.3
These instructions refer to all IPSO models.
The IPSO may be damaged by inappropriate usage. The damage could be such,
that the equipment must not be used before having been checked by a service
representative.
The user should recheck the equipment at regular intervals for any damage or
wear and is expected to inform the service representative immediately of any ab-
normality.
In the unlikely case of one of the following, stop using the equipment, disconnect
the power supply, report the circumstance to the service staff and ask for instruc-
tions:
•The power cord, power plug or power supply are cracked, brittle or damaged.
•Signs of excessive heat are apparent.
•There is evidence or suspicion that a liquid has intruded into any enclosure.
•The power cord or the power supply have been in contact with any liquid.
•The IPSO has been dropped or damaged in any way.
•The equipment does not work correctly.
WARNING!
If you are in doubt about the correct state of any component, do not
use the equipment and inform the service staff.
WARNING!
Do not try to service the equipment by yourself, unless you are spe-
cifically asked to do so and are given instructions by the service
staff. In case of questions or problems, please contact your nearest
Bruker office or representative.
Intended Use
Technical Manual Version 001 BRUKER BIOSPIN 7 (55)
Special Safety Symbols 1.3.1
These symbols are used on the equipment and/or throughout this manual. They
alert to danger and important information:
There are various information notices used in this manual. These notices highlight
important information or warn the user of a potentially dangerous situation.
Intended Use 1.4
The DPP1 is to be used only in a PCI environment and with Bruker AVANCE III
spectrometers for the modification of data streams sent by the gradient controller.
The board is not intended for use outside of these standard parameters.
Contact for Technical Assistance 1.5
For further technical assistance on the DPP1, please do not hesitate to contact
your nearest BRUKER dealer or contact us directly at:
BRUKER BioSpin GMBH
am Silberstreifen
D-76287 Rheinstetten
Germany
Phone: + 49 721 5161 0
FAX: + 49 721 5171 01
E-mail: service@bruker.de
Internet: www.bruker.com
WARNING!
This symbol denotes hints or instructions throughout this manual
whose non-compliance could lead to erroneous or incalculable
behavior of the system.
WARNING!
The symbol indicates a potential risk of injury due to contact with
high voltage.
Technical Manual Version 001 BRUKER BIOSPIN 9 (55)
2
Installation and
Handling 2
Product Requirements and Handling 2.1
The DPP1 Digital Preemphasis Board is a Customer Replaceable Unit (CRU). To
insert or remove the DPP1 follow the instructions in this manual.
Replacing CRU‘s requires opening of the enclosure. Before doing this, the unit
must be completely switched off and unplugged or disconnected and dismounted
from its rack.
PCI Requirements 2.1.1
Handling 2.2
Type of PCI Bus: 32 bit/ 33 MHz
Length of the card: Short, 176mm
PCI functions: Single
Number of interrupts: One at interrupt A, pin A6
PCI signal voltage: The DPP1 can be used in 3.3 V or 5 V buses.
Signals received have to be between 3.3 V to 5 V (5 V tolerance).
The level of signals sent depends on the voltage at the “VI/O” pins
A16, B19, A59 and B59 of the PCI slot used.
Handling under ESD safety conditions is necessary. Do not touch uncov-
ered PCB or connector metal without first discharging yourself!
Do not connect a receiver to the LVDS connector of the controller in slot 2
of the IPSO 19” Unit. The data will never be valid in this location.
A LVDS cable should never be removed from or connected to a powered
controller. Corrupted data could be sampled as valid.
Do not connect more than one gradient amplifier to the same system.
10 (55) BRUKER BIOSPIN Technical Manual Version 001
Installation and Handling
Mounting the DPP1 PCI Board 2.3
The DPP1 board is intended to be mounted in a PCI environment. The driver is LI-
NUX specific and will only work in an AVANCE III IPSO system.
DSP firmware is loaded from the TopSpin PC via the PCI bus and Ethernet.
All gradient values are transferred over two 48–bit LVDS interfaces.
The Next–Value (NV) clock signal is attached using a coax cable on the IPSO 19
inch case, or using a PCI connector pin on the IPSO AQS.
Figure 2.1. IPSO Functional Signal Flow
Booting the DPP1 2.4
The boot process starts after turning on the IPSO. The configuration is carried out
beginning with post code “49” and LINUX begins to boot if the post code exceeds
“60”.
Recognition of the DPP1 during booting can be verified using the Web server on
the IPSO or by using a browser on the TopSpin PC. The IPSO IP address, which
is needed by the browser, can be located: in TopSpin, in the Hyper Terminal or in
a shell on the workstation.
In TopSpin:
Type “ha” at the command line to display a dialog for all devices. Click on
IPSO to open a browser with the IPSO’s IP address.
Installation and Handling
Technical Manual Version 001 BRUKER BIOSPIN 11 (55)
With Hyper Terminal:
Type “ifconfig” at the IPSO prompt to display the IP address:
root@ipso:ifconfig
Enter this IP address in a standard browser‘s URL field.
In a Shell:
Start a broadcast using “ping” and the parameters below will display the IP
addresses of all the connected IPSO devices:
ping –w1 –b 149.236.99.255
Enter this IP address in the URL field of a standard browser.
Proceeding in the browser:
When you have entered the IP address in the browser the browser will display the
“IPSO Service Web” page. Click consecutively on the following to show a list of all
the controllers found as PCI devices. One of them will be the DPP1:
! Information ! View Hardware List
Ports 2.5
Figure 2.2. Ports on the Front Panel of the DPP1
1. 48-Bit LVDS Connector (26 pin) - OUTPUT to the Gradient Amplifier
2. 48-Bit LVDS Connector (26 pin) - INPUT from the Gradient Controller
2
1
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Installation and Handling
Connectors 2.5.1
Data Output to Gradient Amplifier
•Low voltage, low noise LVDS output via 8 balanced data lines and one clock
line.
•A transfer rate of 80 mega-words per second.
•A word width of 48 bits.
Data Input from Gradient Controller
•Low voltage, low noise LVDS input via 8 balanced data lines and one clock
line.
•A transfer rate of 80 mega-words per second.
•A word width of 48 bits.
“Next Value” Clock from IPSO
When installed in the “IPSO 19” the DPP1 takes the “Next Value” clock via its ST1
connector connected to ST32 of the IPSO (IMB) using the cable H5516. In the
“IPSO AQS” the DPP gets this clock signal via pin B14 of the PCI connector.
Currents and Voltages 2.5.2
IPSO 19“ IPSO AQS and Others
Source of the „Next Value“ Clock ST1/H5516/St32 PCI B14
Part Number +5 V + 3.3 V +12 V +5 VSB -12 V
H12513F1 00.5 A 000
Technical Manual Version 001 BRUKER BIOSPIN 13 (55)
3
Reference
Numbers 3
Table 3.1. Parts and Assemblies for the DPP1, H12513F1
Part Number Drawing Number Description Version
H12551F2 H4P2820b PCB Layout DPP1, ECL 01
H12551F3 H4P2820c PCB Layout DPP1, ECL 02/03/04
H12536 DPP1 Programming File
HZ13694 DPP Slot Bracket
Table 3.2. Accessories
Part Number Drawing Number Description
86868 48 Bit LVDS Cable, 1 meter
H5516 Coax Cable, 50 Ohm, SMB/SMB, 135 mm
Technical Manual Version 001 BRUKER BIOSPIN 15 (55)
4
Product Status and
Modifications 4
Introductory Status 4.1
Program File
The name of the program file includes the layout number and the EC level.
Configuration and Settings 4.2
Jumper Setting
There are no jumpers on this board. Some configuration settings have been made
using zero Ohm resistors and should not be changed.
PCI Bus
The following four resistors define the interrupt wiring.
Part
Number Name Layout
Number Modification Program
File Firmware Jumper
Setting
H12513F1 DPP1 H4P2820b Yes No No
Table 4.1. PCI Interrupt Selection
Signal Mounted Resistor Comment
INT_A Yes R99 Interrupt to PCI on pin „A“
INT_B No R100 Not connected.
INT_C No RB30 Not connected.
INT_D No RB29 Not connected.
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Product Status and Modifications
LVDS Configuration
Firmware
The firmware is loaded via PCI and Ethernet from the TopSpin PC as part of Top-
Spin. The DPP1 driver is a part of the “diskless” LINUX.
Modification History 4.3
Table 4.2. LVDS Identification Lines H12513F1 48 Bit Interface
Signal LVDS
Input
LVDS
Output
Resistor
Location Comment
CHANNEL_DETECT_1 20 Not used RB48 CHANNEL_DETECT = 00 G_CNTRL
recognize connection to DPP
CHANNEL_DETECT_0 7Not used RB52
USB pwr 19 19
These signals are connected between
the input and output LVDS connector.
USB gnd 8 8
USB + 1 1
USB - 14 14
Table 4.3. DPP1, H12513F1 Modification History
EC
Number Date Layout
Number Description Serial
Number EC Level
3461 21.9.06 H4P2820B Introduction of the DPP1 for IPSO with
48 bit LVDS and external generation
of NV clock.
0032 not
shipped
00
3462 21.9.06 Removed the selection of NV clock
input by a placement of a resistor. Due
to a new termination, both inputs
(coax connector for 19“ and PCI pin
for AQS) are ready to operate.
< 0041
not
shipped
01
3463 21.9.06 H4P2820C Removed the modifications from lay-
out H4P2820B.
0100 02
3623 28.04.08 Corrected echo position jittering dur-
ing imaging echo experiments.
0251 03
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Description
The PCI Interface 5.2.1
The PCI interface for the DPP1 is implemented using the PCI controller PCI9030
from PLX Technologies. The controller translates external PCI access to internal
local bus access and vice versa. The local bus of the controller is connected to the
mailbox register and the host port of the DSP.
Bus Structure
The DPP1 has two independent bus systems:
•The local bus
•The DSP External Memory Interface (EMIF) bus
Each of these buses has its own address range. Exchanging data between the
two busses is only possible via the DSP host port.
The DSP memory bus is attached to an external memory, as well as the LVDS in-
put and output FIFO. The additional status register attached offers the possibility
for the DSP to exchange data directly with the PCI bus.
The DPP1 control logic registers are also connected to the DSP memory bus.
Local Bus
The local bus connects the DSP host port and the mailbox register to the PCI con-
troller. The PCI controller performs the address mapping between the PCI and the
local bus and provides the PCI bus port and the local bus port.
The PCI controller local bus has a bus width of 32 bit. The four memory regions
are distributed into the following parts:
•Space 0 is reserved for the Host Port Interface of the DSP.
•Space 1 is reserved for logic registers.
•Space 2 resets the DSP.
•Space 3 is reserved for the FLASH memory.
EMIF Bus
The DSP controls access from its host interface via the EMIF bus. The DSP mem-
ory (EMIF) bus is attached to an external memory, the DPP1 control logic, and the
LVDS input and output FIFO’s. The additional mailbox register attached offers the
possibility of the DSP exchanging data directly with the PCI bus.
•Space 0 is reserved for the external memory of the DSP.
•Space 1 is reserved for the control logic and the pipeline register.
•Space 2 is reserved for the LVDS input FIFO
•Space 3 is reserved for the LVDS output FIFO.
DSP
The DSP TMS320C6713B is a high performance floating point processor. When
operating at 300 MHz the C6713B delivers up to 1800 MFLOPS.
Description
Technical Manual Version 001 BRUKER BIOSPIN 19 (55)
LVDS
The data from the GCNTR to the DPP1 and from the DPP1 to the gradient ampli-
fier is transmitted via two serial LVDS links. The word width transmitted is 48 bit
and the word transfer speed is 80 MHz.
FIFO’s
Each LVDS connection is connected to an input and output FIFO. The organiza-
tion of the synchronous FIFO is 8192 x 36 bit.
Memory
The external synchronous SRAM on the EMIF bus of the DSP is 128 KB x 36 bit.
Operation
The Digital Preemphasis Processor (DPP) transmits new gradient data in a pre-
defined time pattern to the gradient amplifier. In each time slot the software tests if
a new data package is transferred from the GCU. The DSP reads the new data
and uses it for the next calculation. If no new data set is available the output data
to the gradient amplifier is calculated with a function of the old output data.
Features
•Floating point DSP TMS320C6713 with internal:
- Level 1 program cache (L1P) 4 KB.
- Level 1 data cache (L1D) 4 KB.
- Level 2 memory cache consists of 256 KB memory space that is shared
between data and memory space.
•128 KB x 36 bit expansion SRAM.
•PCI SMART Target I/O controller PCI9030, 5 V I/O tolerant.
•48 bit LVDS interface 80 MHz.
•Input/Output FIFO 8 KB x 36 bit.
•“Next Value” clock cycle is software programmable from 100 ns up to 1,023
sec.
LVDS Data Structure 5.3
The structure of the 48 bit word is identical at the receiver and transmitter.
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Description
The LVDS interface always sends a default word (Last word; NG=1; !Valid=1)
even if no gradient or NEXT gradient words transfers. With the default word, the
load bits, Valid and NG bit are inactively set to =1.
Table 5.1: Word on the LVDS 48 bit 80 MHz Parallel Interface
Bit 4
8
4
7
... 4
4
4
3
... 3
8
3
7
... 2
2
2
1
... 1
8
1
7
... 6 5 4 3 2 1
Field P
A
R
MSB Address MSB Data Data
(res)
(res) !LA
ST
!
V
A
L
I
D
!I
N
G
ADD<9..6> ADD<5..0> ADD<19..0> gnd gnd
Number 1 4 6 16 412 1 1 1 1 1
Con-
nected to
DSP
Data Bus
or Logic
DSP Data Bus Bit: not connected DSP
Bit
Logic
3
1
29..20 19..0 30
Table 5.2: Bit Fields of the DPP Input and Output Word
Field Value Description
!NG Next gradient bit; high active in FIFO; low active on the LVDS interface.
0Leads only to the Next gradient, the word does not contain data,
!Valid=0 in the same 48 bit word was an error.
1!Valid=0 and Out=1 means a gradient value is transferred without the
Next gradient.
!VALID Gradient data valid bit; high active in FIFO; low active on the LVDS
interface.
0The word contains only data and no „Next Gradient“. !NG=0 in the
same word was an error.
1There is no gradient data in this word.
PAR Parity bit, even parity, bit sum over the bits 1 to 47 (DPP only). The
DPP1 is software controlled.
!LAST 0The last word in the gradient package is marked with !NG=0 or
!VALID=0; high active in FIFO; low active on the LVDS interface.
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