BVM BVME4000 User manual

MC68040/68060 SINGLE BOARD
COMPUTER
BVME4000/6000
User's Manual
Manual P/N 454-44000 BVM Limited,
Hobb Lane,
Hedge End,
Southampton,
SO30 0GH, UK.
TEL: [phone]
FAX: [phone]
E-MAIL: [e-mail]
WEB: http://www.bvmltd.co.uk
Board Revision F
Manual Revision I 21 February 2001
This material contains information of proprietary interest to BVM Ltd. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person
except to meet the purposes for which it was delivered.

This page is intentionally left blank.

i
DISCLAIMER
The information in this document has been checked and
is believed to be entirely reliable, however no
responsibility is assumed for inaccuracies. BVM Ltd.
reserves the right to make changes and/or improvements
in both the product and the product documentation without
notice. BVM Ltd. does not assume any liability arising out
of the application or use of any product described herein;
neither does it convey any licence under its patent rights
or the rights of others.
USE OF PRODUCT
This product has been designed to operate in a VMEbus
and IndustryPackcompatible electrical environment.
Insertion of the board into any slot which is not VMEbus
compatible is likely to cause serious damage. Insertion
and removal of the board from the backplane or
IndustryPack(s)or cable(s) from the board must not be
done whilst in a powered condition.
Do not lever out any devices from the product, which uses
surface-mounted devices extensively, as these can be
fractured by excessive force.
This product uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are
observed when handling the product and associated
devices.
RF. INTERFERENCE
This product complies with European Council Directive
89/336/EEC (EMC directive), and conforms to
EN55022:1995 Class B (Limits and methods of
measurement of radio interference characteristics of
information technology equipment) and EN50082-1:1992
(Electromagnetic compatibility - Generic immunity
standard, Part 1: residential, commercial and light
industry) when used in accordance with the BVM EMC
Guidelines Manual part number 454-77000 (available on
request from BVM Ltd.).
GENERAL NOTICES
UNPACKING AND INSPECTION
This product contains components which are susceptible
to static discharge, and should be handled with
appropriate caution.
Upon receipt of this product, visually inspect the board for
missing, broken or damaged components and for physical
damage to the printed circuit board or connectors. This
product was shipped in perfect physical condition. Any
physical damage to the product is the responsibility of the
shipping carrier and should be reported to the carrier's
agent immediately.
RETURN OF GOODS
Before returning a product for repair, verify as well as
possible that the suspected unit is at fault. Then call BVM
Ltd. for a Customer Return (CR) number. Carefully
package the unit, in the original shipping carton if this is
available, and ship prepaid and insured, preferably by
courier, with the CR number written on the outside of the
package.
Include a return address and the telephone number of a
technical contact, and a detailed description of the
observed fault. For out-of-warranty repairs, a purchase
order for repair charges must accompany the return. BVM
Ltd. will not be responsible for damage due to improper
packaging of returned items. Out of warranty repairs can
be arranged, and will be charged on a material and labour
basis, subject to a minimum repair charge. Return
transportation and insurance will be charged as part of the
repair and is in addition to the minimum charge.
SOFTWARE LICENCE NOTICE
Any software that is provided as Copyright BVM Ltd. is
proprietary and confidential property of BVM Ltd., and
each single copy is given on the agreed understanding
that it is licensed for use on product combinations
supplied by BVM Ltd. or their appointed distributors only.
The software product may not be copied (except for
backup purposes), given away, rented, loaned,
reproduced, distributed or transmitted in any way or form,
in whole or in part, without written permission of BVM Ltd.
This applies to any merged, modified or derivative version
of the software including, but not limited to, versions
produced by customising, translating, reverse
engineering, decompiling or disassembly.
This licence may be automatically terminated without
notice if any of its provisions are breached. Reasonable
legal costs may be awarded to the prevailing party in
connection with this licence agreement. Use of, or
accepted delivery of these products shall constitute your
acceptance of the provisions of this licence agreement.
WARRANTY
A) BVM Ltd. warrants that the articles furnished hereunder
are free from defects in material and workmanship for one
year after the date of shipment.
B) All warranties and conditions, express and implied,
statutory and otherwise, as to the quality of the goods or
their fitness for any purpose are hereby excluded and with
the exception of liability for death or personal injury
caused by negligence as defined in the Unfair Contract
Terms Act 1977 the seller shall not be liable for any loss,
injury or damage arising directly or indirectly from the use,
application or storage of such goods.
C) Subclause (B) above shall not apply where the buyer
deals as a consumer as this expression is defined in the
Unfair Contract Terms Act 1977.
D) The liability of BVM Ltd. hereunder shall be limited to
repair or replacement at the manufacturers discretion of
any defective unit. Equipment or parts which have been
subject to abuse, misuse, accident, alteration, neglect,
unauthorised repair or installation are not covered by this
warranty. BVM Ltd. shall have the right of determination
as to the existence and cause of any defect.
E) The warranty period of the replacement or a repaired
product or part shall terminate with the termination of the
warranty period with respect to the original product or part
for all replacement parts supplied or repairs made during
the warranty period.
F) Although BVM Ltd. offer a high level of technical
support and advice, due to the complex nature and wide
application of product configurations it is the responsibility
of the purchaser to be satisfied at the time of purchase
that the products are suitable for the final application.
G) The term 'Software' used herein is defined as 'any
program data or code in source or binary format recorded
in or on any readable device or media'.
H) BVM Ltd. will effect all reasonable effort to resolve
accepted reproducible software errors reported within 12
months of purchase. Acceptance of an error shall solely
be based on conformance to supporting specifications.
Proper operation of earlier releases is not guaranteed.
NOTICES
Copyright 1993,1995,1998,2001 by BVM Ltd.
OS-9 is a registered trademark of Microware Systems
Corporation.
VxWorks is a registered trademark of Wind River Systems
Inc.
IndustryPack is a registered trademark of Greenspring
Computers.

ii
WARNINGS
Do not lever out the EPROM's from the BVME4000/6000. The board
uses surface-mounted devices extensively, which can be fractured by
excessive force. Use proper EPROM extraction and insertion tools.
Damage may result if users attempt to remove or fit EPROM's
incorrectly.
Do not lever out the IP's from the BVME4000/6000. The board uses
surface-mounted devices extensively, which can be fractured by
excessive force. Damage may result if users attempt to remove or fit
IP's incorrectly.
Do not lever out memory modules from the BVME4000/6000. The
board uses surface-mounted devices extensively, which can be
fractured by excessive force. Memory modules are not a field-fit option.
Damage may result if users attempt to remove or fit memory
modules incorrectly.
Do not fit/remove the 68040/68060 device to/from the
BVME4000/6000. Special tools are required to fit and remove these
devices and the correct voltage settings must be selected. Return the
board to the factory if the 68040/68060 device requires changing.
Damage may result if users attempt to fit or remove the
68040/68060 device.
The BVME4000/6000 uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are observed when
handling the BVME4000/6000, EPROM's, IP's and memory modules.
Ensure the correct polarity of connections to the BVME4000/6000.
In particular ensure the correct polarity of connections to the P2 I/O
connector, incorporating the SCSI connections. Damage may result if
users fail to observe correct connection polarity to the
BVME4000/6000.

iii
Table Of Contents
Contents Page
1. Introduction.......................................................................................................................................1
1.1 Scope.........................................................................................................................................1
1.2 BVME4000 Part Numbers..........................................................................................................1
1.3 BVME6000 Part Numbers..........................................................................................................1
1.4 Memory Module Part Numbers..................................................................................................1
2. Overview...........................................................................................................................................2
2.1 Board Layout..............................................................................................................................2
2.2 Features.....................................................................................................................................3
2.3 Applications................................................................................................................................3
3. Description........................................................................................................................................4
3.1 Block Diagram............................................................................................................................4
3.2 Processor...................................................................................................................................5
3.3 Memory ......................................................................................................................................5
3.4 Real Time Clock.........................................................................................................................5
3.5 Serial Communications..............................................................................................................6
3.6 Parallel Port................................................................................................................................6
3.7 SCSI Interface............................................................................................................................6
3.8 Ethernet Interface.......................................................................................................................6
3.9 IP I/O..........................................................................................................................................6
3.10 VMEbus Interface.....................................................................................................................7
3.10.1 VMEbus Master ...................................................................................................................7
3.10.2 VMEbus Slave......................................................................................................................7
3.11 Interrupts ..................................................................................................................................8
3.11.1 VMEbus Interrupt Handler...................................................................................................8
3.11.2 Internal Interrupts.................................................................................................................8
3.11.3 VMEbus Interrupter..............................................................................................................8
3.12 VMEbus System Controller Functions......................................................................................9
3.13 Power Supply Monitor/Watchdog.............................................................................................9
3.14 Local Bus Monitor.....................................................................................................................9
3.15 Configuration Switch.................................................................................................................9
3.16 EEPROM..................................................................................................................................9
4. Installation.......................................................................................................................................10
5. Configuration ..................................................................................................................................11
5.1 PCB Layout ..............................................................................................................................11
5.2 Link and Switch Definitions ......................................................................................................12
5.2.1 LK1 Abort Switch Enable......................................................................................................12
5.2.2 LK2 Reset Switch Enable.....................................................................................................12
5.2.3 LK3 VMEbus Reset Out Enable...........................................................................................13
5.2.4 LK4 VMEbus Reset In Enable..............................................................................................13
5.2.5 LK5 CPU Cache Inhibit.........................................................................................................14
5.2.6 LK6 Cheapernet Heart Beat Enable.....................................................................................14
5.2.7 LK7,8,9 Ethernet AUI/Cheapernet Select ............................................................................15
5.2.8 LK10,11,12,14,15 EPROM Size & Type Select...................................................................15
5.2.9 LK13 SCSI Termination Disable...........................................................................................16
5.2.10 LK18,19 CPU 5/3.3V Selection..........................................................................................16

iv
5.2.11 LK21 SRAM Backup Selection..........................................................................................17
5.2.12 LK22 VMEbus System Controller Enable..........................................................................17
5.2.13 Configuration Switch..........................................................................................................18
5.3 Indicators..................................................................................................................................18
5.3.1 Green LED - RUNNING........................................................................................................18
5.3.2 Red LED - VMEbus Master Access.....................................................................................18
6. Connector Pinouts ..........................................................................................................................19
6.1 JP1 & JP2 Serial Port Connections..........................................................................................19
6.2 JP3 Parallel Port Connections..................................................................................................19
6.3 JP4 Cheapernet Connector......................................................................................................20
6.4 JP4 Optional 10BaseT Connector............................................................................................20
6.5 JP5A/B IP A/B Connections.....................................................................................................21
6.6 JP7 CPU Fan Power................................................................................................................22
6.7 JP8 JTAG Connector ...............................................................................................................22
6.8 J1 SCSI Connections...............................................................................................................22
6.9 J14 SCSI Peripheral Power Connections.................................................................................23
6.10 P2 I/O Connections ................................................................................................................23
6.11 Protection Fuses.....................................................................................................................24
7. Programming..................................................................................................................................25
7.1 Address Map............................................................................................................................25
7.1.1 I/O Address Map...................................................................................................................26
7.2 Memory Module........................................................................................................................26
7.3 VMEbus Master Access...........................................................................................................27
7.3.1 A16:D16 (D08EO).................................................................................................................27
7.3.2 A16:D32................................................................................................................................27
7.3.3 A24:D16 (D08EO).................................................................................................................27
7.3.4 A24:D32................................................................................................................................28
7.3.5 A32:D16................................................................................................................................28
7.3.6 A32:D32................................................................................................................................28
7.4 SRAM.......................................................................................................................................29
7.5 EPROM....................................................................................................................................29
7.6 SCSI Controller ........................................................................................................................30
7.6.1 Overview...............................................................................................................................30
7.6.2 Programming........................................................................................................................30
7.6.3 Hardware Specific Considerations.......................................................................................30
7.6.4 SCSI Controller Registers.....................................................................................................31
7.6.5 SCSI Electrical Interface.......................................................................................................32
7.7 Ethernet Controller...................................................................................................................33
7.7.1 Overview...............................................................................................................................33
7.7.2 Programming........................................................................................................................33
7.7.3 PORT Access.......................................................................................................................33
7.7.4 Channel Attention Access ....................................................................................................34
7.7.5 Bus Error Handling................................................................................................................34
7.7.6 SYSBUS Byte Requirements ...............................................................................................34
7.7.7 Electrical Interface ................................................................................................................34
7.8 Interrupt Controller ...................................................................................................................35
7.8.1 Overview...............................................................................................................................35
7.8.2 Processor Interrupter............................................................................................................35
7.8.3 VMEbus interrupter...............................................................................................................36

v
7.8.4 Interrupt Controller Registers ...............................................................................................36
7.8.4.1 VMEIRQ Enable Register ...................................................................................36
7.8.4.2 VMEIRQ Vector Register....................................................................................36
7.8.4.3 VMEIRQ Level Register......................................................................................37
7.8.4.4 LOCIRQ Enable Register....................................................................................37
7.8.4.5 ETHIRQ Enable Register....................................................................................37
7.8.4.6 Local IRQ Status Register ..................................................................................38
7.9 IP Controller .............................................................................................................................39
7.9.1 Overview...............................................................................................................................39
7.9.2 IP Expansion Interface..........................................................................................................39
7.9.3 IP Interrupts...........................................................................................................................39
7.9.4 Memory Space Address Map...............................................................................................40
7.9.5 I/O & ID Space Address Map ...............................................................................................41
7.9.6 IP Controller Registers..........................................................................................................42
7.9.6.1 IRQ Level A0 Register ........................................................................................42
7.9.6.2 IRQ Level A1 Register ........................................................................................42
7.9.6.3 IRQ Level B0 Register ........................................................................................42
7.9.6.4 IRQ Level B1 Register ........................................................................................43
7.9.6.5 IP Clock Speed Select Register..........................................................................43
7.9.6.6 IP SYNC Clock Select Register ..........................................................................43
7.10 VMEbus Slave Access Controller...........................................................................................45
7.10.1 Overview ............................................................................................................................45
7.10.2 Standard (A24) & Extended (A32) Accesses....................................................................45
7.10.3 Short I/O (A16) Accesses..................................................................................................46
7.10.4 Controlling The Window Size ............................................................................................46
7.10.5 Local Address Generation.................................................................................................46
7.10.6 Address Control Registers.................................................................................................47
7.10.6.1 A32VBA - A32 VMEbus Base Address Register ................................................47
7.10.6.2 A32MSK - A32 VMEbus Address Mask Register ...............................................47
7.10.6.3 A24VBA - A24 VMEbus Base Address Register ................................................47
7.10.6.4 A24MSK - A24 VMEbus Address Mask Register ...............................................47
7.10.6.5 A16VBA - A16 VMEbus Base Address Register ................................................47
7.10.6.6 A32LBA - A32 Local Base Address Register......................................................47
7.10.6.7 A24LBA - A24 Local Base Address Register......................................................48
7.10.6.8 ADDRCTL - Address Control Register................................................................48
7.11 Configuration Switch...............................................................................................................49
7.11.1 Configuration Switch Layout..............................................................................................49
7.11.2 Configuration Switch Register ...........................................................................................49
7.12 Real Time Clock/Timers.........................................................................................................50
7.12.1 Overview ............................................................................................................................50
7.12.2 Hardware Specific Considerations ....................................................................................50
7.12.3 Programming .....................................................................................................................51
7.13 Parallel Port/Timer..................................................................................................................52
7.13.1 Overview ............................................................................................................................52
7.13.2 Port A Usage......................................................................................................................52
7.13.3 Port B Usage......................................................................................................................52
7.13.4 Port C Usage......................................................................................................................54
7.13.5 Handshake Pin Usage.......................................................................................................55
7.13.6 MC68230 PI/T Registers ...................................................................................................55
7.14 Serial Communications Controller..........................................................................................56

vi
7.14.1 Overview ............................................................................................................................56
7.14.2 Serial Clock Sources..........................................................................................................56
7.14.3 Programming .....................................................................................................................57
8. Specifications..................................................................................................................................58
8.1 On-Board Functions.................................................................................................................58
8.2 VMEbus Master........................................................................................................................58
8.3 VMEbus Slave..........................................................................................................................58
8.4 VMEbus System Controller Functions......................................................................................58
8.5 VMEbus Interrupts....................................................................................................................59
8.6 IP Functions .............................................................................................................................59
8.7 Board Configuration .................................................................................................................59
8.8 Operating Environment ............................................................................................................59
Appendix A Data Sheet & Manual References.....................................................................................60
A.1 MC68040/68LC040/68EC040 User's Manual..........................................................................60
A.2 MC68060/68LC060/68EC060 User's Manual..........................................................................60
A.3 82596CA User's Manual ..........................................................................................................60
A.4 53C710 Data Manual & Programmers Guide ..........................................................................60
A.5 DP8570A Data Sheet...............................................................................................................60
A.6 Z85230 User's Manual.............................................................................................................60
A.7 MC68230 Data Sheet...............................................................................................................60
A.8 VMEbus Specification ..............................................................................................................60
A.9 RS422/485 Interface Module User's Manual............................................................................60
A.10 AM29F040 Data Book ............................................................................................................60
A.11 NMC24C02 Data Sheet..........................................................................................................61
A.12 MEM390 Memory Module User's Manual...............................................................................61
A.13 MEM400 Memory Module User's Manual...............................................................................61
A.14 MEM480 Memory Module User's Guide.................................................................................61
A.15 MEM4SD Memory Module User's Guide................................................................................61
A.16 EXP100 Quad IP Expansion User's Manual...........................................................................61
Appendix B CPU Cache Coherency and Bus Snooping.......................................................................62
B.1 BVME4000 (MC68040)............................................................................................................62
B.2 BVME6000 (MC68060)............................................................................................................64
Appendix C Memory Module Pinout......................................................................................................66
Appendix D IP Expansion Interface Pinout ...........................................................................................67
Appendix E Thermal Management .......................................................................................................68
Appendix F Circuit Diagrams................................................................................................................69

vii
List of Figures
Figure Page
Figure 1 Board Layout.............................................................................................................................2
Figure 2 Block Diagram...........................................................................................................................4
Figure 3 PCB Layout.............................................................................................................................11
Figure 4 LK1 Abort Switch Enable Location..........................................................................................12
Figure 5 LK2 Reset Switch Enable Location.........................................................................................12
Figure 6 LK3 VMEbus Reset Out Enable Location...............................................................................13
Figure 7 LK4 VMEbus Reset In Enable Location..................................................................................13
Figure 8 LK5 CPU Cache Inhibit Location.............................................................................................14
Figure 9 LK6 Cheapernet Heart Beat Enable Location.........................................................................14
Figure 10 LK7,8,9 Ethernet AUI/Cheapernet Select Location...............................................................15
Figure 11 LK10,11,12,14,15 EPROM Size & Type Select Location......................................................15
Figure 12 LK13 SCSI Termination Disable Location.............................................................................16
Figure 13 LK18,19 CPU 5/3.3V Selection Location ..............................................................................16
Figure 14 LK21 SRAM Backup Selection Location...............................................................................17
Figure 15 LK22 VMEbus System Controller Enable Location...............................................................17
Figure 16 Configuration Switch Location...............................................................................................18
Figure 17 JP1 & JP2 Serial Port Connections.......................................................................................19
Figure 18 JP3 Parallel Port Connections ..............................................................................................19
Figure 19 JP4 Optional 10BaseT Connector ........................................................................................20
Figure 20 IP Connector Pin Numbering Viewed from solder side of BVME4000/6000.........................21
Figure 21 Flat Cable Connector Pin Numbering Viewed from front of JP5...........................................21
Figure 22 JP7 CPU Fan Power.............................................................................................................22
Figure 23 JP8 JTAG Connector............................................................................................................22
Figure 24 J1 SCSI Connections............................................................................................................22
Figure 25 J14 SCSI Peripheral Power Connections .............................................................................23
Figure 26 Protection Fuse Positions .....................................................................................................24
Figure 27 Configuration Switch Layout..................................................................................................49

viii
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1 BVME4000/6000
Copyright 1993,1995,1998,2001 BVM Ltd.
1. Introduction
1.1 Scope
This manual provides :-
A getting started guide.
Configuration details.
A user reference guide.
A memory map.
A map of all register locations.
A detailed description of all dedicated registers.
Details of implementation specific considerations for major devices.
General hardware description.
This manual does not provide:-
Detailed data on the operation of the major devices.
Details of VMEbus & IndustryPack™ Specifications.
Information is provided to allow the module to be integrated into a system and configured by the
system software. This User Manual is intended for use by system integrators, service personnel,
software engineers and end users.
Unless otherwise stated, address information is in hexadecimal notation.
The term "IP" is used as an abbreviation for "IndustryPack™" throughout this manual.
1.2 BVME4000 Part Numbers
452-40231/40331 MC68EC040 25/33MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
452-42231/42331 MC68040 25/33MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
Other versions of the BVME4000 are available to special order, where any of the VMEbus I/F,
ETHERNET, SCSI & IP I/F may be omitted or 512Kb SRAM fitted. Contact your supplier for details.
1.3 BVME6000 Part Numbers
452-40631 MC68EC060 66MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
452-42531 MC68060 50MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
Other versions of the BVME6000 are available to special order, where any of the VMEbus I/F,
ETHERNET, SCSI & IP I/F may be omitted or 512Kb SRAM fitted. Contact your supplier for details.
1.4 Memory Module Part Numbers
453-82390/83390 MEM390 25(50)/33(66)MHz 4Mbyte DRAM *
453-82403/83403 MEM400 25(50)/33(66)MHz 16Mbyte DRAM & 4Mbyte FLASH
453-82404/83404 MEM400 25(50)/33(66)MHz 16Mbyte DRAM & 8Mbyte FLASH
453-82482/83482 MEM480 25(50)/33(66)MHz 48Mbyte DRAM *
453-85016/86016 MEM4SD 25(50)/33(66)MHz 16Mbyte SDRAM
453-87064/88064 MEM4SD 25(50)/33(66)MHz 64Mbyte SDRAM
453-87128/88128 MEM4SD 25(50)/33(66)MHz 128Mbyte SDRAM
453-89256/90256 MEM4SD 25(50)/33(66)MHz 256Mbyte SDRAM
Other Memory Module types and options are available, * denotes type not recommended for new
designs. Some Memory Module types can also be "stacked" two high, to increase capacity or mix
memory types. Contact your supplier for details.

BVME4000/6000 2
Copyright 1993,1995,1998,2001 BVM Ltd.
2. Overview
2.1 Board Layout
STATUS LEDs
VMEbus
P1 CONN.
ABORT
RESET
SERIAL
CH. B
SERIAL
CH. A
IP I/O CONN.
CHEAPER
PRINTER
CONN.
NET
LOW
PROM HIGH
PROM
MEMORY
MODULE
INTERFACE
2 X 50 WAY VMEbus
P2 CONN.
68040
or
68060
IndustryPack


Site A
Site B
IndustryPack


Figure 1 Board Layout

3 BVME4000/6000
Copyright 1993,1995,1998,2001 BVM Ltd.
2.2 Features
!BVME4000 - MC68040 CPU (MC68EC040/68LC040 options).
"25 MHz and 33 MHz clock speed variants.
"4096 byte data and instruction caches.
!BVME6000 - MC68060 CPU (MC68EC060/68LC060 options).
"50 MHz and 66 MHz clock speed variants (25 MHz or 33 MHz bus).
"8192 byte data and instruction caches.
!32-bit wide burst fill Dual Ported (with Bus Snooping) memory module interface with NO
capacity limitations allowing many options, for example:
"8Mbytes of FLASH EPROM (Erasable, Programmable non-volatile storage).
"256Mbytes DRAM.
!2Mbyte EPROM pair (16-bit wide), supports 5V FLASH (1Mbyte).
!512K/2Mbyte Non-volatile (battery backed) SRAM (32-bit wide).
!2Kbit EEPROM (NMC24C02).
!High Performance DMA driven 5Mbyte/sec SCSI Interface (NCR53C710).
!High Performance DMA driven Ethernet/Cheapernet (10BaseT option) (82596CA).
!Two 16-bit IP Compatible Sites (Double height 32-bit access supported).
"Expansion Connector allowing 4 IP Compatible Site daughter board.
"8MHz, 32MHz and proprietary high speed 'Source Synchronous Modes' supported.
!Two Interrupt driven serial I/O ports - RS232, RS422 and RS485 options (Z85230).
!Real Time Clock (Battery backed) Including Tick timer, 2 16-bit timers and non-volatile
configuration RAM (DP8570).
!Bi-directional Parallel port including one further 24-bit interrupting Counter/timer (MC68230).
!Optimised A32,A24,A16:D32,D16,D08 master/slave VMEbus interface.
"VMEbus Interrupter.
"VMEbus Interrupt handler.
"Location monitor - Mailbox Interrupts.
!VMEbus System Controller Functions.
"Four level Arbiter (programmable ROR, RWD and SGL).
"RESET, SYSCLK generator.
!Single slot, 6U form factor.
!Available built as a single solution disc based module.
!OS-9, VxWorks, Linux & debug monitor software support.
!Fully compatible to VMEbus specification revision C.1.
2.3 Applications
!VMEbus Main System Processor.
!VMEbus Intelligent I/O Processor.
!High Performance Embedded Processor.

BVME4000/6000 4
Copyright 1993,1995,1998,2001 BVM Ltd.
3. Description
3.1 Block Diagram
68040
or
68060
SCSI
Controller Ethernet Controller VMEbus Slave
Internal Bus
Arbiter
Cheapernet
or 10BaseT
Interface
P2
AUI I/F
Front Panel
BNC or
RJ45
P2
SCSI
Dual Serial
Comms
Controller
50 way
Direct
Connector
EPROM
2Mb
16 Bit Wide
Serial
Buffers
14 way
Connector
JP2
14 way
Connector
JP1
P2
Serial
SRAM
512Kb/2Mb
32 Bit Wide
Memory
Module
R.T.C.
2 x Timers IP Interface
IP A IP B
IP
Expansion
Interface
Front Panel
50 way I/O
Front Panel
50 way I/O
WatchDog
&
Bus Timers Parallel I/O
& Timer
Centronics
Buffers
26 way
Connector
JP3
P2
Parallel I/O
VMEbus
Master
VMEbus
SYSCON
VMEbus
Interrupter
VMEbus
Interrupt
Handler
EEPROM
Figure 2 Block Diagram

5 BVME4000/6000
Copyright 1993,1995,1998,2001 BVM Ltd.
3.2 Processor
The BVME4000 is based on the MC68040 32-bit processor from Motorola running at 25 or 33MHz.
This virtual memory processor provides a MC68030 compatible integer processor running
concurrently with an IEEE754 compatible floating-point unit (FPU). In addition two fully independent
data and instruction demand page memory management units (MMU's) and two independent 4Kbyte
caches provide efficient bus interface with a high degree of instruction execution parallelism.
The BVME6000 is similar to the BVME4000, but is based on the MC68060 32-bit processor from
Motorola running at 50MHz with a 25MHz bus. The MC68060 provides a MC68040 compatible integer
processor running concurrently with a MC68040 IEEE754 compatible floating-point unit (FPU). In
addition two fully independent data and instruction MC68040 compatible demand page memory
management units (MMU's) and two independent 8Kbyte caches.
The BVME4000 and BVME6000 are also available in lower cost versions with the
MC68LC040/68LC060, which provide the same functionality as the MC68040/68060, but without the
FPU, and with the MC68EC040/68EC060 which provide the same functionality, but without the MMU
or FPU. The MC68LC060/68EC060 can run at 50 or 66MHz with a 25 or 33MHz bus respectively.
3.3 Memory
The BVME4000/6000 may be fitted with a large variety of 32-bit wide, burst fill memory devices. The
BVME4000/6000 uses the BVM memory module interface which provides a full 32-bit MC68040/68060
bus, and supports 2/1/1/1 (no wait state) accesses to a variety of standard BVM memory modules,
allowing use of memory modules which currently include:
!8 to 48Mbytes DRAM (5/3/3/3 access at 33MHz bus clock).
!16 to 512Mbytes DRAM (4/1/1/1 read, 3/2/2/2 write at 25 & 33MHz bus clock).
!16Mbytes DRAM plus 8Mbyte FLASH EPROM (4/2/2/2 DRAM, 5/2/2/2 FLASH access).
This memory can be dual ported allowing concurrent accesses by both the processor and other
VMEbus masters. These accesses may be 'snooped' by the processor to maintain cache coherency.
This, together with the onboard 'location monitor' allows full multiprocessor communication with other
CPU (and DMA) VMEbus cards.
The BVME4000/6000 also provides 2Mbytes (512Kbytes to special order) of battery-backed 32-bit
wide Static RAM, providing a 5 CPU clock cycle access at 25MHz or 33MHz bus clock. This SRAM
may be used for non-volatile storage applications, or as main system memory in applications where a
memory module is not fitted. The SRAM can also be dual ported to the VMEbus.
A pair of 32-pin JEDEC pinout sockets provide up to 2Mbytes of 16-bit wide EPROM providing a 10
CPU clock cycle access at 25MHz or 33MHz bus clock. These sockets can support 512K, 1M, 2M, 4M
and 8Mbit EPROM devices, and up to 4Mbit 5V FLASH devices.
3.4 Real Time Clock
The BVME4000/6000 provides a battery backed Real Time Clock using the DP8570 device. This
device is battery backed, and maintains date and time data. The DP8570 can also generate an
interrupt from it's periodic timer from 1mS to 1 second, or from two other independent 16-bit timers on
chip. The timers offer a resolution of up to 500nS, and can be used in one-shot or periodic interrupt
mode. A small amount of non-volatile storage is also provided for system configuration purposes. The
DP8570 is battery backed using a lithium battery giving typically 10 years of non-volatile operation.

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Copyright 1993,1995,1998,2001 BVM Ltd.
3.5 Serial Communications
Two serial communications interfaces are provided from a Z85230 SCC device. The Z85230 provides
both synchronous (SDLC/HDLC) and asynchronous protocols. Asynchronous baud rates of up to
115.2Kbit/s (using the on-board crystal) are supported. Field changeable buffer modules allow RS232,
RS422 or RS485 electrical interfaces to be selected for either (or both) channels. The two serial
interfaces are available on the front panel, or via the rear P2 connector. The synchronous clock
signals are also available via the P2 connector.
3.6 Parallel Port
An 8-bit, bi-directional I/O port with interrupt driven handshake is provided allowing direct connection to
Centronics devices. This is implemented in a 68230 which includes a further 24-bit timer with interrupt
capability. This device also provides part of the board control functions, and is used to control the
software watchdog function. The parallel port is connected to a dedicated connector near the front
panel, or via the P2 connector.
3.7 SCSI Interface
A SCSI interface is provided built around the NCR53C710. This provides asynchronous transfers of up
to 5Mbytes per second. The 32-bit DMA driven interface allows direct access to the entire memory
map of the BVME4000/6000. The burst mode interface stacks up 16 bytes at a time and transfers
them as a line transfer at up to 4/2/2/2 access speeds at 25MHz bus clock. At 5Mbyte/s this gives a
400nS burst every 3.2µS or 12.5% bus bandwidth requirement. The 53C710 is an intelligent processor
in its own right, running SCSI SCRIPTS software. This enables very high level commands to be issued
to the SCSI interface further minimising processor overhead. The SCSI interface is connected to a
dedicated 50-way connector and is also available via the P2 connector.
3.8 Ethernet Interface
An Ethernet Interface is provided built around the Intel 82596CA. This provides a 32-bit DMA driven
interface to both Ethernet (via the AUI interface on the P2 connector) and either Cheapernet (via a
front panel BNC) or optionally 10BaseT (via a front panel RJ45). The 32-bit DMA driven interface
allows direct access to the entire memory map of the BVME4000/6000 allowing full packet
management by the 82596CA. Each 32-bit transfer requires 320nS maximum (including arbitration) to
execute the cycle. A transfer will occur no more frequently than every 4µS (4 bytes at 1Mbyte per
second). Thus worst case bus bandwidth requirement is 8% at 25MHz bus clock.
3.9 IP I/O
Two standard IP compatible sites are provided. The IP interface complies fully with the IP
specification. The two sites may be used individually for single IP's which are accessed as 16-bit wide,
or as a pair for double IP's, which are accessed as 32-bit wide. IP operation is supported at 8MHz,
32MHz, and CPU synchronous speeds. The IP DMA function is not supported by these two sites, but
may be supported on an IP daughter board (see below). The IP ID and I/O spaces are 256bytes each,
and the memory spaces are 8Mbytes. IP vectored interrupts are fully supported and the interrupt levels
may be individually programmed.
An IP expansion bus connector is provided to allow additional IP's to be supported. A further 4 IP's
may be added on a daughter board connected to this expansion interface. Two 'virtual IP' sites are
also available for controlling the daughter board IP interface. The daughter board may include a local
DMA controller and RAM which is accessed through one of the 'virtual IP' sites, thus supporting the IP
DMA function.

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Copyright 1993,1995,1998,2001 BVM Ltd.
3.10 VMEbus Interface
Full VMEbus system controller functions are provided including SYSCLK drive, Bus time out monitor,
SYSRESET drive and an efficient 4 level bus arbiter working in prioritised (PRI), single level (SGL), or
round robin (RRS) arbitration modes.
3.10.1 VMEbus Master
Byte or Word Master accesses may be made to the Standard (A24) and Short I/O (A16) address
spaces, Byte, Word and Longword Master accesses may be made to the Extended (A32) address
space. BVME4000/6000 Longword accesses to the A24 or A16 address space may be converted to
two Word cycles, or proceed as a Longword cycle dependant upon the BVME4000/6000 address
space accessed. Read Modify Write (RMW) cycles are supported for all of these accesses.
VMEbus arbitration is normally configured to be Release On Request (ROR) method. This may be
changed to Release When Done (RWD) with a PLD change. Both schemes use FAIR requesting,
ensuring each master has an equal chance of obtaining the bus. Digital bus busy filtering and
arbitration interleaving is used to ensure premium arbitration performance.
3.10.2 VMEbus Slave
The memory module and on-board SRAM are dual ported onto the VMEbus. The VMEbus base
address, size of window and local base address are programmable for the A24 and A32 address
spaces. The BVME4000/6000 responds to Byte and Word and Longword Slave accesses to the A32,
A24 and A16 address spaces.
The BVME4000/6000 can snoop VMEbus slave accesses if enabled to do so. Thus although the CPU
uses extensive caching, full coherency is maintained by the CPU providing any data that is 'stale' in
the accessed memory - refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)".
A VMEbus location monitor is also supported in the A16 address space. This is a fixed 256byte
window size, and the VMEbus base address is programmable. A local interrupt can be enabled when
the A16 VMEbus window is accessed.
The BVME4000/6000 is compatible with VMEbus address pipelining and RMW cycles.

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Copyright 1993,1995,1998,2001 BVM Ltd.
3.11 Interrupts
3.11.1 VMEbus Interrupt Handler
The BVME4000/6000 may be configured to respond to VMEbus interrupts on any of the 7 VMEbus
interrupt levels. Each interrupt level may be programmed to be enabled or disabled individually.
A User vectored VMEbus interrupt causes the CPU to reply with a VMEbus Master interrupt
acknowledge cycle. This cycle uses only the that is broadcast in a similar way to the addresses. The
A1,2,3 address lines indicate the address level being handled.
The interrupting device returns an ID vector on the odd data byte. This is used as the user vector by
the CPU.
3.11.2 Internal Interrupts
Internal CPU interrupts are generated from a variety of sources, as detailed in the table below:
Source Level Type
VMEIRQ7:1 IRQ7:1 Vectored
ACFAIL 7 Auto
ABORT 7 Auto
8570 RTC 6 Auto
68230 TIMER 5 Vectored
MEMORY MODULE 4 Auto
85230 SCC 3 Vectored
53C710 SCSI 3 Auto
68230 PARALLEL 2 Vectored
82596CA ETHERNET 2 Auto
LOCATION MONITOR 1 Auto
IPA, IPB INT0 & INT1 Programmable Vectored
IP EXPANSION I/F Programmable Vectored
3.11.3 VMEbus Interrupter
The BVME4000/6000 may generate VMEbus interrupts on any programmable single level 1-7 and
responds with a software programmable ID to the subsequent interrupt acknowledge cycle. Writing the
ID to the a vector register causes a VMEbus interrupt to be generated on the selected level. The
BVME4000/6000 VMEbus interrupt ID vector may be programmed to suit the application.

9 BVME4000/6000
Copyright 1993,1995,1998,2001 BVM Ltd.
3.12 VMEbus System Controller Functions
The BVME4000/6000 provides a number of system controller functions that may be enabled by
programming the relevant registers, or by link selection.
RESET
Asserted if +5V falls below 4.65V and when a link is installed. VMEbus RESET has a minimum
asserted period of 200mS.
ARBITRATION
The BVME4000/6000 can be programmed/link selected to provide SGL, PRI or RRS arbitration.
SYSCLK
The BVME4000/6000 can be programmed/link selected to provide a 16MHz VMEbus SYSCLK.
BUS TIMER
The BVME4000/6000 can be programmed/link selected to provide a 128µS Bus Timeout BERR
signal.
3.13 Power Supply Monitor/Watchdog
A MAX791 provides power up/power down control for the battery switching for the non-volatile RAM
and processor RESET. It also provides a processor watchdog capability controlled via the Board
Control Register. If enabled, the processor will be reset if the software fails to maintain pulses to the
watchdog circuit.
3.14 Local Bus Monitor
All bus cycles (including VMEbus arbitration requests) are timed by an on-board timer. If any cycle
takes longer than 64 CPU clock cycles a Transfer Error Abort signal and bus error exception vector
are generated. Thus the processor cannot simply hang-up as a result of invalid addresses being
generated from software. The exception to this is for VMEbus accesses - these are timed by the
VMEbus Timeout monitor.
3.15 Configuration Switch
A 4-bit configuration switch is provided for software bootstrap detection. This switch does not affect
the hardware directly, but is normally used by the software to set up the BVME4000/6000's
configuration registers.
3.16 EEPROM
An NM24C02 serial I2C EEPROM device provides 2Kbits of EEPROM storage for configuration
settings. The NMC24C02 is accessed on the I2C serial bus via the Board Control Register.

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Copyright 1993,1995,1998,2001 BVM Ltd.
4. Installation
The BVME4000/6000 module is inserted into a vacant VMEbus slot. If it is to function as the system
controller, then it should be positioned in slot 1. It passes through all VMEbus daisy chained arbitration
signals.
IACK should be jumpered to IAKIN on the backplane at slot 1. All interrupt IAKIN to IAKOUT and BGIN
to BGOUT signals should be jumpered across vacant slots to the right of the module.
If it is not the system controller, it may be located in any of the VMEbus slots to the right of the
VMEbus system controller.
To install the BVME4000/6000:
1. Ensure all backplane jumpers associated with the slot for the BVME4000/6000 are removed.
2. Ensure the BVME4000/6000 module is correctly configured for the target system.
3. If the Parallel interface is to be used, plug in the parallel cable to JP3 (if not using the P2
connections).
4. Connect the SCSI cable to the 50 way SCSI connector on the BVME4000/6000 (if not using
the P2 connections), ensure the correct polarity.
5. Insert the BVME4000/6000 module into the rack pushing the VMEbus connector fully home.
6. Secure the BVME4000/6000 into the rack with the two fixing screws top and bottom.
7. Plug in serial cables to JP1 and/or JP2 (if not using the P2 connections).
8. If using Cheapernet, connect the Cheapernet BNC-T connector to the BVME4000/6000 BNC
connector or if using the optional 10BaseT, connect the RJ45 connector to the
BVME4000/6000 RJ45 connector.
9. Connect the IP I/O connections to the two 50 way front panel connectors.
10. Ensure that the configuration switch is set up correctly for the software installation.
11. Ensure the correct application EPROM's are fitted.
Removal is the reverse of assembly.
If the test or application software fails, ensure that all installation instructions have been correctly
carried out. Some typical reasons for incorrect operation are:-
1. Socketed components may become disturbed in transit. Push home all socketed components
where suspect.
2. The BVME4000/6000 module uses the VMEbus Address modifier codes to determine address
significance. Ensure the host CPU module produces the correct address modifier codes.
3. Ensure that all links are configured to the default set-up or that any alterations to the default
are correctly configured.
4. Ensure that the VMEbus backplane (if used) is correctly configured with regard to the daisy-
chain signal jumpers and the IACK termination jumpers (if any).
The BVME4000/6000 CPU requires adequate airflow across it to ensure correct operation. A heatsink
may need to be fitted to the CPU - refer to "Appendix E Thermal Management (on page 68)" for more
details.