CAES GR-CPCIS-XCKU User manual

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
GR-CPCIS-XCKU Development Board
GR-CPCIS-XCKU
GR-CPCIS-XCKU-DSUM
Feb 2022, Version 1.2
Baseline features
The GR-CPCIS-XCKU is an FPGA development
board. Its cutting-edge technology allows the
development of next-generation system on
chips and its interfaces are particularly suited
to emulate space applications.
This board implements a Xilinx Ultrascale
FPGA, in a 1517 ball-grid-array package. The
board was initially designed to use a XCKU060
sized device but is compatible with larger
devices of the same series with the same
footprint.
Optionally, the board also features a GR716
rad-hard microcontroller which can act as the
FPGA supervisor for scrubbing and
programming.
The GR-CPCIS-XCKU is a 1 slot, 6U high
board with a CPCI-S backplane format, and
can be used stand alone on the bench top, or
installed in a CPCI-Serial rack
The GR-CPCIS-XCKU includes:
•Xilinx XCKU, in 1517 pin FCBGA package.
•GR716 microcontroller. - Optional
•FPGA interface to DDR3 SDRAM via two
SODIMM connectors.
•SPI flash for FPGA configuration (512
Mbit), for GR716 boot (256 Mbit), and for
data (256 Mbit). The FPGA has also access
to two NVM: 512 Mbit SPI and Parallel
Flash memory (40 bit wide)
•FMC Mezzanine expansion connector.
•Scrubbing interface for FPGA. Available
also without the GR716.
•2×10 connector to interface with a GR-
ACC-6U_6UART breakout board providing
access to 6 UARTS (or 16 GPIOs).
Front Panel interfaces
•2x RJ45 to FPGA via magnetics and Gbit
Ethernet transceivers. RGMII interface to
FPGA
•1x eSATA for SpaceFibre to FPGA via CML
redriver.
•2x MDM9 for SpaceWire via LVDS
transceivers/repeaters to FPGA.
•Status LEDs, push-buttons and switches
•2xSMA or 2xSMB for PPS time distribution to
FPGA.
•2xUSB ports for:
oJTAG access to FPGA and FMC
(separate chains)
oGR716 debug UART and two FPGA
UARTs
Backplane interfaces
•8 x SpaceFibre for full-mesh interconnect
using FPGA GTH banks
•8 x SpaceWire for dual-star interconnect
•Dual-redundant CAN-bus to FPGA and/or
GR716 via two or four transceivers
•SGPIO and I2C connected to FPGA with
jumper-configurable pull-ups
•12V supply from backplane that can be turned
off by the external input PS_ON#
•Other utility signals connected to the FPGA
This board design is part of a project that has received funding from the European
Union's Horizon 2020 research and innovation programme under Grant Agree-
ment No 869945.
Data Sheet & User Manual
Feb 2022

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
2
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
TABLE OF CONTENTS
1Introduction..................................................................................................................................3
1.1 Scope of the Document .........................................................................................................3
1.2 Reference Documents............................................................................................................3
2Abbreviations ...............................................................................................................................3
3Introduction..................................................................................................................................4
3.1 Overview ...............................................................................................................................4
3.2 Handling ................................................................................................................................7
4Board Design................................................................................................................................8
4.1 Board Block Diagram............................................................................................................8
4.2 Board Mechanical Format .....................................................................................................9
4.3 Xilinx Ultrascale FPGA ........................................................................................................9
4.4 GR716 Microcontroller .......................................................................................................11
4.5 Memory ...............................................................................................................................13
4.6 Board Interfaces ..................................................................................................................14
4.6.1 High-Speed Serial Links ..............................................................................................14
4.6.2 Ethernet ........................................................................................................................18
4.6.3 PPS...............................................................................................................................19
4.6.4 FTDI (USB Serial) .......................................................................................................20
4.6.5 FMC Mezzanine Board Interface.................................................................................21
4.6.6 I2C................................................................................................................................23
4.6.7 JTAG ............................................................................................................................24
4.6.8 FPGA-GPIO.................................................................................................................25
4.6.9 Reset Circuit.................................................................................................................26
4.6.10 CPCI-S Backplane .......................................................................................................27
4.7 Oscillators and Clock Inputs ...............................................................................................30
4.8 Power Supply and Voltage Regulation ................................................................................32
5Setting Up and Using the Board ................................................................................................34
5.1 GR716 Processor Programing and Debug...........................................................................34
5.2 FPGA Programing and Debug.............................................................................................34
5.3 Switches and Bootstrap Signals ..........................................................................................34
6Interfaces and Configuration......................................................................................................36
6.1 List of Connectors ...............................................................................................................36
6.2 List of Headers ....................................................................................................................50
6.3 List of Oscillators, Switches and LED's..............................................................................51

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
3
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
1INTRODUCTION
1.1 Scope of the Document
This document provides a Data Sheet & User Manual for the GR-CPCIS-XCKU Development and
Demonstration board.
The work has been performed by Cobham Gaisler AB, Göteborg, Sweden.
1.2 Reference Documents
The following documents are referred as they contain relevant information:
[RD1] GR-CPCIS-XCKU Board_schematic.pdf, Schematic
[RD2] GR-CPCIS-XCKU Board_assy_drawing.pdf, Assembly Drawing
[RD3] GRMON3 User's Manual, available from:
https://www.gaisler.com/index.php/products/debug-tools/grmon3
[RD4] GR716 LEON3FT Microcontroller - User’s Manual, available at
https://www.gaisler.com/doc/gr716/gr716-ds-um.pdf
2ABBREVIATIONS
ASIC
Application Specific Integrated Circuit.
DSU
Debug Support Unit
EDAC
Error Detection and Correction
ESA
European Space Agency
ESD
Electro-Static Discharge
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
GPIO
General Purpose Input / Output
HSSL
High Speed Serial Link
IC
Integrated Circuit
I/O
Input/Output
IP
Intellectual Property
LDO
Low Drop-Out
LPC
Low Pin Count
LVDS
Low Voltage Digital Signalling
PCB
Printed Circuit Board
POL
Point of Load
PPS
Pulse Per Second
SOC
System On a Chip

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
4
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
SPW
SpaceWire
TBC
To Be Confirmed
TBD
To Be Defined
3INTRODUCTION
3.1 Overview
This document describes the GR-CPCIS-XCKU Development Board.
This equipment is a 1 slot, 6U high board with a CPCI-S backplane format. It can be used stand alone
or it can be installed in a CPCI-Serial rack.
The cutting edge Ultrascale FPGA allows the development of next-generation system on chips on
FPGA while also providing a fantastic benchmark for FPGA prototypes for ASIC products.
This board also provides developers with a convenient hardware platform for the evaluation and
development of software for the GR716 radiation hardened microcontroller.
Figure 1 GR-CPCIS-XCKU Development Board

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
5
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
The board contains the following main items as detailed in section 4 of this document:
•Cobham Gaisler GR716 radiation-hardened microcontroller featuring a fault-tolerant LEON3
SPARC V8 processor (Note: This item is not fitted in some versions of the board)
•Xilinx Ultrascale XCKU060 FPGA
•Dual SODIMM sockets for DDR3 SDRAM memory (96 bit wide interface)
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for FPGA
configuration
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for FPGA non-
volatile memory
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for GR716-boot
configuration
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for GR716-data non-
volatile memory
•Parallel Flash memory (40 bit wide) connected to FPGA
•Dual Gbit Ethernet interface with standard RJ45 connector
•Dual 1 PPS interface
•Dual SPW/LVDS interfaces with MDM9S connector on front panel
•front panel SPFI interface with E-SATA connector
•FTDI Serial to USB converter for FMC- JTAG and GR716 DSU/UART interfaces
•FMC mezzanine connector
•Header for FPGA SOCPIO (16 pins)
•Header for GR716 SOCPIO (30 pins)
•CPCI-S Backplane interface
•VIN power input (+12V nom.) via backplane or 2 pin header
•on-board regulators converting from VIN to various on-board voltages
•switches and headers for bootstrap and configuration settings

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
6
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Figure 2 GR-CPCIS-XCKU Main Board

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
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GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
3.2 Handling
ATTENTION: OBSERVE PRECAUTIONS FOR HANDLING
ELECTROSTATIC SENSITIVE DEVICES
This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges
(ESD). When handling or installing the unit observe appropriate precautions and ESD safe practices.
When not in use, store the unit in an electrostatic protective container or bag.
When configuring the jumpers on the board, or connecting/disconnecting cables, ensure that the unit
is in an unpowered state.
When operating the board in a 'stand-alone' configuration, the power supply should be current limited
to prevent damage to the board or power supply in the event of an over-current situation.
This board is intended for commercial use and evaluation in a standard laboratory environment,
nominally, 20°C. All devices are standard commercial types, intended for use over the standard
commercial operating temperature range (0 to 70ºC).

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
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GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
4BOARD DESIGN
4.1 Board Block Diagram
Figure 3 GR-CPCIS-XCKU Board Block Diagram
The GR-CPCIS-XCKU Board provides the electrical functions and interfaces as represented in the
block diagram, Figure 3.

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
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GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
4.2 Board Mechanical Format
The design is conceived as a 6U high, 1 slot wide module for mounting in the controller slot of a 6U
rack with a CPCI-S Backplane.
The dimensions of the main PCB are 233.35x160mm (excluding the connector protrusions).
The board can be fitted with a front-panel compatible with either a 20.32mm or 25.4mm wide
backplane pitch. The default panel is for a 25.4mm backplane pitch.
This prototype board is intended for installation in a rack with forced air cooling. However, for
installation in conduction cooled environment, a future design could accommodate standard
wedgeloks on the top and bottom rail edges of the board.
This would require the exact Wedge-lok type and mounting hole definition to be known, and the front
panel to be modified to accommodate them.
A standard FMC style (VITA 57.1) mezzanine interface connector allows an FMC -LPC Mezzanine
board to be mounted to the board.
The face to face mounting distance between the main board and mezzanine boards is 10mm. While
the prototype board is mounted using simple 10mm nickel-brass Hex spacers, a future design could
accommodate a custom aluminium bracket to act as a thermal interface between the two boards.
4.3 Xilinx Ultrascale FPGA
This board implements a large Xilinx Ultrscale FPGA, in a 1517 ball-grid-array package. The board
is initially designed to use a XCKU060 sized device, but is compatible with larger devices of the
same series which have the same footprint.
The Xilinx Ultrascale FPGA is a complex device with many modes of operation and features. For the
details of the interfaces, operation and programming, refer to the dedicated Xilinx documentation.
The assignment of the FPGA Logic banks is represented in Figure 4.
For detailed information about the signal and pin assignment of the FPGA, refer to [RD1].
The pin assignment has been performed taking into account the constraints described in the Xilinx
document ‘Radiation Tolerant Kintex UltraScaleXQRKU060 FPGA Data Sheet’ (DS882.pdf), which
would allow this board to also be populated with the FPGA version in a CNA1509 package instead
of the commercial FFVA1517 package.

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
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GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Figure 4 FPGA Bank and Signal Assignment
Bank 0 of the FPGA is the configuration and JTAG interface of the FPGA. To allow the GR716 to
perform configuration of the FPGA via its SMAP interface, it must connect to the GR716 with 3.3V
logic. This bank and Bank 65 are constrained to use an I/O voltage of 3.3V. Bank 65 is assigned also
to the SMAP interface of the GR716 and for other miscellaneous 3.3V logic interface signals.
Logic banks 24 & 25 are assigned to the FMC-LPC interface (LVDS differential pairs) and to 1.8V
logic for the PIO interface and are powered with an I/O voltage of 1.8V.
Logic banks 44, 45, 46, 47, 48 are dedicated to the 96 bit wide DDR3 Memory data interface and are
powered with an I/O voltage of 1.5V. The pin assignment of these interfaces takes account of the
assignment constraints imposed by the Xilinx ‘Memory Interface Generator’ (MIG) software for
DDR3 interfaces.
Logic bank 64 is assigned to the Dual Gbit Ethernet interface, the SPI Data flash and the parallel
NOR flash interface and is powered with an I/O voltage of 1.8V
Logic banks 66 and 67 are assigned to the SPW interfaces (LVDS differential pairs) and are powered
with an I/O voltage of 1.8V
Logic bank 68 is also assigned to the parallel NOR flash interface and is powered with an I/O voltage
of 1.8V.
GTH banks Q224 provides high speed transceiver links for the Front Panel SPFI interface and the
optional High Speed serial link pins on the FMC connector.
GTH banks Q225, Q226, Q227, Q228 provide high speed transceiver links to the CPCI-S backplane.