CAES GR-CPCIS-XCKU User manual

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
GR-CPCIS-XCKU Development Board
GR-CPCIS-XCKU
GR-CPCIS-XCKU-DSUM
Feb 2022, Version 1.2
Baseline features
The GR-CPCIS-XCKU is an FPGA development
board. Its cutting-edge technology allows the
development of next-generation system on
chips and its interfaces are particularly suited
to emulate space applications.
This board implements a Xilinx Ultrascale
FPGA, in a 1517 ball-grid-array package. The
board was initially designed to use a XCKU060
sized device but is compatible with larger
devices of the same series with the same
footprint.
Optionally, the board also features a GR716
rad-hard microcontroller which can act as the
FPGA supervisor for scrubbing and
programming.
The GR-CPCIS-XCKU is a 1 slot, 6U high
board with a CPCI-S backplane format, and
can be used stand alone on the bench top, or
installed in a CPCI-Serial rack
The GR-CPCIS-XCKU includes:
•Xilinx XCKU, in 1517 pin FCBGA package.
•GR716 microcontroller. - Optional
•FPGA interface to DDR3 SDRAM via two
SODIMM connectors.
•SPI flash for FPGA configuration (512
Mbit), for GR716 boot (256 Mbit), and for
data (256 Mbit). The FPGA has also access
to two NVM: 512 Mbit SPI and Parallel
Flash memory (40 bit wide)
•FMC Mezzanine expansion connector.
•Scrubbing interface for FPGA. Available
also without the GR716.
•2×10 connector to interface with a GR-
ACC-6U_6UART breakout board providing
access to 6 UARTS (or 16 GPIOs).
Front Panel interfaces
•2x RJ45 to FPGA via magnetics and Gbit
Ethernet transceivers. RGMII interface to
FPGA
•1x eSATA for SpaceFibre to FPGA via CML
redriver.
•2x MDM9 for SpaceWire via LVDS
transceivers/repeaters to FPGA.
•Status LEDs, push-buttons and switches
•2xSMA or 2xSMB for PPS time distribution to
FPGA.
•2xUSB ports for:
oJTAG access to FPGA and FMC
(separate chains)
oGR716 debug UART and two FPGA
UARTs
Backplane interfaces
•8 x SpaceFibre for full-mesh interconnect
using FPGA GTH banks
•8 x SpaceWire for dual-star interconnect
•Dual-redundant CAN-bus to FPGA and/or
GR716 via two or four transceivers
•SGPIO and I2C connected to FPGA with
jumper-configurable pull-ups
•12V supply from backplane that can be turned
off by the external input PS_ON#
•Other utility signals connected to the FPGA
This board design is part of a project that has received funding from the European
Union's Horizon 2020 research and innovation programme under Grant Agree-
ment No 869945.
Data Sheet & User Manual
Feb 2022

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Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
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TABLE OF CONTENTS
1Introduction..................................................................................................................................3
1.1 Scope of the Document .........................................................................................................3
1.2 Reference Documents............................................................................................................3
2Abbreviations ...............................................................................................................................3
3Introduction..................................................................................................................................4
3.1 Overview ...............................................................................................................................4
3.2 Handling ................................................................................................................................7
4Board Design................................................................................................................................8
4.1 Board Block Diagram............................................................................................................8
4.2 Board Mechanical Format .....................................................................................................9
4.3 Xilinx Ultrascale FPGA ........................................................................................................9
4.4 GR716 Microcontroller .......................................................................................................11
4.5 Memory ...............................................................................................................................13
4.6 Board Interfaces ..................................................................................................................14
4.6.1 High-Speed Serial Links ..............................................................................................14
4.6.2 Ethernet ........................................................................................................................18
4.6.3 PPS...............................................................................................................................19
4.6.4 FTDI (USB Serial) .......................................................................................................20
4.6.5 FMC Mezzanine Board Interface.................................................................................21
4.6.6 I2C................................................................................................................................23
4.6.7 JTAG ............................................................................................................................24
4.6.8 FPGA-GPIO.................................................................................................................25
4.6.9 Reset Circuit.................................................................................................................26
4.6.10 CPCI-S Backplane .......................................................................................................27
4.7 Oscillators and Clock Inputs ...............................................................................................30
4.8 Power Supply and Voltage Regulation ................................................................................32
5Setting Up and Using the Board ................................................................................................34
5.1 GR716 Processor Programing and Debug...........................................................................34
5.2 FPGA Programing and Debug.............................................................................................34
5.3 Switches and Bootstrap Signals ..........................................................................................34
6Interfaces and Configuration......................................................................................................36
6.1 List of Connectors ...............................................................................................................36
6.2 List of Headers ....................................................................................................................50
6.3 List of Oscillators, Switches and LED's..............................................................................51

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Feb 2022, Version 1.2
1INTRODUCTION
1.1 Scope of the Document
This document provides a Data Sheet & User Manual for the GR-CPCIS-XCKU Development and
Demonstration board.
The work has been performed by Cobham Gaisler AB, Göteborg, Sweden.
1.2 Reference Documents
The following documents are referred as they contain relevant information:
[RD1] GR-CPCIS-XCKU Board_schematic.pdf, Schematic
[RD2] GR-CPCIS-XCKU Board_assy_drawing.pdf, Assembly Drawing
[RD3] GRMON3 User's Manual, available from:
https://www.gaisler.com/index.php/products/debug-tools/grmon3
[RD4] GR716 LEON3FT Microcontroller - User’s Manual, available at
https://www.gaisler.com/doc/gr716/gr716-ds-um.pdf
2ABBREVIATIONS
ASIC
Application Specific Integrated Circuit.
DSU
Debug Support Unit
EDAC
Error Detection and Correction
ESA
European Space Agency
ESD
Electro-Static Discharge
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
GPIO
General Purpose Input / Output
HSSL
High Speed Serial Link
IC
Integrated Circuit
I/O
Input/Output
IP
Intellectual Property
LDO
Low Drop-Out
LPC
Low Pin Count
LVDS
Low Voltage Digital Signalling
PCB
Printed Circuit Board
POL
Point of Load
PPS
Pulse Per Second
SOC
System On a Chip

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Document Data Sheet & User Manual
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SPW
SpaceWire
TBC
To Be Confirmed
TBD
To Be Defined
3INTRODUCTION
3.1 Overview
This document describes the GR-CPCIS-XCKU Development Board.
This equipment is a 1 slot, 6U high board with a CPCI-S backplane format. It can be used stand alone
or it can be installed in a CPCI-Serial rack.
The cutting edge Ultrascale FPGA allows the development of next-generation system on chips on
FPGA while also providing a fantastic benchmark for FPGA prototypes for ASIC products.
This board also provides developers with a convenient hardware platform for the evaluation and
development of software for the GR716 radiation hardened microcontroller.
Figure 1 GR-CPCIS-XCKU Development Board

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The board contains the following main items as detailed in section 4 of this document:
•Cobham Gaisler GR716 radiation-hardened microcontroller featuring a fault-tolerant LEON3
SPARC V8 processor (Note: This item is not fitted in some versions of the board)
•Xilinx Ultrascale XCKU060 FPGA
•Dual SODIMM sockets for DDR3 SDRAM memory (96 bit wide interface)
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for FPGA
configuration
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for FPGA non-
volatile memory
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for GR716-boot
configuration
•512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for GR716-data non-
volatile memory
•Parallel Flash memory (40 bit wide) connected to FPGA
•Dual Gbit Ethernet interface with standard RJ45 connector
•Dual 1 PPS interface
•Dual SPW/LVDS interfaces with MDM9S connector on front panel
•front panel SPFI interface with E-SATA connector
•FTDI Serial to USB converter for FMC- JTAG and GR716 DSU/UART interfaces
•FMC mezzanine connector
•Header for FPGA SOCPIO (16 pins)
•Header for GR716 SOCPIO (30 pins)
•CPCI-S Backplane interface
•VIN power input (+12V nom.) via backplane or 2 pin header
•on-board regulators converting from VIN to various on-board voltages
•switches and headers for bootstrap and configuration settings

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Figure 2 GR-CPCIS-XCKU Main Board

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3.2 Handling
ATTENTION: OBSERVE PRECAUTIONS FOR HANDLING
ELECTROSTATIC SENSITIVE DEVICES
This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges
(ESD). When handling or installing the unit observe appropriate precautions and ESD safe practices.
When not in use, store the unit in an electrostatic protective container or bag.
When configuring the jumpers on the board, or connecting/disconnecting cables, ensure that the unit
is in an unpowered state.
When operating the board in a 'stand-alone' configuration, the power supply should be current limited
to prevent damage to the board or power supply in the event of an over-current situation.
This board is intended for commercial use and evaluation in a standard laboratory environment,
nominally, 20°C. All devices are standard commercial types, intended for use over the standard
commercial operating temperature range (0 to 70ºC).

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4BOARD DESIGN
4.1 Board Block Diagram
Figure 3 GR-CPCIS-XCKU Board Block Diagram
The GR-CPCIS-XCKU Board provides the electrical functions and interfaces as represented in the
block diagram, Figure 3.

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4.2 Board Mechanical Format
The design is conceived as a 6U high, 1 slot wide module for mounting in the controller slot of a 6U
rack with a CPCI-S Backplane.
The dimensions of the main PCB are 233.35x160mm (excluding the connector protrusions).
The board can be fitted with a front-panel compatible with either a 20.32mm or 25.4mm wide
backplane pitch. The default panel is for a 25.4mm backplane pitch.
This prototype board is intended for installation in a rack with forced air cooling. However, for
installation in conduction cooled environment, a future design could accommodate standard
wedgeloks on the top and bottom rail edges of the board.
This would require the exact Wedge-lok type and mounting hole definition to be known, and the front
panel to be modified to accommodate them.
A standard FMC style (VITA 57.1) mezzanine interface connector allows an FMC -LPC Mezzanine
board to be mounted to the board.
The face to face mounting distance between the main board and mezzanine boards is 10mm. While
the prototype board is mounted using simple 10mm nickel-brass Hex spacers, a future design could
accommodate a custom aluminium bracket to act as a thermal interface between the two boards.
4.3 Xilinx Ultrascale FPGA
This board implements a large Xilinx Ultrscale FPGA, in a 1517 ball-grid-array package. The board
is initially designed to use a XCKU060 sized device, but is compatible with larger devices of the
same series which have the same footprint.
The Xilinx Ultrascale FPGA is a complex device with many modes of operation and features. For the
details of the interfaces, operation and programming, refer to the dedicated Xilinx documentation.
The assignment of the FPGA Logic banks is represented in Figure 4.
For detailed information about the signal and pin assignment of the FPGA, refer to [RD1].
The pin assignment has been performed taking into account the constraints described in the Xilinx
document ‘Radiation Tolerant Kintex UltraScaleXQRKU060 FPGA Data Sheet’ (DS882.pdf), which
would allow this board to also be populated with the FPGA version in a CNA1509 package instead
of the commercial FFVA1517 package.

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Figure 4 FPGA Bank and Signal Assignment
Bank 0 of the FPGA is the configuration and JTAG interface of the FPGA. To allow the GR716 to
perform configuration of the FPGA via its SMAP interface, it must connect to the GR716 with 3.3V
logic. This bank and Bank 65 are constrained to use an I/O voltage of 3.3V. Bank 65 is assigned also
to the SMAP interface of the GR716 and for other miscellaneous 3.3V logic interface signals.
Logic banks 24 & 25 are assigned to the FMC-LPC interface (LVDS differential pairs) and to 1.8V
logic for the PIO interface and are powered with an I/O voltage of 1.8V.
Logic banks 44, 45, 46, 47, 48 are dedicated to the 96 bit wide DDR3 Memory data interface and are
powered with an I/O voltage of 1.5V. The pin assignment of these interfaces takes account of the
assignment constraints imposed by the Xilinx ‘Memory Interface Generator’ (MIG) software for
DDR3 interfaces.
Logic bank 64 is assigned to the Dual Gbit Ethernet interface, the SPI Data flash and the parallel
NOR flash interface and is powered with an I/O voltage of 1.8V
Logic banks 66 and 67 are assigned to the SPW interfaces (LVDS differential pairs) and are powered
with an I/O voltage of 1.8V
Logic bank 68 is also assigned to the parallel NOR flash interface and is powered with an I/O voltage
of 1.8V.
GTH banks Q224 provides high speed transceiver links for the Front Panel SPFI interface and the
optional High Speed serial link pins on the FMC connector.
GTH banks Q225, Q226, Q227, Q228 provide high speed transceiver links to the CPCI-S backplane.

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GTH banks Q126, Q127, Q128 are unused on this board.
4.4 GR716 Microcontroller
The microcontroller has the following interfaces as represented in Figure 5.
SMAP Parallel data interface for read-out and programming of FPGA configuration.
I2C Two-wire Serial I2C interface with GR716 as Master (see section 4.6.6)
SPI SPI master interface for user-defined SPI data exchange with FPGA
FPIO[3..0] Four 3.3V LVTTL signals for user defined signalling between GR716 and FPGA
SPW Spacewire LVDS interface between GR716 and FPGA
CAN3 CAN data interface between GR716 and Backplane
CAN4 CAN data interface between GR716 and Backplane
SPI-BOOT SPI Memory interface to Serial SPI memory (see section 4.5)
SPI-DATA SPI Memory interface to Serial SPI memory (see section 4.5)
UART2 2-wire Serial UART interface to GR716 UART0 interface
DSU 2-wire Serial UART interface to GR716 Debug Support Unit interface
GR-STS GPIO output connected to front-panel LED for user defined signalling
GR-EN Front panel DIP Switch connected to GR716 DSU Enable input
GR-BRE Front panel DIP Switch connected to GR716 DSU Break input
GPIO-HDR28 GPIO signals for GR716 connected to standard 0.1” header for user defined purposes
FMC-ON GPIO to Power Circuits to control the enabling of the +12V FMC power supply
Figure 5 GR716 Interfaces

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Table 1 Definition of GR716 GPIO pin functions
GR716 GPIO pin
Interface
Function
GPIO0
SPI Data Prom
SLV1
GPIO1
SPI Data Prom
SCK1
GPIO2
SPI Data Prom
MOSI1
GPIO3
SPI Data Prom
MISO1
GPIO4
GPIO to FPGA
FIO0
GPIO5
GPIO to FPGA
FIO1
GPIO6
GPIO to FPGA
FIO2
GPIO7
GPIO to FPGA
FIO3
GPIO8
GPIO to Power Control
FMC-ON
GPIO9
GPIO Header
GPIO9
GPIO10
GPIO Header
GPIO10
GPIO11
GPIO Header
GPIO11
GPIO12
GPIO Header
GPIO12
GPIO13
SPI to FGPA
SCLK0
GPIO14
SPI to FGPA
MISO0
GPIO15
SPI to FGPA
MOSI0
GPIO16
GPIO Header
GPIO16
GPIO17
SPI to FGPA
SLV0
GPIO18
GPIO Header
GPIO18
GPIO19
GPIO Header
GPIO19
GPIO20
GPIO Header
GPIO20
GPIO21
GPIO Header
GPIO21
GPIO22
GPIO Header
GPIO22
GPIO23
GPIO Header
GPIO23
GPIO24
GPIO Header
GPIO24
GPIO25
SMAP to FPGA
SMAP_INITN
GPIO26
SMAP to FPGA
SMAP_DONE
GPIO27
SMAP to FPGA
SMAP_D0
GPIO28
SMAP to FPGA
SMAP_D1
GPIO29
SMAP to FPGA
SMAP_D2
GPIO30
SMAP to FPGA
SMAP_D3
GPIO31
SMAP to FPGA
SMAP_D4
GPIO32
SMAP to FPGA
SMAP_D5
GPIO33
SMAP to FPGA
SMAP_D6
GPIO34
SMAP to FPGA
SMAP_D7
GPIO35
SMAP to FPGA
SMAP_PROGN
GPIO36
SMAP to FPGA
SMAP_RDWR
GPIO37
SMAP to FPGA
SMAP_CSIN
GPIO38
SMAP to FPGA
SMAP_SCLK
GPIO39
GPIO Header
GPIO39
GPIO40
GPIO Header
GPIO40
GPIO41
I2C
SDA
GPIO42
I2C
SCL
GPIO43
GPIO Header
GPIO43

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GR716 GPIO pin
Interface
Function
GPIO44
GPIO Header
GPIO44
GPIO45
GPIO Header
GPIO45
GPIO46
GPIO Header
GPIO46
GPIO47
GPIO Header
GPIO47
GPIO48
GPIO Header
GPIO48
GPIO49
GPIO Header
GPIO49
GPIO50
UART
RXD2
GPIO51
UART
TXD2
GPIO52
GPIO Header
GPIO52
GPIO53
GPIO Header
GPIO53
GPIO54
GPIO Header
GPIO54
GPIO55
GPIO Header
GPIO55
GPIO56
GPIO Header
GPIO56
GPIO57
Front Panel LED
GR-STS
GPIO58
CAN to backplane
CAN-TX3
GPIO59
CAN to backplane
CAN-RX3
GPIO60
GPIO Header
GPIO60
GPIO61
CAN
CAN-RX4
GPIO62
CAN
CAN-TX4
GPIO63
GPIO Header
GPIO63
The GR716 microcontroller is a complex device with many modes of operation. For the details of the
interfaces, operation and programming, refer to [RD4].
4.5 Memory
This boards incorporates various on-board memories as represented in Figure 6:
DDR3-SDRAM Dual SODIMM sockets for DDR3 SDRAM memory (96 bit wide interface).
Nominally this data width can provide 64 bit data and 32 bit check-bit data
for error correction. Due to constraints in the internal FGPA design, these are
implemented with two controller interfaces.
FPGA-CONFIG 512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) as
non-volatile storage for the FPGA configuration.
FPGA-MEMORY 512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for
FPGA non-volatile memory
NOR-FLASH Parallel Flash memory (40 bit wide) connected to FPGA, implemented using
Cypress, Spansion, S29GL064S90TFVV10, 64 Mbit (8 M x 8-Bit/4M x 16-
Bit), 1.8 V Flash PROM, in, TSOP-56 packages.
GR716-BOOT 512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for
GR716-boot configuration
GR716-DATA 512 Mbit SPI memory (Cypress, S25FL512SAGN in SOIC-16 package) for
GR716-data non-volatile memory

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Figure 6 Board Memory Configuration
4.6 Board Interfaces
4.6.1 High-Speed Serial Links
The board incorporates a large number of SPFI and SpaceWire Links distributed between the FPGA,
CPCI-S backplane, GR716 Processor and External Front panel connectors as represented in Figure 7.
The Front panel Spacewire connections are buffered with DS10BR150TSD/NOPB LVDS transceivers.
The Front Panel SPFI connections are buffer with a DS80PCI102SQ/NOPB CML re-driver circuit.

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Figure 7 On-Board SpaceWire Connections
SPW links which connect to the FPGA are implemented using using the LVDS differential
drivers/receivers implemented in the FPGA.
All SPW links which connect to the backplane (SPW1to SPW8) include resistors to provide Fail-
safe/Cold-Spare protection network as shown in Figure 8. This means the internal 100Ohm
differential pair termination inside the FPGA cannot be used for these links.
Figure 8 SPW fail-safe RX network

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The interface signal to FPGA pin correspondence is listed in Table 2 .
Table 2 SPW Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
SPW0
TXD_N/_P
Bank 67
IO_L4
T17/T18
TXS_N/_P
Bank 67
IO_L3
N16/N17
RXD_N/_P
Bank 67
IO_L2
P16/R16
RXS_N/_P
Bank 67
IO_L1
P18/P19
SPW1
TXD_N/_P
Bank 67
IO_L16
E17/F17
TXS_N/_P
Bank 67
IO_L14
H17/H18
RXD_N/_P
Bank 67
IO_L21
A19/B19
RXS_N/_P
Bank 67
IO_L23
A20/B20
SPW2
TXD_N/_P
Bank 66
IO_L16
F12/F13
TXS_N/_P
Bank 66
IO_L15
D14/D15
RXD_N/_P
Bank 66
IO_L13
E15/F15
RXS_N/_P
Bank 66
IO_L14
F14/G15
SPW3
TXD_N/_P
Bank 67
IO_L12
J18/K18
TXS_N/_P
Bank 67
IO_L11
J19/J20
RXD_N/_P
Bank 67
IO_L9
L18/L19
RXS_N/_P
Bank 67
IO_L10
J16/K16
SPW4
TXD_N/_P
Bank 67
IO_L20
C18/D18
TXS_N/_P
Bank 67
IO_L19
C19/D19
RXD_N/_P
Bank 67
IO_L13
G19/H19
RXS_N/_P
Bank 67
IO_L15
F19/G20
SPW5
TXD_N/_P
Bank 67
IO_L23
B17/C17
TXS_N/_P
Bank 67
IO_L24
A17/A18
RXD_N/_P
Bank 67
IO_L17
E20/F20
RXS_N/_P
Bank 67
IO_L18
E18/F18
SPW6
TXD_N/_P
Bank 66
IO_L12
H14/J14
TXS_N/_P
Bank 66
IO_L11
G15/G16
RXD_N/_P
Bank 66
IO_L10
J15/K15
RXS_N/_P
Bank 66
IO_L9
K12/K13
SPW7
TXD_N/_P
Bank 66
IO_L19
A12/A13
TXS_N/_P
Bank 66
IO_L20
C13/D13
RXD_N/_P
Bank 66
IO_L18
E12/E13
RXS_N/_P
Bank 66
IO_L17
D16/E16
SPW8
TXD_N/_P
Bank 66
IO_L7
H13/J13
TXS_N/_P
Bank 66
IO_L8
L12/L13
RXD_N/_P
Bank 66
IO_L5
L15/M15

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Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
RXS_N/_P
Bank 66
IO_L6
P14/P15
SPW9
TXD_N/_P
Bank 67
IO_L8
M16/M17
TXS_N/_P
Bank 67
IO_L7
K17/L17
RXD_N/_P
Bank 67
IO_L6
R17/R18
RXS_N/_P
Bank 67
IO_L5
N18/N19
SPW10
TXD_N/_P
Bank 66
IO_L24
B14/C14
TXS_N/_P
Bank 66
IO_L21
A14/A15
RXD_N/_P
Bank 66
IO_L23
B15/B16
RXS_N/_P
Bank 66
IO_L22
B12/C12
SPFI links are implemented using using the GTH High Speed Transceivers of the FPGA. As per the
SPFI requirements, all links are AC coupled and have 100kOhm pull-down resistors to ground.
The interface signal to FPGA pin correspondence is listed in Table 3 .
Table 3 SPFI Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
SPFI1
TXD1_P/_N
Bank 228
TX3
V6/V5
RXD1_P/_N
Bank 228
RX3
V2/V1
TXD2_P/_N
Bank 228
TX2
Y6/Y5
RXD2_P/_N
Bank 228
RX2
W4/W3
SPFI2
TXD1_P/_N
Bank 228
TX1
AA4/AA3
RXD1_P/_N
Bank 228
RX1
Y2/Y1
TXD2_P/_N
Bank 228
TX0
AB6/AB5
RXD2_P/_N
Bank 228
RX0
AB2/AB1
SPFI3
TXD1_P/_N
Bank 227
TX3
AD6/AD5
RXD1_P/_N
Bank 227
RX3
AC4/AC3
TXD2_P/_N
Bank 227
TX2
AE4/AE3
RXD2_P/_N
Bank 227
RX2
AD2/AD1
SPFI4
TXD1_P/_N
Bank 227
TX1
AF6/AF5
RXD1_P/_N
Bank 227
RX1
AF2/AF1
TXD2_P/_N
Bank 227
TX0
AG8/AG7
RXD2_P/_N
Bank 227
RX0
AG4/AG3
SPFI5
TXD1_P/_N
Bank 226
TX3
AH6/AH5
RXD1_P/_N
Bank 226
RX3
AH2/AH1
TXD2_P/_N
Bank 226
TX2
AJ8/AJ7
RXD2_P/_N
Bank 226
RX2
AJ4/AJ3
SPFI6
TXD1_P/_N
Bank 226
TX1
AK6/AK5
RXD1_P/_N
Bank 226
RX1
AK2/AK1
TXD2_P/_N
Bank 226
TX0
AL8/AL7
RXD2_P/_N
Bank 226
RX0
AL4/AL3

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
18
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
SPFI7
TXD1_P/_N
Bank 225
TX3
AM6/AM5
RXD1_P/_N
Bank 225
RX3
AM2/AM1
TXD2_P/_N
Bank 225
TX2
AN8/AN7
RXD2_P/_N
Bank 225
RX2
AN4/AN3
SPFI8
TXD1_P/_N
Bank 225
TX1
AP6/AP5
RXD1_P/_N
Bank 225
RX1
AP2/AP1
TXD2_P/_N
Bank 225
TX0
AR8/AR7
RXD2_P/_N
Bank 225
RX0
AR4/AR3
SPFI-FP
TXD_P/_N
Bank 224
TX3
AT6/AT5
RXD_P/_N
Bank 224
RX3
AT2/AT1
4.6.2 Ethernet
A Dual Ethernet RJ45 interface is provided on the board front panel, and is connected to the FPGA.
This interface can operate in either 100Mbit or Gbit mode, and can be used for standard networking.
Two external PHY devices, (Micrel KSZ9031RNX) are implemented on the board.
These PHY devices interface to the FPGA using the RGMII interface standard.
Figure 9 Ethernet RGMII to FPGA interface (1 of 2 shown)
Each interface has a separate MDIO interface connection to the FPGA.
The interface signal to FPGA pin correspondence is listed in Table 4 and Table 5 .
Table 4 ETH0 Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
ETH0
TXD0
Bank 64
IO_L12N
AN19
TXD1
Bank 64
IO_L14N
AL18
TXD2
Bank 64
IO_L11N
AN17

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
19
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
TXD3
Bank 64
IO_L10N
AP18
RXD0
Bank 64
IO_L16P
AK18
RXD1
Bank 64
IO_L16N
AK17
RXD2
Bank 64
IO_L15N
AK16
RXD3
Bank 64
IO_L15P
AJ16
TXCLK
Bank 64
IO_L12P
AM19
TX_CTL
Bank 64
IO_L9N
AM19
RXCLK
Bank 64
IO_L14P
Al19
RX_CTL
Bank 64
IO_L9P
AP16
MDINT
Bank 64
IO_T1U
AN16
MDC
Bank 64
IO_L13N
AM17
MDIO
Bank 64
IO_L10P
AP19
Table 5 ETH1 Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
ETH1
TXD0
Bank 64
IO_L6N
AU19
TXD1
Bank 64
IO_L4P
AV19
TXD2
Bank 64
IO_L5P
AT18
TXD3
Bank 64
IO_L6P
AT19
RXD0
Bank 64
IO_L3P
AU17
RXD1
Bank 64
IO_L5N
AT17
RXD2
Bank 64
IO_L3N
AU16
RXD3
Bank 64
IO_L7N
AR17
TXCLK
Bank 64
IO_L11P
AN18
TX_CTL
Bank 64
IO_L4N
AW18
RXCLK
Bank 64
IO_L13P
AL17
RX_CTL
Bank 64
IO_L7P
AR18
MDINT
Bank 64
IO_L8P
AR20
MDC
Bank 64
IO_T0U
AU20
MDIO
Bank 64
IO_L8N
AT20
4.6.3 PPS
Two SMA connectors are provided on the front panel for user use and expected to be used for PPS
inputs or outputs.
No detailed specification for the type or levels for these signals has been given.
These are therefore connected directly to the FPGA as LVTTL/LVCMOS33 signals, and care should
be taken to ensure the allowable input voltage is not exceeded.
The interface signal to FPGA pin correspondence is listed in Table 6 .
Table 6 PPS Interface to FPGA pin mapping

© Cobham Gaisler AB
Kungsgatan 12 | SE-411 19 Goteborg | Sweden
[phone] | www.caes.com/gaisler
20
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
PPS
PPS0
Bank 65
IO_L13P
AL12
PPS1
Bank 65
IO_L14P
AL14
4.6.4 FTDI (USB Serial)
An FTDI FT4232 serial to USB interface chip is implemented on the board to allow an external PC
to interface to the following serial interfaces:
•GR716 DSU serial interface
•GR716 UART-0 serial interface
•GR716 UART-1 serial interface
•FMC JTAG interface
The front panel interface connector (marked ‘FTDI’ on the front panel) is a standard USB Micro-AB
style connector.
Figure 10 FTDI UART to Serial Interface
The interface signal to FPGA pin correspondence is listed inTable 7 .
Table 7 FTDI Interface to FPGA pin mapping
Interface
Signal
FPGA Bank
FPGA Signal
FPGA pin
UART0
TXD0
Bank 65
IO_L3P
AV13
RXD0
Bank 65
IO_L3N
AW13
UART1
TXD1
Bank 65
IO_L9N
AT12
RXD1
Bank 65
IO_L5N
AV12