Celoxica RC200 User manual

Platform Developer’s Kit
RC200/203 Manual

RC200/203 Manual
Celoxica, the Celoxica logo and Handel-C are trademarks of Celoxica Limited.
All other products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the
copyright holder.
The product described in this document is subject to continuous development and improvement. All
particulars of the product and its use contained in this document are given by Celoxica Limited in good
faith. However, all warranties implied or express, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. Celoxica Limited shall not
be liable for any loss or damage arising from the use of any information in this document, or any
incorrect use of the product.
The information contained herein is subject to change without notice and is for general guidance only.
Copyright © 2005 Celoxica Limited. All rights reserved.
Authors: RG
Document number: 1
Customer Support at http://www.celoxica.com/support/
Celoxica in Europe Celoxica in Japan Celoxica in the Americas
T: [phone] T: [phone] T: [phone]
E: [email protected] E: [e-mail] E: [email protected]
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RC200/203 Manual
Contents
1RC200/203 BOARD.................................................................................................... 8
2RC200/203 OVERVIEW................................................................................................ 9
2.1 STANDARD KIT...................................................................................................... 9
2.2 PROFESSIONAL KIT ............................................................................................. 10
2.3 EXPERT KIT ........................................................................................................ 10
2.4 RC200/203 SUPPORT SOFTWARE........................................................................ 11
3INSTALLATION AND SET-UP ........................................................................................ 12
4HARDWARE DESCRIPTION .......................................................................................... 13
4.1 RC200/203 DEVICES .......................................................................................... 13
4.2 RC200/203 CONNECTORS .................................................................................. 14
4.3 CPLD14
4.3.1 Control and data pins............................................................................................................ 14
4.3.2 CPLD clock............................................................................................................................ 15
4.3.3 Register map in the CPLD for the FPGA .............................................................................. 15
4.3.4 CPLD / parallel port interface................................................................................................ 16
4.4 FPGA18
4.4.1 FPGA operation modes......................................................................................................... 19
4.4.2 Programming the FPGA using the FTU2 program................................................................ 19
4.4.3 Programming the FPGA from the parallel port...................................................................... 19
4.4.4 Programming the FPGA from SmartMedia ........................................................................... 20
4.4.5 Programming from a specific address in the SmartMedia: ................................................... 20
4.4.6 Reading data from the CPLD to the FPGA........................................................................... 20
4.4.7 Writing data to the CPLD from the FPGA ............................................................................. 21
4.4.8 Transferring data between the FPGA and host..................................................................... 21
4.4.9 Using the FPGA in parallel port control mode....................................................................... 21
4.5 PARALLEL PORT ................................................................................................. 21
4.6 SMARTMEDIA FLASH MEMORY............................................................................. 22
4.6.1 SmartMedia connections to the CPLD.................................................................................. 22
4.6.2 FPGA access of SmartMedia................................................................................................22
4.6.3 Parallel port access of SmartMedia ...................................................................................... 23
4.7 ZBT SRAM BANKS ............................................................................................ 23
4.8 CLOCK GENERATOR (PLL).................................................................................. 24
4.8.1 Programming the PLL via the parallel port or FPGA............................................................. 25
4.9 ETHERNET.......................................................................................................... 26
4.10 VIDEO INPUT PROCESSOR .................................................................................. 26
4.11 VIDEO OUTPUT PROCESSORS ............................................................................. 27
4.11.1 Digital / Analogue converter................................................................................................ 27
4.11.2 RGB to NTSC/PAL encoder................................................................................................ 28
4.11.3 TFT flat panel display.......................................................................................................... 28
4.12 AUDIO CODEC................................................................................................... 28
4.13 RS-232 SERIAL TRANSMISSION.......................................................................... 28
4.14 MOUSE AND KEYBOARD PS/2 PORTS.................................................................. 29
4.15 7-SEGMENT DISPLAYS ....................................................................................... 29
4.16 ATA /EXPANSION HEADER................................................................................ 30
4.17 LEDS.............................................................................................................. 32
4.18 CONTACT SWITCHES ......................................................................................... 32
4.19 RESET BUTTON................................................................................................. 33
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RC200/203 Manual
4.20 JTAG CONNECTOR........................................................................................... 33
4.21 CAMERA AND CAMERA SOCKET.......................................................................... 33
4.22 BLUETOOTH MODULE ........................................................................................ 34
4.23 TOUCH SCREEN ................................................................................................ 34
4.24 DATA SHEETS AND SPECIFICATIONS.................................................................... 34
5RC200/203 PSL REFERENCE.................................................................................... 36
5.1 USING THE RC200 PSL...................................................................................... 36
5.2 CLOCK DEFINITIONS ............................................................................................ 36
5.2.1 Specifying a clock source...................................................................................................... 37
5.2.2 Specifying a clock rate .......................................................................................................... 37
5.2.3 Checking the clock rate......................................................................................................... 37
5.3 DETECTING THE BOARD TYPE............................................................................... 37
5.4 LED MACROS..................................................................................................... 38
5.4.1 RC200LEDWrite() ................................................................................................................. 38
5.4.2 RC200LED*Write() macros...................................................................................................38
5.4.3 RC200LEDWriteMask()......................................................................................................... 38
5.5 PUSH BUTTON MACROS ....................................................................................... 39
5.5.1 RC200ButtonRead().............................................................................................................. 39
5.5.2 RC200Button*Read() macros................................................................................................39
5.5.3 RC200ButtonReadMask().....................................................................................................39
5.6 SEVEN-SEGMENT MACROS................................................................................... 39
5.6.1 Setting segments................................................................................................................... 39
5.6.2 Writing digits.......................................................................................................................... 40
5.7 ZBT SRAM MACROS.......................................................................................... 40
5.7.1 RAM management tasks....................................................................................................... 41
5.7.2 Setting the RAM address ...................................................................................................... 41
5.7.3 Write address mask............................................................................................................... 41
5.7.4 Reading from RAM................................................................................................................ 42
5.7.5 Writing data to RAM.............................................................................................................. 42
5.8 PS/2 PORT MACROS............................................................................................ 42
5.8.1 Mouse management tasks....................................................................................................42
5.8.2 Reading data from the mouse...............................................................................................42
5.8.3 Writing data to the mouse ..................................................................................................... 43
5.8.4 Keyboard management tasks................................................................................................43
5.8.5 Reading data from the keyboard........................................................................................... 43
5.8.6 Writing data to the keyboard ................................................................................................. 43
5.9 RS-232 PORT MACROS ....................................................................................... 44
5.9.1 RS-232 management tasks...................................................................................................44
5.9.2 Reading from the RS-232 port ..............................................................................................46
5.9.3 Writing to the RS-232 port..................................................................................................... 46
5.10 TOUCH SCREEN MACROS................................................................................... 46
5.10.1 Touch screen management tasks....................................................................................... 46
5.10.2 Touch screen position (raw)................................................................................................ 46
5.10.3 Touch screen position (scaled) ...........................................................................................47
5.11 VIDEO OUTPUT MACROS .................................................................................... 47
5.11.1 Video output management tasks......................................................................................... 47
5.11.2 Enabling video output.......................................................................................................... 48
5.11.3 Querying screen sizes......................................................................................................... 49
5.11.4 Disabling video output......................................................................................................... 49
5.11.5 Writing a pixel...................................................................................................................... 50
5.11.6 Current scan position .......................................................................................................... 50
5.11.7 Blanking status of current scan position.............................................................................. 50
5.11.8 Horizontal and vertical sync status......................................................................................50
5.12 VIDEO INPUT MACROS........................................................................................ 51
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RC200/203 Manual
5.12.1 Video input management tasks........................................................................................... 51
5.12.2 Selecting the video input..................................................................................................... 51
5.12.3 Selecting the colour-encoding standard.............................................................................. 51
5.12.4 Reading a pair of YCrCb pixels...........................................................................................52
5.12.5 Reading a pair of RGB pixels.............................................................................................. 52
5.12.6 Reading a single RGB pixel ................................................................................................ 53
5.13 AUDIO I/O MACROS........................................................................................... 54
5.13.1 Audio codec management tasks......................................................................................... 54
5.13.2 Setting the audio input......................................................................................................... 54
5.13.3 Boosting the input amplifier................................................................................................. 54
5.13.4 Setting the gain level........................................................................................................... 54
5.13.5 Setting the input sample rate............................................................................................... 55
5.13.6 Reading from the audio interface........................................................................................ 55
5.13.7 Setting the output volume.................................................................................................... 55
5.13.8 Setting the output sample rate ............................................................................................ 56
5.13.9 Writing to the audio interface............................................................................................... 56
5.14 BLUETOOTH MACROS........................................................................................ 56
5.14.1 Bluetooth management tasks..............................................................................................57
5.14.2 Resetting the Bluetooth device............................................................................................ 57
5.14.3 Reading from the Bluetooth device..................................................................................... 57
5.14.4 Writing to the Bluetooth device............................................................................................ 57
5.15 SMARTMEDIA MACROS...................................................................................... 57
5.15.1 Using the SmartMedia macros............................................................................................ 58
5.15.2 SmartMedia management tasks.......................................................................................... 59
5.15.3 Initializing the SmartMedia device.......................................................................................59
5.15.4 SmartMedia manufacturer and device code ....................................................................... 59
5.15.5 Resetting the SmartMedia................................................................................................... 60
5.15.6 Erasing SmartMedia memory.............................................................................................. 60
5.15.7 Number of pages per block................................................................................................. 60
5.15.8 Logical and physical addressing......................................................................................... 60
5.15.9 Reading from and writing to the SmartMedia...................................................................... 62
5.16 ETHERNET MACROS .......................................................................................... 64
5.16.1 Ethernet management tasks ...............................................................................................64
5.16.2 Enabling the Ethernet device .............................................................................................. 65
5.16.3 Setting the Ethernet mode................................................................................................... 65
5.16.4 Disabling the Ethernet device.............................................................................................. 65
5.16.5 Resetting the Ethernet device............................................................................................. 65
5.16.6 Reading a packet ................................................................................................................ 66
5.16.7 Writing a packet to the network........................................................................................... 67
5.17 RECONFIGURING THE FPGA.............................................................................. 68
5.18 CPLD CONTROL............................................................................................... 69
5.18.1 CPLD management tasks ...................................................................................................69
5.18.2 Enabling the CPLD.............................................................................................................. 69
5.19 FPGA /PARALLEL PORT COMMUNICATION.......................................................... 69
5.19.1 Enabling the Send Protocol driver....................................................................................... 70
5.19.2 Disabling the Send Protocol driver......................................................................................70
5.19.3 Writing data to the host PC ................................................................................................. 70
5.19.4 Reading data from the host PC........................................................................................... 70
5.20 EXPANSION PORT PINS ...................................................................................... 71
6INDEX....................................................................................................................... 73
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RC200/203 Manual
Conventions
The following conventions are used in this document.
2Warning Message. These messages warn you that actions may damage your hardware.
ÏHandy Note. These messages draw your attention to crucial pieces of information.
Hexadecimal numbers will appear throughout this document. The convention used is th
the numbe with '0x' in comm at of prefixing r on with standard C syntax.
s:
me DestinationFileName
struct
rackets around an element show that it is optional but it may be repeated any number of times.
string ::= "{character}"
Sections of code or commands that you must type are given in typewriter font like this:
void main();
Information about a type of object you must specify is given in italics like thi
copy SourceFileNa
Optional elements are enclosed in square brackets like this:
[type_Name]
Curly b
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RC200/203 Manual
Assumptions & Omissions
This manual assumes that you:
•have used Handel-C or have the Handel-C Language Reference Manual
•are familiar with common programming terms (e.g. functions)
•are familiar with your operating system (Linux or MS Windows)
This manual does not include:
•instruction in VHDL or Verilog
•instruction in the use of place and route tools
•tutorial example programs. These are provided in the Handel-C User Manual
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RC200/203 board
1 RC200/203 board
The RC200 and RC203 are platforms for evaluation and development of high-performance
FPGA-based applications. The platforms include a Xilinx Virtex-II FPGA, external memory,
programmable clocks, Ethernet, Audio, Video, SmartMedia, Parallel port, RS-232 and PS/2 keyboard
and mouse. Supporting software includes PAL, DSM, the RC200 PSL, and the FTU2 File Transfer
Utility.
The only difference between the RC200 and RC203 platforms is the FPGA fitted, a 2V1000-4 on the
RC200 and a larger 2V3000-4 on the RC203.
The RC200 is available in 3 versions:
•Standard (part number RC-I-200-2V1K4S)
•Professional (part number RC-I-200-2V1K4P)
•Expert (part number RC-I-200-2V1K4E)
The RC203 is also available in 3 versions:
•Standard (part number RC-I-203-2V3K4S)
•Professional (part number RC-I-203-2V3K4P)
•Expert (part number RC-I-203-2V3K4E)
Except where specifically noted in this document "RC200" should be taken as meaning either RC200 or
RC203.
Note: On the RC203 platform it is very important not to use any pins not specifically referenced in this
document. To do so risks damaging the FPGA device.
It is recommended that you use the RC200 Platform Support Library to program the board.
System requirements
•DK Design Suite. Only required if you want to use the PAL, DSM and RC200 Platform
Support libraries.
•Microsoft Windows NT4, Windows 2000 or Windows XP for the FTU2 program and for use
of the DK Design Suite.
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RC200/203 board
2 RC200/203 overview
The devices and connectors on the board are shown in the overview of devices (see page 13) and
overview of connectors (see page 14).
Note: the Xilinx Virtex II device on the RC203 has part number XC2V3000-FG676.
2.1 Standard kit
•Virtex-II 2V1000-4 (RC200) or 2V3000-4 (RC203) FPGA
•Ethernet MAC/PHY with 10/100baseT socket
•2 banks of ZBT SRAM providing a total of 4-MB
•Video support including:
•Composite video in/out
•S-Video in/out
•VGA out
•Camera in (Camera socket provides camera power)
•AC'97 compatible Audio including
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RC200/203 board
•Microphone in
•Line in (Stereo)
•Line/Headphone out (Stereo)
•Connector for SmartMedia Flash memory for storage of BIT files
•CPLD for configuration/reconfiguration and SmartMedia management
•Power-on load from SmartMedia
•Load when SmartMedia installed
•Reconfigure on demand from FPGA
•Parallel port connector and cable, for BIT-file download and host communication with FPGA
•RS-232
•PS/2 keyboard and mouse connectors
•2 seven-segment displays
•2 blue LEDs
•2 momentary contact switches
•50 pin expansion header including:
•33 general I/O pins
•3 power pins (+12V, +5V, +3.3V)
•2 clock pins
•JTAG connector
•Perspex top and bottom covers
•Universal 110/240V power supply (IEC Mains lead not included)
•Celoxica Platform Developer’s Kit including:
•Platform Support Library for RC200/203
•Platform Abstraction Layer for RC200/203
•Data Stream Manager for MicroBlaze soft-core microprocessor
•FTU2 BIT file transfer utility (for Windows NT4, Windows 2000 and Windows XP)
2.2 Professional kit
This provides the following features in addition to the Standard kit:
•Headphone/microphone set
•Mouse
•16-MB SmartMedia card
•Colour camera
2.3 Expert kit
This provides the following features in addition to the Professional Kit:
•Bluetooth wireless module
•Memory banks expanded to 4-MB each giving a board total of 8-MB
•TFT flat panel display or touch screen
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RC200/203 board
2.4 RC200/203 support software
The following software support for the RC200/203 is provided as part of the Platform Developer's Kit:
•RC200 Platform Support Library (PSL)
•RC200 Platform Abstraction Layer (PAL) implementation
•Data Stream Manager (DSM) implementation for MicroBlaze soft-core microprocessor
•FTU2 program (for Windows NT4, Windows 2000 and Windows XP). Allows you you to
download BIT files onto the FPGA.
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RC200/203 overview
3 Installation and set-up
Unpacking the board
You should take care to avoid static discharge when handling the RC200/203 board, as this may
damage it. You are recommended to use an earth strap. If an earth strap is not available, ensure that
you make contact with earth before and during handling of the board, and only handle the board by its
edges.
Connecting the cables
The board must be powered down before you attach cables. The connectors are labelled on the board
and in the overview of connectors (see page 14).
You will need to connect the board to your PC with an IEEE 1284-compliant parallel port cable if you
want to use the Celoxica FTU2 program to download BIT files, or to read from or write to SmartMedia
memory. A cable is provided as part of the RC200/203 kit.
Switching on the power
You need a 12V DC power supply with a 2.1mm, centre-positive plug. The power supply must be able to
source at least 2A.
Peripheral devices should be connected before the RC200/203 Board is turned on. Otherwise the
devices may not function correctly.
LED D2 will light up when the power is on. This is the lower of the 2 LEDS to the left of the Celoxica
copyright printed on the board.
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Installation and set-up
4 Hardware description
This section describes the devices on the RC200, how to program the FPGA and how to transfer data
between the host, SmartMedia and FPGA.
Schematics for the board are available in
InstallDir\PDK\Documentation\PSL\RC200\RC200VBDOC.pdf for the RC200 or in
InstallDir\PDK\Documentation\PSL\RC203\RC203VBDOC.pdf for the RC203 (for installations
using PDK3.1 or later).
Note: On the RC203 platform it is very important not to use any pins not specifically referenced in this
document. To do so risks damaging the FPGA device.
There is also a list of data sheets (see page 34) for the devices.
4.1 RC200/203 devices
DEVICES ON THE RC200/203
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Installation and set-up
4.2 RC200/203 connectors
CONNECTORS ON THE RC200/203
4.3 CPLD
The RC200/203 has a Xilinx XC95144XL 3.3V CPLD.
The CPLD is connected to the:
•FPGA
•Parallel port
•SmartMedia Flash RAM
•JTAG chain
The CPLD can configure the FPGA withdata received from SmartMedia memory, or via the parallel port.
4.3.1 Control and data pins
The RC200 CPLD has 10 control lines and 8 data lines. 3 of the control lines are used as an address
bus. The control lines have two meanings, depending on the FPGA operation mode(see page 19).
The FPGA operation mode is determined by whether the CPLD pin P9 is set high or low.
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Installation and set-up
CPLD control
line RC200 FPGA
pin
RC203
FPGA
pin
Function (normal FPGA
operation) Function (parallel port control mode)
P0 Y19 AB21 CCLK Not used
P1 AA3 AC5
PnCS (Parallel Not Chip
Select) - Input nWR (Not Write) - Input
P2 Y4 AB6
nRDWR (Not Read Write) –
Input/Output nRDWR (Not Read Write) - Output
P3 A2 C4 nPROG Not used
P4 AB20 AD22 DONE Not used
P5 AA19 AC21 Address [0] – Output nINIT – Output
P6 AB19 AD21 Address [1] – Output nWAIT – Output
P7 R22 U24 Address [2] – Output nADDR – Input
P8 V22 Y24
nCS (Not Chip Select) –
Output nDATA – Output
P9 T18 V20 Set high Set low
CPLD data line RC200 FPGA pin RC203 FPGA pin
FD0 V18 Y20
FD1 V17 VY19
FD2 W18 AA20
FD3 Y18 YAB20
FD4 Y5 AB7
FD5 W5 AA7
FD6 AB4 AD6
FD7 AA4 AC6
4.3.2 CPLD clock
The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module. This is divided by
2 to give an internal clock speed of 25MHz.
4.3.3 Register map in the CPLD for the FPGA
The RC200 CPLD has 3 address lines:
CPLD pins RC200 FPGA pins RC203 FPGA pins
P5 Addr[0] AA19 AC21
P6 Addr[1] AB19 AD21
P7 Addr[2] R22 U24
Only the lower 5 of the 8 possible values within the 3-bit CPLD address are used by the FPGA:
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Installation and set-up
0 Control of SmartMedia and PLL
Bit 0: SmartMedia nCS signal
Bit 1: SmartMedia CLE signal
Bit 2: SmartMedia ALE signal
Bit 3: Disable SmartMedia state machine
Bit 4: Not used (Write 0)
Bit 5: Not used (Write 0)
Bit 6: PLL clock pin (I2C bus)
Bit 7: PLL data pin (I2C bus 1 = Tristate (input) 0=0)
1 Read status Register
Bit 0: Master FPGA DONE signal
Bit 1: (not used; undefined)
Bit 2: FPGA nINIT signal
Bit 3: SmartMedia nBUSY signal
Bit 4: SmartMedia Detect (1 = SmartMedia inserted)
Bit 5: SmartMedia not Write Protect
Bit 6: SmartMedia state machine disable status
Bit 7: PLL data line (I2C bus)
2 Data bus access of the SmartMedia
3 Upper byte of Block address for the SmartMedia (only the lower 5 bits are used)
4 Lower byte of Block address for the SmartMedia
5 Read from this address to start reprogramming of the FPGA from
SmartMedia
4.3.4 CPLD / parallel port interface
The RC200 CPLD supports an EPP (Enhanced Parallel Port) interface.
The parallel port is connected to the CPLD on the following pins:
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Installation and set-up
CPLD pins Signal Parallel port pins
76 ParSCTL 13
77 ParPE 12
78 Parnwait 11
79 ParINIT 10
80 Pardata7 9
81 Pardata6 8
82 Pardata5 7
85 Pardata4 6
86 Pardata3 5
89 Paraddr 17
90 Pardata2 4
91 Parnreset 16
92 Pardata1 3
93 Parnerror 15
94 Pardata0 2
95 Parndata 14
96 Parnwrite 1
The CPLD has 3 address pins. When the CPLD is communicating with the parallel port data lines, the 8
values within the 3-bit CPLD address are used as follows:
Address value Description
0 Read and write (i.e. data pins) when FPGA is in parallel port control mode
1 Read and write from host for SmartMedia
2 Not used
3 Read status of signals (8-bit data line from CPLD):
Bit 0: Master FPGA DONE signal
Bit 1: (not used; undefined)
Bit 2: FPGA nINIT signal
Bit 3: SmartMedia nBUSY signal
Bit 4: SmartMedia Detect (1 = SmartMedia inserted)
Bit 5: SmartMedia not Write Protect
Bit 6: SmartMedia state machine disable status
Bit 7: PLL data line (I2C bus)
Write status of signals:
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Installation and set-up
Address value Description
Bit 0: SmartMedia nCS signal
Bit 1: SmartMedia CLE signal
Bit 2: SmartMedia ALE signal
Bit 3: Disable SmartMedia state machine
Bit 4: Master FPGA nPROG pin (inverted by CPLD)
Bit 5: Not used (Write 0)
Bit 6: PLL clock pin (I2C bus)
Bit 7: PLL data pin (I2C bus 1 = Tristate (input) 0=0)
4 Not used
5 Not used
6 Not used
7 CPLD version ID (0x51)
4.4 FPGA
The RC200 board has a Xilinx Virtex-II FPGA (part: XC2V1000-4FG456C on RC200 and
XC2V3000-4FG676 on RC203). The device has direct connections to the following devices:
•CPLD
•ZBT RAM
•Ethernet
•Clock generator
•Video input
•Video DAC
•RGB to PAL/NTSC encoder
•Audio codec
•RS-232
•PS/2 connectors
•Expansion header
•2 seven-segment displays
•2 blue LEDs
•2 contact switches
•Bluetooth (if fitted)
•TFT Flat screen (if fitted)
•Touchscreen (if fitted)
Details of pin connections are given in the sections about these devices.
Ïrd using Handel-C, remember that the pins should be listedIf you are programming the boa
in reverse (descending) order.
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Installation and set-up
The FPGA also has access to the parallel port and to the SmartMedia Flash memory through the CPLD.
You can program the FPGA via the CPLD from the SmartMedia Flash memory, or from the parallel port.
4.4.1 FPGA operation modes
The RC200 FPGA has two modes of operation:
•normal operation: communicates with the SmartMedia and PLL and is a parallel port slave
•parallel port control operation: becomes parallel port master and drives all parallel port
signals
The operation mode is set by control line P9 on the CPLD. If P9 is high, the FPGA is in normal operation
mode. If P9 is low, the FPGA is in parallel port control operation mode.
The function of the other CPLD control lines changes, depending on whether P9 is high or low.
4.4.2 Programming the FPGA using the FTU2 program
Celoxica provides a File Transfer Utility program, FTU2, which simplifies the process of programming
the RC200 FPGA via the parallel port.
4.4.3 Programming the FPGA from the parallel port
To program the RC200 Virtex-II from the parallel port:
1. Check that the board is connected and powered by reading the CPLD version ID (CPLD
address value 7).
The board may not return the ID if the FPGA is controlling the parallel port. If this happens,
eject the SmartMedia card and press the Reset button.
2. Disable and clear the FPGA by asserting nPROG (CPLD address 3, bit 4). Leave nPROG
asserted.
3. Disable the SmartMedia state machine by asserting CPLD address 3, bit 3 and leave this
asserted during programming.
4. Wait at least 1mS.
5. Deassert nPROG.
6. Wait for nINIT (CPLD address 3, bit 2) to go high, showing that the FPGA has cleared its
memory. For timeouts this is 4uS per frame, giving a total of 4.9mS for the Virtex II
XC2V1000 on the RC200 and 13mS for the XC2V3000 on the RC203.
7. The entire BIT file without the header can now be transferred directly to address 0. The
CPLD times the nCS, nWR and CCLK signals such the FPGA may be programmed.
8. After programming the FPGA, you need to wait at least 100µS before accessing the CPLD.
Alternatively, wait 1µS and check that PnCS is high (i.e. that there is no access to the
parallel port).
If programming is successful, DONE (CPLD address 3, bit 0) will be high, lighting the DONE LED. The
SmartMedia state machine can then be re-enabled by setting the Disable SmartMedia state machine
signal low (address 3, bit 3). If there is an error during programming the FPGA will signal a CRC error by
lowering nINIT (unless the FPGA is accessing the CPLD).
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Installation and set-up
4.4.4 Programming the FPGA from SmartMedia
You can program the RC200 Virtex-II from BIT files loaded onto the SmartMedia device. The BIT files
can be in exactly the same format as if you were programming from the parallel port. There is no need to
change or remove the header.
To program the Virtex-II from page 1 on the SmartMedia Flash, use one of the following:
•Apply power to the board
•Press the Reset button on the board
•Insert the SmartMedia card whilst the board is switched on
4.4.5 Programming from a specific address in the SmartMedia:
1. Set a block address in the CPLD using Address 4 for the lower byte of the address and
Address 3 for the upper byte (only the lower 5 bits of this byte are used).
2. Read from Address 5.
These steps will cause the CPLD to read from the relevant address in the SmartMedia and write the data
to the FPGA. Data is written using following steps:
•CPLD sets up the FPGA for programming.
•CPLD reads the ID register of the code to find out if 4-word addresses are required.
•CPLD reads the page valid byte (512+5) to see if it is valid.
If the page valid byte is invalid it searches though the block checking the page valid byte
until it finds a page that is valid.
The first valid page is skipped (if programming from address zero this is the CIS page).
•Data is copied to the FPGA until the FPGA is DONE. Bad pages are skipped.
The CPLD automatically adds 16 clock cycles after DONE to complete programming. If the FPGA
signals an error during programming, the FPGA is reset and the CPLD waits until a new SmartMedia is
inserted.
It is assumed that if a single page is invalid then the entire block is invalid, and all the pages within the
block will have the block invalid byte set. The CPLD doesn't check the SmartMedia ECC (Error
Correcting Code) as the FPGA programming datastream has its own CRC (Cyclical Redundancy
Checking) which checks that the data stream is correct.
4.4.6 Reading data from the CPLD to the FPGA
To read data from the RC200/203 CPLD and write it to the FPGA:
1. Set up the address and tristate the data bus.
2. Wait at least 10ns.
3. Set nCS low.
4. Wait at least 10ns.
5. Set nRDWR low.
6. Wait at least 40ns before reading data.
7. Tristate nRDWR.
8. Set nCS high.
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