Colex Vme-80186 User manual

talEX

VME

80186

TECHNICAL

MANUAL

.

All information included in this manual,

is

subject to

AU

rights reserved.

VME-80186

COLEX

VME-S81S6

COLEX's

advanced

system

design

has

made

it

possible

to

bring

two

of

the

most

popular

system

concepts

of

the

80's

together

onto

one

board:

the

Intel

80186

16

bit

microprocessor

and

the

VMEbus.

By

expanding

the

memory

address

space

to

16

megabytes,

adding

address

modifiers,

and

providing

the

proper

timing

controls,

COLEX

has

made

the

VME-80186

compatible

to

the

VMEbus

standard

and

to

other

VMEbus

products

meeting

specification

Revision

B

or

later.

The

VME-80186

allows,

for

the

first

time,

the

use

of

the

popular

operating

,system

MSDOS

together

with

the

VMEbuL

The

8088/8086

has

the

widest

range

of

installations

among

all

16

bit

computers.

The

80186,

incorporates

full

8088/8086

upward

compatibility

while

compressing

40

chips

into

one

package.

The

result

is

a

wide

range

of

software

and

hardware

options

for

the

system

builder.

The

features

of

the

VME-80186

include:

Processor

Clock

speed

On-board

memory

Add-on

memory

Off-board

memory

Video

output

Serial

I/O

DMA

Printer

output

VMEbus

expansion

Mass

storage

Real

time

clock

MultiCpu

option

80186

CPU

13

MHz

l28kb

2 JEDEC

EPROM

sockets

128kb

Parity

for

all

256k

bytes

of

memory

16

megabytes

address

space

5

address

modifiers

Optional

video

controller

2

RS232

ports

with

25

connectors

High

speed

DMA

channel

Centronics

compatible,

25

connector

Full

VMEbus

interface,

slot

one

functions

Bus

master,

slave

and

controller

SASI

interface

to

floppy

and

hard

disks

with

alarm,

timer,

and

battery

backup

For

parallel

processing

HIGH

PERFORMANCE

APPLICATIONS

Applications

for

the

VME-80186

include

machine

tool

control,

communications

contra

llers

and

preprocessor

5,

small

busi

ness

computers,

process

control,

and

I/O

processor

for

multi-processor

systems.

The

VME-80186

is

compatible

with

VMEbus

products

from

dozens

of

vendors,

plus

other

COLEX

VMEbus

products

and

can

be

expanded

to

,use

AID

converters,

additional

mass

memory

devices,

direct

industrial

interfaces,

CMOS

RAM

modules,

graphics

display

controllers,

and

many

more.

I

128/256k

MEMORY

This

memory

consists

of

128k

bytes

located

on

the

main

board,

it

can

be

expanded

by

an

additional

128k

by,tes

by

using

the

XRAM

card.

Parity

logic

is

provided

by

the

XRAM

add-on

and

performs

parity

checking

on

both

the

main

board

memory

and

the

plug-on

memory.

Cycle

time

of

the

memory

averages

625ns.

Refresh

for

all

VME-80l86

memory

is

done

by

a

controller

on

the

VME-

80186

card.

The

m~mory

map

on

the

VME-80186

card

is

separated

into

5

working

segments.

Three

segments

perform

actual

memory

functions,

one

is

for

I/O

accesses

to

the

VMEbus,

the

last

is

to

allow

VMEbus

generated

vector

interrupts

to

be

read

by

the

80186

chip.

On-board

RAM

memory

Off-board

memory

Vector

interrupt

input

VMEbus

short

I/O

not

used

On-board

EPROM.memory

0-

256Kb

256-

768Kb

768-

800Kb

800-

832Kb

832-

960Kb

96@-l@24Kb

256Kb

5l2Kb

32Kb

128Kb

64Kb

This

mapping

is

programmable

by

the

80186

CPU

chip.

The

above

mapping

is

used

by

COLEX

in

standard

software.

X

RAM

The

XRAM

card

adds

l28Kb

memory

and

a

parity

controller

to

the

VME-8@186

by

way

of

3

connector

rows.

The

XRAM

card

is

simply

plugged

into

these

connector

rows,

only

one

orientation

is

possible.

The

memory

control

logic

automatically

uses

the

added-on

ram.

The

parity

controller

performs

parity

checking

and

generation

for

the

entire

256k

ram.

If

an

error

is

detected,

a

BERR/

signal

will

be

generated

•.

This

will

cause

a 'NON MASKABLE

INTERRUPT'

to

the

813186

if

the

VME-8@186

NMI

enable

bit

is

set.

2

SERIAL PORTS

Serial

I/O

is

possible

via

the

2

ports

on

the

card.

P4

is

connected

as

a

DCE

for

direct

connection

to

a

terminal,

P3

is

wired

as

DTE

for

direct

connection

to

a

modem,

or

to

another

computer.

Each

port

has

its

own

baud

rate

generator

connected

to

a

3.6864

MHz

crystal

oscillator.

All

common

baud

rates

may

be

used.

Multiple

protocols

are

supported,

including

ASYNC,

BYSYNC,

HDLC,

and

SDLe

at

speeds

up

to

I

megabaud.

The

channels

can

also

be

programmed

for

PM,

NRZI,

and

BIPHASE

encoding

and

decoding.

Both

serial

ports

are

interfaced

via

25

plugs

on

the

front

panel

of

the

card.

The

serial

I/O

controller

chip

used

is

the

ZILOG SCC

8530,

full

programming

details

can

be

found.

in

the

ZILOG

see

programming

manual,

a

brief

summary

is

provided

at

the

end

of

this

document.

The

DTE

port

(See

channel

A)

can

be

programmed

for

internal

or

external

clocks,

and

internal

or

external

sync

by

the

following

jumpers:

Jl

selects

external

sync

from

P3

15

J2

selects

the

internal

baud

rate

generator

from

channel

B

J3

enables

the

internally

generated

sync

to

P3

15

Jl

and

J3

should

not

be

inserted

at

the

same

time.

P3

17

is

connected

to

the

SCC

/TRxCA

input

allowing

this

to

be

used

as

a

clock

input.

with

J2

installed,

the

on-board

baud

rate

generator

is

connected

to

both

the

/RTxeA

input

and

to

P3

14

for

the

clock

output.

sec

PROGRAttMING

While

the

Zilog

technical

manual

is

the

best

source

of

information

on

the

SCC

chip

used

on

the

89186

for

all

serial

I/O,

the

following

quick

summary

of

common

programming

options

can

save

the

user

time.

1)

Baud

rate

selection

The

source

of

the

baud

rate

clock

is

a

3.6864

MHz

crystal

on

channel

B

from

RTXCB

to

SYNCB.

Register

11

should

be

programmed

as

fo1:1ows

to

use

this

crystal:

channel

A:

56h

channel

B:

D4h

This

enables

the

2,

16

bit

divide

counters

to

provide

a

baud

rate

to

the

A

and

B

channels.

Both

transmit

and

receive

rates

will

be

the

same.

Register

14

should

be

programmed

with

a

9lh.

3

sec

Programming

continued

2)

Baud

rate

speed

To

calculate

the

correct

divide

count

for

each

channel,

use

the

following

formula:

(BR =

required

baud

rate)

=

115200

-2

BR

Example:

115200

-2

=

10

9600

for

9600

baud

This

is

programmed

into

register

12/13,

register

13

is

the

MSB.

,3)

Data

parameters

Registers

3,4

and

5

determine

the

parameters

used

in

the

character

data.

For

n6rmal

operation

(~

data

bits,

no

parity,

1

stop

bit,

ASYNC,

DTR

and

RTS

active)

the

following

codes

are

used~

~

register

3

4

5

content

Clh

44h

EAh

4)

General

parameters

To

reset

the

chip,

tbe

following

data

should

be

written

first:

register

data

channel

A: 9

80h

9

00b

15

00h

channel

B:

9

40h

9·

00b

15

00h

5)

Summary

The

byte

strings

to

be

outputted

to

the

SCC

for

9600

baud

operation

on

both

channel

s

would

be:

(a

11

data

hex)

A:

09/80/09/00/03/Cl/04/44/05/EA/0B/56/0C/0A/0D/00/0E/01/0F/00

B:

09/40/09/00/03/Cl/04/44/05/EA/0B/D4/0C/0A/00/00/0E/0l/0F/00

The

first

byte

is

the

register,

the

second

is

the

data.

4

SCC

Programming

continued

6)

Interrupts

The

SCC

chip

cannot

generate

interrupts

to

the

80186.

7)

Reading

status

The

sec

can

be

polled

for

data

ready

or

transmitter

empty

by

testing

the

listed

bit.

receive

ready

transmit

ready

=

bit

0

=

bit

2

CENTRONICS INTERFACE

For

connection

to

a

printer,

a

Centronics-compatible

interface

is

provided.

The

interface

is

made

via

PS,

a

25

connector

on

the

front"of

the

card.

This

connector

matches

the

lower

25

pins

of

the

standard

36

Centronics

connector

for

ease

of

cable

construction.

When

outputting

to

the

printer,

the

BUSY

and

PE

(paper

empty)

signals

should

be

tested,

both

must

be

low

before

data

can

be

sent.

After

data

is

outputted

to

the

printer

data

port,

the

strobe

should

be

pulsed

low

for

at

least

10

us

(exact

duration

depends

on

the

printer

used).

5

VMEbus

INTERFACE-

slot

1

functions

The

VME-SOlS6

functions

as

system

controller

in

a

VMEbus

system.

This

allows

other

cards

to

be

plugged

in~o

the

bus,

using'the

arbitration

logic

of

the

VME-80l86

to

allow

data

to

be

exchanged

between

any

two

cards

on

the

bus.

These

'slot

one'

functions

include:

a

16

MHz

bus

clock;

a

single-

level

arbiter

of

bus

requests

by

the

on-board

80186

or

any

other

card;

and

processing

of

BERR,

ACFAIL,

SYSFAIL,

INT,

and

NMI

requests.

In

the

arbitration

process,

interrupt'

requests

have

priority

over

bus

requests.

The

80186

LOCK

function

(used

typically

for

bit

test

and

set)"

is

handled

as

a

uninterruptable

cycle,

allowing

orderly

interprocessor

communication.

Interrupt

levels

1

and

3

are

supported

from

the

bus,

bus

supplied

interrupt

vectors

can

be

read

by

the

80186

in

arder

to

form

a

VMEb~s

compatible

interrupt

acknowledge

cycle.

Other

boards

may

exchange

data

on

the

VMEbus

without

affecting

the

through~ut

of

the

80186

cpu.

VMEbus

Memory

addressing

The

80186

chip

normally

can'

address

only

I

megabyte

of

memory.

The

C6lex

design

adds

address

modifiers

and

extra

memory

address

bits

to

allow

the

full

use

of

the

VMEbus

16

megabyte

memory

space,

with

minimal

overhead

on

the

part

of

the

programmer.

Two

programmable

register

files

added

to

the

80186

address

outputs

allow

it

to

address

supervisor

and

user

memory

spaces,

normal

and

short

t/O,

separate

program/data

memory

areas,

and

other

user

defined

address

modifiers.

The

4

register

files

(4

byte

dual

port

memories)

allow

the

80186

address

range

of

256-768Kb

to

be

mapped

to

any

512kb

block

of

memory

in

the

VMEbus

memory

and

address

modifier

map.

This

allows

4

types

of

operations

(DMA

I/O,

DMA

~emory,

CPU

I/O

and

CPU

memory)

to

be

automatically

correctly

mapped

to

the

bus,

depending

on

the

cycle

being

executed,

without

any

output

instruction

to

the

register

files.

The

type

of

address

modifiers

defined

in

the

Rev.

B

VMEbus

spec

which

are

supported

by

the

VME-80186

card

are

shown

below.

The

left

colu~n

represents

the

address

modifier

to

be

selected

from

the

register

file.

The

right

column

is

the

data

which

must

be

programmed

into

the

file

to

generate

the

address

modifier

in

the

left

column.

Note

that

AM4

is

not

generated-by

the

register

file

(see

6

VMEbus memory

addressing

-

continued

bi

ts

bits

VMEbus

address

modifier

5 4 3 2 I

~

register

file

2 1

0'

Supervisor

program

1 1 1 1 1 0 I

0'

1

Supervisor

data

1 I 1 I 0 I

0'

1 1

Supervisor

short

I/O

1 0 1 1 0 1

0'

I 1

User

program

1 I I 0 I

0'

1

0' 0'

User

data

1 1 1 0 0 1 0 I

0'

User

short

I/O

I 0 1 0 0 1 0 I 0

Register

file

codes

for

common

address

modifiers

Additionally,

any

of

the

'undefined'

codes

fitting

the

model

'lxlxxx'

may

be

generated

for

customized

applications,

where

'x'

is

either

a 0

or

1.

The

register

file

contents

are

programmable

from

the

CPU

by

outputing

the

pattern

required

to

the

a"ppropriate

port.

With

an

output

instruction,

the

CPU

must

write

all

8

bits

of

data

to

one

of

the

4

register

file

ports.

Every

subsequent

VMEbus

transfer

will

use

the

data

stored

in

the

appropriate

register

file

to

extend

the

80'186

addressing

to

the

full

VMEbus

space.

The

data

byte

written

to

the

register

file

(bits

o

to

7)

are

sent

to

the

bus

as

5

address

bits

(A19

to

A23)

and

3

Address

Modifier

bits.

As

can

be

seen

from

the

following

table,

the

address

and

address

modifier

data

bits

must

be

merged

by

the

program

to

generate

the

proper

pattern.

Address

modifier

register

files

AM5

AM4 AM3

AM2

AMI

AM0

A23 A22 A21

1 x 1

b0 b2

bi

b7 b6

b5

Note

that

'b0'

to

'b7'

represent

the

bi

ts

in

the

accumulator

of

the

80186

CPU.

Also

note

that

AM4

is

not

directly

programmable

from

the

register

file.

Instead,

this

bit

is

driven

by a

memory

select

decode

line

from

the

80186

chip.

This means

it

is

low

when

memory

addresses

are

in

the

range

of

76Bk

to

832K,

otherwise

it

is

high.

AM5

is

always

driven

high

during

VME-80I86

VMEbus

accesses

in

order

to

disable

the

unused

32

bit

transfer

mode

of

the

bus.

AM3

is

always

driven

high,

as

the

functions

performed by

this

bit

when

low

are

not

defined

by

the

VMEbus

specification.

7

A20

A19

b4 b3

VMftJus msoory

addressing

-

continued

The

4

register

files

are

loaded by 80186

local

output

instructions

to

the

appropriate

I/O

port.

The

I/O

port

addresses

and

their

functions

are:

Port

Enabled

during

200

CPU

short

I/O

address,

DMA

I/O

source

address

202

DMA

I/O

destination

address

204

CPU

memory

address,

DMA

memory

source

address

206

DMA

memory

destination

address

Which

of

the

4

register

files

are

enabled

as

address

modifiers

and

upper

address

bits

during

a

VMEbus

transfer

is

determined

by 2

functions:

a) Second

cycle

in

a

DMA

transfer

(destination)

b)

Short

I/O

request

( 80186

local

address

between 768k and 832k )

This

approach

allows

DMA

transfers

to

be

programmed

between

blocks

of

VMEbus

memory

which

are

separated

by more

than

S12k

bytes.

This

is

done by

programming

the

source

and

destination

register

files

with

different

memory

contents.

The scheme

also

allows

the

short

I/O

addresses

of

the

VMEbus

to

be

accessed

by

the

CPU

independently

of

the

memory

mode

(supervisor/user,

data/program)

selected.

By·

separating

the

source

and

destination

address

modifiers

and

upper

address

bits,

the

80186

DMA

channel

chip

has

full

power

to

move

data

anywhere,

far

beyond

the

usual

80186

chip

addressing

limitations.

Interrupt

acknowledge

cycle

After

the

CPU

receives

an

interrupt

on

inputs

1

or

3 from

the

VMEhus,

it

can

read

in

the

vector·from

the

interrupting

device

by

the

following

sequence:

Read

memory

address

c0003H

·if

interrupt

level

1

vector

is

to

be

read

Read

memory

address

c0007H

if

interrupt

level

3

vector

is

to

be

read

8

8'1186 VMIbls

byte

DDde

canpatibility

Addresses

from

Al

to

A18

are

provided

directly

by

the

80186

chip

to

the

VMEbus. The 80'186

BHE

and

A0'

lines

are

translated

into

VMEbus

consistent

upper and lower

data

strobes.

Long

word

transfers

are

not

supported

by

the

VME-80186.

The

COLEX

VME-80'186

card

correctly

manages

the

different

methods

the

80'186

chip

and

VMEbus

chip

use

to

define

the

high

and low

bytes

of

a

16

bit

word.

00'

to

07

of

the

80'186

chip

is

connected

to

08

to

015 on

the

VMEbus.

Likewise,

08-015

is

connected

to

00'-07.

Internal

connections

are

not

affected

by

the

'swap'

of

these

data

lines.

(All I/O

on

the

VME-80'186

card

is

accessable

by

the

80'186

only.)

with

this

translation,

a 16

bit

word

written

into

memory

by

a 68000

with

be

correctly

read

by

the

80'186.

without

this

swap,

word

transfers

would

be

incompatible.

Logic

on "the VME-80186

card

also

assures

that

Byte

transfers

on

the

VMEbus

are

also

completely

canpatible.

Internal

Processor

IIBIDry

organization

data

=

1234H

680'0'0

address

1-23 000000 12 I

34

address

bit

A0

0 1

00000

80186

34

I

12

o 1

The

above

example

shows how

the

2

CPU

chips

store

the

hexidecimal

word

'1234·

in

memory. The

swap

built

into

the

VME-80186

allows

all

data

interchange

between

CPU·s

to

be

programmer

transparent.

The 80186

programmer should

not

write

words

on

odd

memory

addresses

if

the

68000

is

to

correctly

read

this

data,

since

the

68000

chip

itself

cannot

support

this

feature.

9

89186

chip

initialization

The

internal

registers

of

the

80'186

require

initialization

on power-on

for

correct

operation

of

the

chip

and

the

VMEbus

interface

described

in

this

specification.

The

complete

list

of

registers

and

the

data

required

is

listed

below:

name

address

data

function

control

block

defaults

to

0'FF0'0H

after

reset

upper

chip

select

0FFA0H

0F0'38H

EPROM

at

last

64K

bytes

no

wait

states

external

ready

lower

chip

select

0FFA2H

03FF8H

RAM

at

0'

to

256K

external

ready

peripheral

select

0'FFA4H

@@E3BH

I/O

base

address

at

E0'0'0',

3

wait

states

for

pes

0--3

midrange

chip

select

0FFA6H

0CIFBH

Interrupt

acknowledge

cycle

via

access

to

768k -

80'0'k

short

I/O

via

80'ek

-832k

3

wait

states

and

ready

MPCS

0'FFA8H

0'90'BBH

7

I/O

chip

selects,

not

memory

mapped I/O

3

wait

states

for

pes

4-6

4 x

32k

byte

segments

Timer

am

DMA

registers

are

not

listed,

these

do

not

affect

basic

operation

of

the

board.

The

INTEL

80'186

chip

manual

should

be

referred

to

for

more

detail.

AlDRESS

POlIFIER

INITIALIZATION

The

address

modifiers

are

initialized

to

allow

the

80'186

address

space

in

the

range

of

256k-768k

to

access

the

VMEbus

memory

from

13

to

SI2k.

Also,

the

short

I/O

space

is

set

up.

PORT

DATA

FUNCTION

0'E200'

0'3

Short

I/O

space

0E202

0'3

Short

I/O

space

·0E2@4

0'5

Supervisor

space,

address

0'

0E20'6

0'5

Supervisor

space,

address

0

10

GmERAt

PORPOSE

I/O

P6

is

a 9

connector

on

the

front

panel

which

may

be used

for

connection

of

the

VME-80186

card

to

external

signals.

On

the

connector

,are

2

of

the

3

counter/timers

of

the

80186 and 5

single

bi

t

TTL

compatible

inputs.

In

addition,

P2

contains

one

interrupt

input,

a

TTL

input,

and a

TTL

output

bit

for

custom

applications.

SASI

IN'I'ERF1\CE

For

interfacing

the

80186

card

to

floppy

disks,

hard

disks,

cartridge

tapes

and

other

mass

storage

devices,

the

VME-80186

includes

a

DMA

controlled

SASI

port

via

the

board's

P2

connector.

Necessary

control

of

hard

disk

error

management

is

included

to

interrupt

and

stop

DMA

transfers

should a

disk

error

occur.

The VME-80186

does

not

latch

the

SASI

data

in

either

direction,

instead

the

SASI

interface

is

provided

with

await

generator

to

assure

that

the

SASI

device

has

transferred

the

data

before

the

80186

processor

is

allowed

to

continue.

Since

an I/O

cycle

to

the

SASI

port

will

normally

not

be

started

until

the

SASI

device

has

issued

a

request,

no

timeout

is

required.

Jll

controls

whether

or

not

wait

states

are

generated

by

the

hardware

during

the

select

sequence.

with

Jll

installed,

the

interface

adheres

to

the

SASI

bus

specifications.

If

a

SASI

controller

is

used

(for

example

XEBEC

1410)

which

will

respond

with

BUSY

is

less

than

800

ns

(the

maximum 80186

built-in

wait

state

timeout),

then

Jll

may

be

removed.

This

allows

automatic

system

configuration

software

to

sense

and

check

the

presence

of

a

variable

number

of

connected

controller

devices.

The

design

of

the

VME-80186

allows

multiple

cards

to

share

the

same SMI

interface

bus.

This

allows

direct

disk

to

memory

transfers

without

using

the

VMEbus

in

mul

ticpu

applications.

This

can

significantly

improve

the

system's

throughput.

The

SASI

bus can

support

a wide range

of

peripherals,

including

floppy

disks,

hard

disks,

tape

drives

and

future

storage

media

including

laser

disks.

OOLEX

considers

the

SASI

interface

combined

with

the

DMA

of

the

80186

to

be

the

optimal

method

of

system/drive

interface.

Direct

Meul>ry

Access

transfers

The VME-80l86

includes

two

DMA

channels.

One

is

dedicated

for

fast,

transparent

transfers

of

data

between

the

SASI

interface

port

and memory.

Even

with

'the

fastest

SASI

devices,

the

processor

still

is

operating

at

50%

throughput.

When

compared

to

typical

programmed

data

tra~sfers,

the

VME-

80'186

card

will

transfer

data

up

to

10

times

faster

than

non-dma

applications.

Also,

having

the

memory on

the

came

card

as

the

SASI

port

saves

bus

accesses,

reSUlting

in

far

faster

system

operation.

The

second

DMA

channel

is

free

for

use

in

memory-memory

or

memory-VMEbus

short

I/O

transfers.

Note

that

if

both

DMA

channels

are

used

at

the

same

time

with

the

VMEbus,

that

the

same

512Kb

block

will

be

used (same

register

file)

•

11

A

sepa)::ate

source

and

destination

register

Jile

is

provided

to

allow

transfers

on

the

VMEbus

between

different

5l2Kb

blocks.

The

source

register

used

will

be

the

same

as

that

used

for

CPO

VMEbus

accesses,

the

destination

register

is

unique

to

the

DMA.

The

card

allows

the

DMA

to

be

used

with

short

I/O

ports

on

the

bus.

Separate

register

files

are

provided

for

this

operation

mode.

The

VME-80186

card

contains

socket~

for

2

EPROM

devices

of

up

to

32Kb

each.

The 80816

chips

is

programmable

for

the

number

of

wait

states

required

to

allow

for

access

times

of

a

wide

range

of

EPROM

devices.

The

EPROMs

are

accessible

only

by

the

on-board

80186,

not

by

the

VMEbus.

Jumper

J6

allows

the

type

of

EPROM

used

to

be

selected.

Both

EPROMs

must

use

the

same jumper

connection.

cro

Al3

nlc

cro Al4

prom

type

2732

2764

27128

27256

J6

1.

.2

socket

26

3.

.4

+5

volts

5.

.6

socket

27

jumpers

2-4

1-2

1-2,

5-6

REAL

TIME

CLOCK

A

battery

backed-up

real

time

calendar

clock

chip

maintains

current

time

with

a 99

year

calendar

even

during

power-off

conditions.

Additionally,

a

timer

interrupt

output

is

available

on

P2

6c

for

custom

applications.

The

programming

of

the

M3000

chip

is

summar

ized

in

attached

application

note.

More

details

can

be

found

in

the

M3000

data

sheet

from

MEM

Microelectronic-Marin,

Switzerland.

The

chip

is

organized

as

16

byte

registers,

each

accessable

via

2, 4

bit

(nibble)

data

transfers.

The M3000

provides

a

real

time

clock,

alarm

and

timer

function.

Only

the

real

time

clock

is

typically

used

in

the

VME-80186,

thus

the

7

bytes

used

by

the

timer

and

alarm

can

be

used

as

non-volatile

ram

instead.

The

clock

is

updated

each

second,

and

the

update

lasts

6 ms.

The

M3000

cannot

be

read

during

these

updates

since

the

data

is

changing,

hence

the

busy

signal

should

be

checked

before

reading

the

clock.

Once a

I/O

cycle

by

the

80186

has

been

started,

the

M3000

will

not

start

an

update

until

after

the

cycle

is

completed.

Each

cycle

consists

of

4

nibble

transfers.

Busy.

can

be

detected

by

reading

bi

t 8

of

port

l80H. The

chip

is

busy

when

this

bi

t

is

low.

One

of

16

addresses

can

be

selectea,

and

the

data

can

be

read

or

written

via

bit

0 - 3

of

the

I/O

port

l00H.

12

MSDOS

SOFlWARE

SUPPORT

A

preinstalled

MSOOS

operating

system

is

available

to

use

the

VME-80l86

in

a floppy

or

hard

disk

environment.

This

system

allows

program development

directly

on

the

COLEX

VME-80l86

card,

with

assembly and

compilation

times

roughly 4

times

faster

that

the

IBM

personal

computer.

The

MSDOS

software

package can

be

purchased

for

use

with

the

VME-80l86

in

constructing

a

user

assembled system. A

turnkey

complete packaged computer

may

also

be

purchased

from

COLEX

including

10

Mb

winchester

hard

disk,

floppy

backup,

3

slot

VMEbus

backplane

and power

supply

in

an

attractive

case.

BUilt-in

fiDmWare

COLEX

ships

the

VME-:80186

with

a

buil

t-

in

program

debugger

to

assist

in

testing

of

user"

generated

programs,

especially

in

applications

usi~g

customer

written

software.

The

features

of

the

debugger

include:

Breakpoints

set,

clear

2

breakpoints

Dump

memory

in

Intel

fonnat

to

the

DTE

port

Execute program

Fill

memory

area

Hexidecimal

calculations

Locrl

Intel

fonnat

fran

DTE

port

Memory"display, update

Offset,

set

relative

start

address

Port

display,

update

Trace program

in

memory,

display

registers

and

status

eXamine and update

register

contents

Y

turnsthedebugger

into

a

terminal

via

the

DTE"port

13

I/O

MAP

The

I/O

ports

of

the

VME-80l86

card

are

defined

in

the

following

table.

The

I/O

ports

of

the

VME-80l86

are

only

accessible

by

the

on-board 80186.

All

signals

are

active

high

unless

preceded by a

'/'.

The

polarity

matches

the

signals

'shown

in

the

connector

pinout

table.

For

example,

the

/STROBE

output

to

the

printer

will

go

low

when

the

port

192

is

written

with

bit

0

low.

I/O Address

TYPE

FUNcrION

E000

RD/WR

SASI

DATA

PORT

Serial

I/O

ports

A and B

E080

RD/WR

sec

COMMAND

CHANNEL

B

E082

RD/WR

sex::

DATA

OiANNEL

B

E084

RD/WR

sec

COMMAND

CHANNEL

A

E086

RD/WR

sec

DATA

CIiAL.~EL

A

E100

RD/WR

Real

Time

Clock

(R'IC)

ElS0

RD

TTL

input

port

BIT

number

Function

0

P6

X

data

1

P6

Y

data

2

P6

M

data

3

P6

D

data

4

P6

G

data

5

Printer

busy

6

Printer

paper

anpty

7

/SYSFAIL

8 Real

time

clock

busy

9 Colex

use

only

10

Colex

use

only

11

/ACFAIL

12

TTL

input

bit

P2

7c

E180

WR

not

used

E190

lID

SASI

status

port

BIT

function

0

/RQ

request

1

/MSG

message

2

/BUSY

busy

3

/1/0

Input

/ Output

status

14

I/O Address

TYPE

FUNCTION

E190-7

WR

Control

ports

(only

bit

0

is

used)

E190

WR

TI'l

output

connector

P2

5c

'·E192

WR

not

used

El94

WR

/STROBE

to

printer,

active

low

El96

WR

NMI

enable

when

high

El98

WR

SASI

RST

reset,

active

high

El9A

WR

SASI

SEL

select,

active

high

E19C

WR

'FAIL'

output

to

VMEbus,

active

high

El9E

WR

/LED

status

LED

display,

on

when

low

E200

register

files:

Al9

to

A23,

plus

address

modifier

E200

WR

I/O

source

E202

WR

I/O

DMA

destination

E204

WR

Manory

source

E206

WR

Memory

DMA

destination

E280

WR

Printer

data

port

81816

chip

PCS

progrcmming

The 80186 Programmable Chip

Select

(PCS)

lines

are

programmed

to

provide

the

following

addresses

for

on-board I/O.

The

above

addresses

assume

the

following

programming

is

used.

PCS

0'

1

2

3

DISPLACEMENT

.0

80H

100H

l80H

PCS

4

5

6

81186

INTERROPrS'

DISPLACEMENT

200H

280H

300H

.

not

used

The 80186

has

5

interrupt

inputs.

They

are

used

on·

the

VME-80186

card

as

follows:

int0

VMEbus

interrupt

line

3

intI

P2

6a

int2

VMEbus

interrupt

line

1

int3

SAS!

interface

int4

ACFAIL,

BERR,

Parity

error

8n86

TIMER

amrrERS

The

80186

chip

has

3

counter/timer

channels.

The

2

full

counter/timers

are

connected

to

2

of

the

7

input

bits

from

P6.

The'third

timer

channel

is

used

as

a I

ms

clock

input

in

the

COLEX

debugger and

MSDOS.

It

is

available

for

use

in

non

MSDOS

applications.

timer

0

timer

1 p6

input

'X

interrupt'

P6

input

'y

interrupt'

15

VMfbJs

signal

description

The

signals

used by

the

VME-80186

are:

/ACFAIL

input

/IACKIN

input

/IACKOUT

output

Am0-AM5

output

/AS I/O

A01-A23

I/O

/BBSY

output

/BCLR

output

/BERR

I/O

/BG30UT

output

/BGxIN

input

/BR3

input

output

/DS0

I/O

/OSl

I/O

/OTACK

I/O

000'-015

I/O

/IACK

output

/IRQl

/IRQ3

/LWORD

input

/SYSFAIL

I/O

/SYSRESET

input

/WRITE

I/O

/SYSCLK

output

indicates

that

the

power

5upply

is

going

to

fail

not

used by

slot

1

cards

TS

same

as

/IACK

(slot

1)

TS

driven

during

bus

cycles

only

TS

address

strobe

TS

addresses

OC

driven

during

bus

cycles

TS

driven

when

VME-80186

wants

bus

OC

driven

by

parity

error

during

slave

cycles

driven

by

bus

timeout

logic

for

all

cycles

TS

acknowledge bus

to

requester

not

used

by

slot

1

starts

bus

arbitration

OC

driven

low

when

the

80186

starts

a

bus

access

TS

low

data

byte

transfer

TS

high

data

byte

transfer

TS

acknowledges end

of

cycle

TS

data

bits

TS

active

when

memory

location

c0000-c000'7

is

addressed

request

interrupt

level

I

request

interrupt

level

3

disables

accesses

to

VME-80l86

OC

driven

by

'FAIL'

bit

from 80186

readable

by 80186 cpu

TTL

input

resets

the

card

when

low

TS

indicates

write

cycle

on

bus

16

MHz

bus

clock

16

VHEbls

cormector

PI

.

row a row b row c

- - --

1 000

BBSY/

008

2

D01

OCLR/

009

3 002

ACFAIL/

D10

4 003 011

5 004 012

6

D05

013

7 006

D14

8

007

015

9 Ground Ground

10

SYSCLK

SYSFAIL/

11 Ground

BG30UT/

BERR/

12

OS

1/

SYSRESET/

.

l3

OS

0/

LWORD/

14

WRITE/

AMS

15 Ground BR3/

A23

16

DTACK!

AM0

A22

17

Ground

AM0

A21

18

AS/

AM0

A20

19

Ground

AM0

A19

20

lACK!

Ground

A18

21

A17

22

IACKOUT/

A16

23

AM4

. Ground

A15

24

A07

IRQ7/

A14

25

MJ6

IRQ7/ Al3

26

A05

IRQ7/

A12

27

A04

IRQ7/

All

28

A03

IRQ7/

A10

29

A02

IRQ7/

A09

30

A01

IRQ7/

A08

31

-12V

+5V

Standby

+12V

32

+SV +SV +SV

Signals

not

listed

are

not

used

by

the

VME-80186

card.

17

Colex VME-80186 User manual

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