Control Data 3300 User manual

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COMPUTER SYSTEM
REFERENCE MANUAL
CONTROL DATA
CORPORATION

3300 CHARACTERISTICS
• Stored-program, solid-state, scientific and business data processing computer
• Time-sharing and multiprogramming features
• Parallel mode of operation
• Diode logic
• Character and word addressing (4 characters per word)
• Address modification (indexing)
• Indirect addressing
• 28-bit storage word (24 data bits and 4 parity bits)
• Nonvolatile magnetic core storage
• Complete cycle time: 1.25 microseconds
• Access time: O. 75 microsecond
• Storage sharing
• Selected storage protection
• Instruction repertoire compatible with the 3100, 3200, and 3500 Computers
• Business oriented Moves, Searches, Edit, Compare, Conversion, and BCD
arithmetic instructions
• Logical and sensing operations
• Masked storage searches
• Block control operations
• Trapped instruction processing
• 24- bit accumulator register and auxiliary accumulator register
• Binary arithmetic: 2221:-1 modulus, one's complement for all single pre-
cision (24-bit) operations and double precision (48-bit) addition and subtrac-
tion
• 64-word register file (0.5 microsecond cycle time)
• Complete interrupt system
• ASCII to BCD conversion (and vice versa) and 4-bit/6-bit packing
• Real-time clock (1.0 millisecond incrementation) ,
•
Sit- down operator's console featuring: On-line typewriter and complete
display and control system
• Upward compatability with 3100 and 3200 computer systems
• Standard 3000 Series type 12- bit bidirectional data channel
• Compatible r/o mediums include magnetic tape, disk file, punched cards,
paper tape, and printed forms
• Options include:
• Memory expansion to 262,144 words (over 1 million characters)
• Additional 12-bit data channels or high-speed 24-bit data channels
• Floating point and 48-bit precision multiply and divide hardware logic
• Multiprogramming hardware module
• Business Data Processor
• Complete selection of advanced peripheral equipment

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COM PUTER SYSTEM
REFERENCE MANUAL
CONTROL DATA
I
CORPORATION

REVISION
01 (11-16-65)
A (5-13-66)
B
(9-12-66)
C
(2-23-67)
D
(6-14-67)
E
(6-14-67)
F
(
6-14-67)
G (10-2-67)
H
(4-4-68)
RECORD
of REVISIONS
NOTES
Original printing.
. Publications Change Order CA13641. Complete revision.
All previous editions obsolete.
Publication Change Order 14387, no Product Designation change.
The following pages were
revised or added:
iii"
v,
vii,
1-3,
1-13, 1-14, 2-4, 2-5,
3-1 through 3-8,
4-3, 4-5, 4-8, 4-9,
5-2, 5-7,
5-12, 5-13, 5-16, 5-18, 5-21,
5-22, 5-30,
5-41, 5-42, 5-68, 5-69,
5-73,
5-75, 5-76,
5-79, 5-80,
5-82, 5-95.0, 5-95.1, 5-96.0, 5-96.1, 5-98 through 5-103, 5-105,
5-106, 5-114
through 5-123, 5-129 through 5-137,
5-140 through 5-147, 5-149, 5-151,
5-153, 5-154, 5-155,
C-7, E-10 through E-13, Instruction Tables 6,
7,
8,
11, 12,
13, 14, 16, 17, 18. 19, 22,
24,
25,
and 30,
Index-I,
Index-2 and Index-3.
---
Publication Change Order 15865,
no Product Dp"iS",a.Llon change. The following pages were
revised or added:
iv, v,
1-1,
1-10, 1-13, 1-14, 2-6, 3-3,
3-5,
3-6, 4-2, 4-3, 4-4, 4-5, 4-6,
4-7,
4-8, 4-9, 4-10,
4-11,
5-26, 5-68, 5-69, 5-84, 5-87,
5-89, 5-91, 5-92, 5-94, 5-112, 5-116,
5-117, 5-122, 5-144,
5-147, 5-149, 5-151, 5-155,
Section 6, A-3,
A-4, F-7,
Index-I, Index-2,
and Index- 3.
Engineering/Publications Change Order 16076.
The foUowil!K2ages were revised or adde'd:
v,
2-5, 2-6, 2-7, 2-8, 2-9 and 5-81.
Field Change Order 16164,
new Product Designation 3312-A12.
The following pages were revised
or added:
5-18, 5-21, 5-82,
5-82.0, D-I0,
Instruction Tables 8 and 22.
Publications Change Order 16626, no Product Designation chaI!ge.
The following pages were
revised or added:
iii
v
1-8 2-1 2-5
2-6
3-6,
3-7
4-4, 4-11, 4-12,
5-3, 5-12, 5-13,
5-16,
5-17 5-20 5-21 5-22 5-25, 5-28, 5-32, 5-33,
5-40,
5-112, 5-113,
C-9, D-5, D-6, D-9,
D-I0,
F-7
Instruction Tables 10 11 12 13 19
21 27
28 and Index-3.
Publication Change Order 17622.
Page 5-155 revised and page 5-156 added.
Publication Change Order 19253, no Product Designation change.
Pages iii, 1-13, 1-14, 1-15,2-6,
4-6,5-1~5-127,5-147,5-155,C-11,C-12,C-13,
Instruction Tables 2, 14, 16 and 26 revised.
Address comments concerning this
manual to:
Pub No. 60157000
© 1966, 1967,1968
Control Data Corporation
Technical Publications Department
4201 North LeXington Avenue
St. Paul, Minnesota 55112
by Control Data Corporation
Printed in United States of America
or use Comment Sheet in the back of
this manual.
I
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1. General Systems Description
Introduction
Computer Modularity
Central Processing Unit
Storage Modules
Input/Output Modules
Floating Point Module
Multiprogramming Module
Business Data Processor
Operator's Console
Power Control Panel
Internal Organization
Central Processing Unit
Peripheral Equipment
2. Storage System
General Information
Storage Modules
Storage Registers
Storage Word
Character Modes
Single - Character Mode
Double - Character Mode
Triple - Character Mode
Full - Word Mode
Address Mode
Addressing
Multiprogramming and Relocation
Storage Protection
Permanent Protection
Selective Protection
Program Protection
No Protection
Storage Sharing
3. Input/Output System
General Information
Interface Signals
3306 and 3307 Communication
Channels
I/O Parity
Parity
Checking with 3306
Parity Checking with 3307
Transmission Rates
Input/Output Relocation
Auto Load/Auto Dump
CONTENTS
1-1
1-2
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1- 5
1- 5
1-14
2-1
2-1
2-1
2-4
2-4
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-6
2-6
2-9
2-9
2- 9
3-1
3-3
3-4
3-4
3-4
3-5
3-6
3-7
3-7
4. Interrupt System
General Information
Interrupt Conditions
Internal Condition Interrupts
Input/Output Interrupts
Executive Interrupt
Storage Parity Error Interrupt
Illegal Write Interrupt
Trapped Instruction Interrupts
Power Failure Interrupt
Interrupt
Control
Enabling or Disabling Interrupt
Control
Interrupt Priority
Sensing Interrupts
Clearing Interrupts
Interrupt Processing
Interrupt Mask Register
Interrupts During Executive Mode
5. Instructions
General Information
Instruction Parameters
Instruction Word Formats
Word Addressing vs. Character
Addressing
Indexing and Address Modifica-
tion
Addressing Modes
Indexing and Indirect Address-
ing Examples
Trapped Instructions
Instruction List
No-Operation Instructions
Instruction Execution Times
Halt and Stop Instructions
Enter Instructions
Increase Instructions
Skip Instructions
Inter- Register Transfer
Instructions
Jump Instructions
Load Instructions
Store Instructions
Shift and Scale Instructions
Arithmetic Instructions
Logical Instructions
Masked Search and Compare
Instructions
Condition Test Instructions
Sensing Instructions
Pause Instructions
Interrupt Instructions
Input/Output Instructions
Relocation Control Instructions
4-1
4-2
4-2
4-3
4-3
4-4
4-4
4-5
4-6
4-7
4-7
4-7
4-8
4-8
4-8
4-9
4-11
5-1
5-1
5-4
5- 5
5-6
5-7
5-9
5-11
5-11
5-18
5-19
5-24
5-25
5-27
5-28
5-32
5-41
5-49
5- 53
5-57
5-60
5-70
5-75
5-81
5-83
5- 87
5-89
5-92
5-112
iii
Rev. F

Instructions (Cont'd)
Multiprocessing Control Instruc-
tions 5-113
Conversion Instructions 5-114
Character Search Instructions 5-124
Move Instructions 5-137
6. Software Systems
General Information
Operating Systems
Real-Time SCOPE
MASTER
MSOS
SCOPE Utility Routines
Languages
FORTRAN-32
Mass Storage FORTRAN
COBOL 32
COBOL 33
Mass Storage COBOL
ALGOL
COMPASS-32
COMPASS-33
Data Processing Package
Report Generator
6-1
6-1
6-2
6-2
6-2
6-2
6-3
6-3
6-3
6-3
6-4
6-4
6-4
6-4
6-5
6-5
6-5
Input / Output
RESPOND /MSOS
MSIO
SIPP
6-5
6-6
6-6
6-6
A pplic a tions 6- 6
PERT/TIME 6-7
PERT/COST 6-7
SORT 6-7
Mass Storage SORT 6-7
REGINA-I 6-7
ADAPT 6-8
7. Console and Power Control Panel
General Information
Console
Register Displays
Instruction and Communication
Registers
Instruction State and Operand
State Registers
Data Interchange Display
Status Display
Switches and Controls
Typewriter
Power Control Panel
Elapsed Time Meters
Storage Protect Switches
7-2
7-2
7-2
7-2
7-3
7-3
7-4
7-6
7-19
7-24
7-24
7-24
APPENDIXES
A. CONTROL DATA 3100, 3200, 3300 Computer Systems Character Set
and BCD / ASCII Code Conversions
B. Supplementary Arithmetic Information
C. Programming Reference Tables and Conversion Information
D. Instruction Formats and Notes
E. Multiprogramming and Relocation Supplementary Information
F. Business Data Processing Supplementary Information
GLOSSARY, INSTRUCTION TABLES, AND INDEX
Rev. C
iv

FIGURES
1-1 3300 Modularity Example 1- 2
1-2 Computer Word Character
1-3
1-4
2-1
2-2
3-1
3-2
3-3
Positions and Bit Assignments 1-5
Block Control Scanning Pattern 1-11
Parity Bit Assignments 1-12
3300 Storage Modules 2-2
Optional Protect Scheme
3300 I/O System
3-2
I/O Channel Power Panel
Principal Signals Between I/O
Channel and External Equipment 3- 3
5-1 Word-Addressed Instruction
Format
5-2 Character-Addressed Instruc-
tion Format
5-3 Business Oriented Instruction
Format
5-4 Indexing and Indirect Address-
ing Routine Flow Chart
5-5 Operand Formats and Bit
Allocations for MUAQ and
DV AQ Instructions
5- 6 Operand Formats and Bit
Allocations for Floating Point
Arithmetic Instructions
5- 6. 1 77 Connect Operation
5-4
5-4
5-6
5-8
5-64
5-67
5- 95.1
5-6.2 77 Select Function Operation
5 -7 73 I/O Operation with Storage
5- 8 74 I/O Operation with Storage
5-9 75 I/O Operation with Storage
5-10 76 I/O Operation with Storage
5 -11 73 I/O Operation with A
5-12 74 I/O Operation with A
5-13 75 I/O Operation with A
5-14 76 I/O Operation with A
5-15 SRCE Operation
5-16 SRCN Operation
5-17 Move Instruction
7 -1 3300 Console
7 -2 Register Display Area
7- 3 ISR and OSR Display and
Binary Entry Switches
7- 4 Data Interchange Display
7- 5 Status Display
7- 6 Condition Switches
7-7 Access Keyboard Switches
7-8 Upper Console Switch Panel
7-9 Breakpoint Switch Examples
7 -10 Console Typewriter Control
Switches
7 -11 Power Control Panel
TABLES
1-1
Register File Assignments
1-10 5-2
Summary of Instruction
1-2
Buffer Groups
1-11
Execution Times
1- 3
BCR Conditions
1-14
5-3
Interrupt Mask Register Bit
2-1
Storage Protection Switch Assignments
Descriptions
2-6
5-4 Bit Assignments for Interrupt
2-2
Storage Protection Switch Sensing Conditions
Settings
2-7
5-5 Internal Status Sensing Mask
2-3
Optional Storage Protection
5-6
Pause Sensing Mask
Example
5-7
Interrupt Mask Register Bit
4-0
Parity Error Interrupt Codes
4-5
Assignments
4-1
Trapped Instruction for
5-8
Modified I/O Instruction
Non- Executive Mode without a Words
3310 or 3312 Module System
4-6
5-9 Block Control Clearing Mask
4-2
No-Operation Instruction for 5-10 Editing Examples
N on- Executive Mode
4-6 7-1
Data Interchange Indicator
4-3
Interrupt Priority
4-8
Descriptions
4-4
Representative Interrupt Codes
4-10
7-2
Status Display Indicator
4-5
Interrupt Mask Register Bit Descriptions
Assignments
4-11
7-3
Condition Switches Descrip-
4-6
Condition Register Bit tion
Assignments
7-4
Access Keyboard Switches
5-1
Instruction Synopsis and Index
5-12 7-5
Console Typewriter Switches
and Indicators
7-6
Console Typewriter Codes
5-96,1
5-99
5-101
5-103
5-105
5-106
5-108
5-109
5-111
5-126
5-128
5-139
7-1
7-2
7-3
7-3
7-4
7-7
7-9
7-10
7-17
7-19
7-25
5-12
5-84
5-84
5-85
5-87
5-90
5- 93
5-95
5-153
7-4
7-5
7-7
7-10
7-21
7-23
v
Rev. F

FORWARD
This manual provides information for the machine language use of the 3300 computer
system. Its intention is to describe the capabilities and programming restraints of
the hardware.
COMPASS mnemonics are used to abbreviate titles of instructions; however, no software
systems are used in describing instructions. Brief descriptions of these software
systems are included in Section 6. Detailed descriptions for those systems in operation
are available in the appropriate software reference manuals.
Programming information for most available peripheral equipments is contained in the
3000 Series Peripheral Equipment Reference Manual, Pub. No. 60108800.
vii
Rev. B

CONTROL DATA 3300 COMPUTER SYSTEM

1. GENERAL SYSTEMS DESCRIPTION
INTRODUCTION
The CONTROL DATA* 3300 is an advanced design general-purpose computing
system providing high performance time- sharing with multiprogramming fea-
tures to satisfy present and future needs of business and scientific users. Ad-
vanced design techniques are used throughout the 3300 to provide expedient
solutions for scientific, real-time, and business data processing problems.
Time- sharing and multiprogramming features of the 3300 enable a user to
enter many programs and receive processed results without the delays incurred
in single-job batch processing systems. This feature not only reduces turn-
around time but also provides a considerable saving in computer usage and
personnel time. Multiprocessing of programs further enhances system perfor-
mance when additional central processors are integrated into a total system.
Software systems for the 3300 take full advantage of the time-sharing and
multiprogramming capabilities of the hardware and include the MASTER,
Real-Time SCOPE, and MSOS operating systems, and the Mass Storage
Input/Output (MSIO) system. A synopsis of each of these systems and other
software is included in Section 6 of this manual.
All existing programs written for CONTROL DATA 3100 and 3200 systems can be
processed by a 3300. I/O characteristics for the 3300 are identical to the
3100, 3200, 3400, 3500, 3600, and 3800 line of Control Data computers - a fact
which facilitates incorporating the 3300 into a SATELLITE* configuration.
Included in the expanded repertoire of 3300 instructions is a complete list of
business data processing instructions. These extend the flexibility of the 3300
by performing field searches, moves, compares, tests, conversions, arithmetic
operations, and complete COBOL editing while utilizing the time- sharing feature
of the 3300.
A wide selection of proven peripheral equipment is available for use in a 3300
system including many new and advanced equipments.
*Registered trademark of Control Data Corporation
1-1
Rev. C

This manual describes the various features of the 3300 and provides program-
ming and operation information. Reference and supplementary information may
be found in the Appendixes.
COMPUTER MODULARITY
A 3300 computer consists of various logic cabinet modules designed to perform
specific operations. If additional storage, input/ output channels, or arithmetic
capabilities are desired for an existing installation, an appropriate module is
integrated into the system. Figure 1-1 illustrates and describes the modules
of a typical 3300 computer.
®
@
©
K J I H G
Central Processing Unit (CPU)
2-3306 Input/Output (I/O)
channels or 1-3307 channel
and 1-3306 channel (Channels
o and 1)
2-3306 I/o channels or 1-3307
channel and 1-3306 channel
2-3306 I/O channels or 1-3307
channel and 1-3306 channel
A
®
®
©
®
CD
GD
®
BCD E F
2-3306 I/O channels or 1-3307
channel and 1-3306 channel
Power controls for I/O channels
©@®
3310 Floating Point module
3311 Multiprogramming module
Power Control Panel for@ @
3309- 8K Storage Module
3309- 8K Storage Module
Figure 1-1. 3300 Modularity Example
NOTES
1. A minimum 3300 configuration consists of items @ , @ , CD, and Q) .
2. A 3302 16K storage module may be substituted for items GD and ® .
(Cont'd on next page)
Rev. A
1-2

3. Additional storage modules are added to the left of item ® .
4. The 3312 BDP (not shown) is a "stand-alone" cable connected unit. Addi-
tional storage modules may also be stand-alone units to conform to installa-
tion space.
5. 3307 I/O channels are always designated an even channel number, i. e., 0,2,
4, or 6.
Central Processing Unit
The Central Processing Unit (CPU) is standard in all 3300 systems and performs
the following functions:
• Controls aBd synchronizes most internal operations of the computer.
• Processes all 24- bit precision fixed point arithmetic.
• Processes 48-bit precision addition and subtraction.
• Executes Boolean instructions.
• Character and word loading and storing.
• Executes decision instructions.
• Controls standard search and move operations, external equipment and
typewriter I/O, real-time clock referencing, and register file operations.
• Recognizes and processes all interrupts.
If the Business Data Processor (BDP) is present in a system, the CPU relin-
quishes control to it until the business oriented instructions(s) have been pro-
cessed.
Storage Modules
The magnetic core storage (MCS) available for 3300 systems ranges from a min-
imum of 8,192 (32,768 characters) to 262,144 (1,048,576 characters) words. An
MCS system is expanded in 16,384 word increments after two initial 8,192 word
storage modules are installed in the system. Up to 131,072 words of MCS may
be included in a system without the multiprogramming option present.
The following optional storage modules are available:
Model 3309 - 8,192 word (32,768 characters) MCS memory module
Model 3302 - 16,384 word (65,536 characters) MCS memory module
The word "storage" is used synonymously with "memory" in this text and both
refer to MCS unless otherwise stated. Additional information pertaining to the
3300 storage system may be found in Section 2.
Input/Output Modules
Two types of Input/Output (I/O) modules are available for use in 3300 systems.
These are the 3306 and 3307 Communication Channels.
The 3306 is a bidirectional 12-bit parallel data channel and conforms to the stand-
ard I/O specifications for all CONTROL DATA 3000 Computers. A maximum of
1-3
Rev. B

eight 3306 channels may be incorporated in a single system with up to eight
peripheral controllers connected to each channel. Space is provided for mount-
ing two 3306 channels per module. Figure 1-1 shows the placement of the
channels in a maximum I/O channel configuration.
The 3307 is a bidirectional 24-bit parallel data channel and also conforms to the
Control Data 3000 I/O specification. In each 3307 channel 12-to 24-bit assembly/
disassembly is included. A maximum of four 3307 channels in addition to four
3306 channels may be present in a single system.
Additional information pertaining to the 3306 and 3307 I/O channels may be
found in Section 3.
Floating Point Module
The optional 3310 Floating Point Module permits a user to directly execute
floating point addition, subtraction, multiplication, and division instructions
utilizing 48-bit precision floating point operands. This option also permits
direct execution of 48- bit precision multiplication and division instructions.
Multiprogramming Module
The optional 3311 Multiprogramming Module provides capability to relocate
program instructions, data, and I/O in MCS. This option implements the 3300
memory page system and provides inherent memory protection as well as re-
location and MCS extension to 262,144 words. If the 3311 is not present in a
system, the maximum number of words is 131,072. Refer to Appendix E for
additional information.
Business Data Processor
The optional 3312 Business Data Processor (BDP) provides the capability to
directly execute variable field length business data processing instructions.
These instructions include field searches, moves, editing operations, compares,
arithmetic operations, and binary/BCD/ASCII conversions. Delimiting is pro-
vided for appropriate instructions to increase their flexibility.
The internal organization of the BDP is further described under Internal Organi-
zation in this section.
Operator's Console
The operators desk console includes:
•. Octal register displays
• Built- in on-line typewriter
• Built-in entry keyboard and control switches
• Complete status monitoring system
• Operator's chair
Rev. A 1-4

A complete description of the console, examples of manual operations, and a
picture of the console can be found in Section 7.
Power Control Panel
A power control panel is provided to control secondary logic power to the CPU,
floating point module, and I/O channels 0 and 1. Other modules have their own
power control panels. Primary power for the entire computer system is con-
trolled by a group of switch boxes mounted on a nearby wall.
INTERNAL ORGANIZATION
Central Processing Unit
Computer Word Format
The standard 3300 computer word consists of 24 binary digits. Each word is
divided into four 6- bit characters. In storage, an odd parity bit is genera ted
and checked for each of the four characters, lengthening the storage word to
28 bits. Figure 1-2 illustrates the bit assignments of a computer word in
storage.
23 1817 12 II
0605 00
I 0 I 2 I 3 I
\ \ ! I
Character Designators
Figure 1-2. Computer Word Character Positions and Bit Assignments
Register Descriptions
A Register (Arithmetic): The A register (accumulator) is the principal arith-
metic register. Some of the more important functions of this register are:
• Most arithmetic and logical operations use the A register in formu-
lating a result. The A register is the only register with provisions
for adding its contents to the contents of a storage location or
another register.
• The A register may be shifted to the right or left separately or
in conjunction with the Q register. Right shifting is end-off; the
lowest bits are discarded and the sign is extended. Left shifting
is end-around; the highest order bit appears in the lowest order
stage after each shift; all other bits move one place to the left.
• The A register holds the word which conditions jump and search
instructions.
Q Register (Arithmetic): The Q register is an auxiliary accumulator register
and is generally used in conjunction with the A register.
1-5
Rev. A

The principal functions of Q are:
• Providing temporary storage for the contents of A while A is used
for another arithmetic operation.
• Forming a double-length register, AQ.
• Shifting to the right or left, separately or in conjunction with A.
• Serving as a mask register for 06, 07, and 27 instructions.
E Register (Arithmetic): The optional arithmetic register E is present in a
system whenever the 3311 Floating Point option is present in a system. During
floating point/ 48- bit precision operations, the E register is divided into two
parts, EU'~ and EL'~, each composed of 24 bits. It is used as follows:
• 48-bit precision multiplication; holds the lower 48 bits of a 96-bit
product.
• 48-bit precision division; initially holds the lower 48 bits of the
dividend; upon completion, holds the remainder.
• Floating point multiplication; holds the re sidue of the coefficient
of the 48- bit product.
• Floating point division; holds the remainder.
P Register (Main Control): The P register is the Program Address Counter.
It provides program continuity by generating in sequence the storage addresses
which contain the individual instructions. During a Normal Exit the count in P
is incremented by 1 at the completion of each instruction to specify the address
of the next instruction. These addresses are sent via the S (address) Bus to the
specified storage module where the instruction is read. A Skip Exit advances
the count in P by 2, bypassing the next sequential instruction and executing the
following one. For a Jump Exit, the execution address portion of the jump in-
struction is entered into P and used to specify the starting address of a new
sequence of instructions.
Bb Registers (Main Control): The three index registers, B1, B2, and B3, are
used in a variety of ways, depending on the instruction. In a majority of the
instructions they hold quantities to be added to the execution address, M=m+Bb.
The index registers may be incremented or decremented.
C Register (Main Control): Quantities to be entered into the A, Q, B, or P
registers or into storage from the entry keyboard are temporarily held in the
Communication (C) register until the TRANSFER switch is pushed. If an error
is made while entering data into the Communication register, the KEYBOARD
CLEAR switch may be used to clear this register.
The C register holds words read from storage during a Sweep or Read Storage
operation. The contents of C are displayed on the console whenever the key-
board is active.
*E
U
signifies EU ; EL signifies EL .
pper ower
Rev. A
1-6

F Register (Main Control): The program control register F holds an instruction
during the time it is being executed. During execution, the program may modify
the instruction in one of three ways:
• Indexing (Address Modification) - A quantity in one of the index
registers (Bb) is added to the lower 15 bits of F for word- ad-
dressed instructions, or to the lower 17 bits of F for character-
addressed instructions. The signs of Bb and F are extended for
the addition process.
• Indirect Addressing - The lower 18 bits of F are replaced by
new'a: 'b; and'm' designators from the original address M
(modified if necessary, M = m + Bb).
• Indirect Addressing (load and store index instructions) - Bits
00 - 14 and 17 of F are replaced by new 'a' and 'm' designators
from the original address M (no modification possible).
After executing an instruction a Normal Exit, Skip Exit,or Jump Exit is perform-
ed. F is displayed on the console whenever the keyboard is inactive and the
computer is not in the GO mode.
Instruction State Register (Main Control): Instruction State register is a 3- bit
register that is referenced under certain conditions when the computer is oper-
ating in Executive mode. The (ISR)':' are appended to the (p) in the process of
referencing different program address groups. Refer to Appendix E for the
different conditions when this register may be used.
Operand State Register (Main Control): Operand State register is also a 3-bit
register that is referenced under certain conditions when the computer is oper-
ating in Executive mode. Appendix E describes the conditions when the OSR is
referenced with regard to the operational state of the CPU.
Channel Index Register (Main Control): The Channel Index register (CIR) is a
3
-bit register whose contents are logically OR' ed (inclusive OR function) with
the channel designator' ch' for the following instructions:
• 73 -76 I/O instructions
• 77.0 Connect
• 77. 1 Select Function
• 77.2 Sense External Status
• 77. 2 Copy External Status
• 77. 3 Sense Internal Status
• 77.3 Copy Internal Status
• 77.4 Sense Interrupt
This permits instructions to be written for channel 0 and allows the monitor pro-
gram to assign the proper channel by altering the (CIR). The (CrR) can be trans-
ferred by instruction to the lower 3 bits of the A register and vice versa. A
momentary switch is provided on the console for displaying (eIR) in the lowest
digit position of the Index register display area.
':'The parentheses, as they are used in this case, are an accepted method for
expressing the words "the content(s) of" (in this case "the contents of" the ISR
regi ster).
1-7
Rev. A

Condition Register (Main Control): Bits in the Condition register (CR) are used
as flags to initiate computer action and to record current operating conditions
during Executive mode. With the exception of bit 04, the register is not used
during non- Executive mode operations.
All register bits can be set or cleared with the ACR (77. 634) instruction; selected
bits are set or cleared by individual instructions and conditions, Refer to Section
4 for special considerations involving the register during interrupt processing.
The register bit assignments are listed below:
Bit 00
Bit 01
Bit 02
Bit 03
Bit 04
Bit 05
Boundary Jump
Destructive Load A
Operands Relocated Using OSR
Program State Jump
Interrupt System Enabled
Program State
Data Bus Register (DBR - Main Control): A 24- bit Data Bus register is used to
temporarily hold the data received from storage, Communication register, and
other logic areas. It is a nondisplayed and nonaddressable register.
During character-addressed or I/O operations, data entering the DBR may be
shifted one, two, or three character positions during the transfer to reach the
correct character position within the DBR.
Interrupt Mask Register (Main Control): The 12- bit Interrupt Mask register
allows a user to honor or ignore a group of various interrupts by setting the
register bits to "I' s" or "0' s ". Each register bit corresponds to a particular
interrupt condition. The mask bits may be set or cleared by executing the SSIM
and SCIM instructions, respectively. The specific mask register bit assign-
ments are described in Section 4.
S Register (Storage): The S register holds the address of the storage word
currently being referenced.
Z Register (Storage): The Z register is the storage restoration and Modification
register. Data stored or being transferred to or from the address specified by
the S register must pass through Z. The entire storage word including the four
parity bits is represented by the Z register and is displayed on the Storage
Module control panel.
Bus Systems
The Data Bus provides a common path over which data must flow to the storage,
arithmetic, console typewriter, and I/O sections of the computer. These sec-
tions are connected in parallel to the Data Bus. During the execution of each
instruction, Main Control determines which data transfer path is activated.
Rev. F
1- 8

An odd parity bit is generated for the lower byte of each word as it leaves the
DBR during I/O operations. In the case of a 3307 I/O Channel, parity for the
upper byte of data is generated in the channel itself rather than in the Data Bus.
The S or Address Bus is a data link between Main Control and storage for trans-
mitting storage addresses. Inputs to the S Bus are from the P register, F reg-
ister, Block Control, and the Breakpoint circuits.
Executive Mode
The CPU can operate in either the non-Executive mode or Executive mode. In
non-Executive mode the 3300 operates identically to the 3200.
Depressing the EXECUTIVE MODE switch on the operator's console causes the
3300 to function in the Monitor State of Executive mode. All 3300 instructions
may be executed in the Monitor State provided the necessary hardware is pre-
sent in the system.
After executing a Set Boundary Jurpp (SBJP) instruction, the next jump instruction
causes the 3300 to advance to the Program State of Executive mode. In Program
State, the CPU performs at its highest efficiency by restricting itself to actual
computations by not executing I/O or Block Control instructions. If a Halt (00.0)
instruction, any of the 71-77 instructions (except SBCD 77.72 and SFPF 77.71),
or an inter -register transfer affecting registers 00 through 37 of the register file
is attempted while in Program State, the 3300 reverts to the Monitor State of
Executive mode. Additional information can be found in Appendix E.
Block Control
Block Control is an auxiliary control section within a 3300 processor.
In conjunction with the register file and program control, it directs the following
opera tions :
• External equipment I/O
• Search/Move
• Real- Time clock
• Console typewriter I/O
• High- speed temporary storage
Register File: The register file is a 64-word (24 bits per word) rapid access
memory with a cycle time of 0.5 usec. Although the programmer has access to
all registers in the file with the interregister transfer (53) instruction, certain
registers are reserved for specific purposes (see Table 1-1)~ All reserved
registers may be used for temporary storage if their use will not disrupt other
operations that are in progress.
The contents of any register in the file may be viewed by selecting the register
number with the Breakpoint switch and pressing the READ STO switch on the
keyboard. The contents may be altered by setting the Breakpoint switch, pres-
sing the WRITE STO switch, and entering a new word from the keyboard.
1-9 Rev. A

Register
Numbers
00-07
10-17
20
21
22
23
24-27
30
31
32
33
34-77
TABLE 1-1. REGISTER FILE ASSIGNMENTS
Register Functions
Modified I/O instruction word containing the current character
address (channel 0-7 control)
Modified I/O instruction word containing the last address ± I,
depending on the instruction (channel O-~ control)
Search instruction word containing the current character ad-
dress (search control)
Move instruction word containing the source character address
(move control)
Real-time clock, current time
Current character address (typewriter control)*
Temporary storage
Instruction word containing the last character address + 1
(search control)
Instruction word containing the destination character address
(move control)
Real-time clock, interrupt mask
Last character address +1 (typewriter control) *~,
Temporary storage
*The contents of register 23 should have the following format:
23 2120 1716 OOE--Bit positions
1<0-7)_ I
Must contain the ~- Sla~ed area ShOUl~current character address
gram state number contain "0' s"
**The contents of register 33 should have the following format:
23 1716
00
Slashed area
should c;:tain "0' s"
\
Last character address plus one
Block Control Priority: Access to Block Control circuits is shared between the
computer's main program control and block control buffered functions. Functions
within Block Control are divided into three groups (Refer to Table 1-2.) The
five scanners that provide the priority access network for the system are the Pro-
gram/Buffer scanner, the Group scanner, 'and the three inner group scanners.
Figure 1-3 illustrates the scanning pattern of the priority network.
Rev. C
1-10