Control Data 3100 User manual

COMPUTER SYSTEM
REFERENCE MANUAL
CONTROL DATA
CORPORATION

60108400
Record of Revisions
REVISION NOTES
A
Obsoletes previous editions.
B
Publications Change Order 11527 which incorporates
(9-27-65)
extensive revisions into this manual.
This edition
obsoletes previous editions.
Pub. No. 60108400
September 1965 Address comments concerning this manual
to:
Control Data Corporation
Technical Publications Department
4201 North Lexington Avenue
©1965, Control Data Corporation
Printed in the United States
of America St. Paul, Minnesota 55112
Or use Comment Sheet in back of this manual.

CONTENTS
Section 1. SYSTEM DESCRIPTION
INTRODUCTION ................................................................... 1-1
COMPUTER MODULARITY. .. . .. . . . .. .. . .. . . . .. .. .. . .. .. . . . .. .. . . . .. .. .. . . .. . .. . ... 1-1
Main Control and ArithmeticModule ......... , ........ , ........................... 1-3
Block Control and Interrupt Module. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . .. 1-3
Storage Module. . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 1-3
Input/Output Sub-Modules. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. .. 1-3
Optional Arithmetic Module .......................... , ........ , .................. 1-4
Consoles. . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . .. . . .. 1-4
Power Control Panel ..... , .................. , .................................... 1-7
3104 COMPUTER .. , ............................................................... 1-7
COMPUTER ORGANIZATION. . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . .. . . . . .. . . . . . .. 1-7
Computer Word Format .......................................................... 1-7
Register Descriptions. . . . . . . .. . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 1-7
Data Bus and (S' Bus ............................................................. 1-11
Block Control ................................................................... 1-11
Integrated Register File ......................................................... 1-12
Real-Time Clock ................................................................. 1-12
Parity ......................................................................... 1-13
PERIPHERAL EQUIPMENT ........................................................ 1-14
Section 2. STORAGE CHARACTERISTICS
STORAGE MODULE CONTROL PANEL. . . .. .. .. . .. .. . .. .. . . .. . . .. .. .. . .. . .. .. .. . ... 2-1
STORAGE REGISTERS. . . . . . . . . . . . .. . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . . .. . .. 2-2
S Register. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 2-2
Z Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . .. 2-2
READ/WRITE CHARACTERISTICS . . . . . . . . . . . .. .. . .. . . . . . . .. .. .. ... . . . .. .. . . .. .. ... 2-2
Single-CharacterMode. . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. 2-2
Double-Character Mode. . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . .. . . . . . .. . . . . . . .. 2-2
Triple-Character Mode. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . .. 2-2
Full-Word Mode ................................................................. 2-2
Address Mode ............ , ................. , ........ " ................. , ........ 2-2
STORAGE ADDRESSING. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . .. 2-3
STORAGE SHARING. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . .. 2-3
STORAGE PROTECTION. . . . . .. . . .. . .. .. . .. . .. . . .. .. .. . . ... .. . . . .. . .. .. . . .. .. . .. ... 2-3
Permanent Protection ................................ , ................. , ........ 2-4
Selective Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . .. . .. 2-4
No Protection. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . .. . . .. . . . . .. 2-4
Section 3. INPUT/OUTPUT CHARACTERISTICS
INTERFACE SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . .. . . .. 3-1
I/O PARITY ........................................................................ 3-2
Parity Checking with the 3106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
Parity Checking with the 3107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
iii
Rev. B

AUTO LOAD/AUTO DUMP. . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .... 3-3
Preliminary Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 3-3
Auto Load ..... -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
Auto Dump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
3100 Auto Load/Auto Dump Interim Subroutine ... '" ................. " .......... 3-3
SATELLITE CONFIGURATIONS .................................................... 3-5
Section 4. INTERRUPT SYSTEM
GENERAL INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
INTERRUPT CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
Internal Interrupts .............................................................. 4-1
Trapped
Instruction Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
Power Failure Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
I/O Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
INTERRUPT MASK REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
INTERRUPT CONTROL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
Enabling or Disabling Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Interrupt Priority ............................................................... 4-4
Sensing Interrupts- ....................... -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
Clearing Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
INTERRUPT PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
Section 5. CONSOLES AND POWER CONTROL PANEL
CONSOLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
Register Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 5-1
Console Loudspeaker
.......................................................... " 5-4
Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-7
POWER CONTROL PANEL ......................................................... 5-15
Switches ........................................................................ 5-15
Elapsed Time
Meters ............................................................ 5-15
Section 6. TYPEWRITER
DESCRIPTION ...... - ............................................................... 6-1
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
Set Tabs, Margins, and Spacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
Clear ........................................................................... 6-2
Status Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
Type In and Type Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
Type Out and Type Dump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
CONSOLE SWITCHES AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
CHARACTER CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5
Section 7. INSTRUCTIONS
GENERAL INFORMATION ......................................................... 7-1
Instruction Word Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-1
iv

Word Addresses vs. Character Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-2
Symbol Definitions. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3
Indexing
and Address Modification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3
Addressing Modes. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .
.. 7-4
Indexing
and Addressing Mode Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-5
I/O Channel Considerations .................................................... " 7-6
Trapped
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-6
INSTRUCTION LIST ............................................................... " 7-7
Register OperationswithoutStorage Reference
..................................... 7-12
Load
........................................................................... 7-20
Store
.......................................................................... 7-23
Inter-registerTransfer, 24-bit Precision
.......................................... 7-26
Inter-register Transfer, 48-bit Precision
.......................................... 7-29
Stops and Jumps ................................................................ 7-30
Logical Instructions with StorageReference ........................................ 7-37
Arithmetic, Fixed Point, 24-bit Precision
.......................................... 7-38
Arithmetic, Fixed Point, 48-bit Precision
.......................................... 7-40
Arithmetic, Floating
Point ....................................................... 7-43
BCD
........................................................................... 7-46
Storage Shift, Searches, Compare
and Register Shifts ............................... 7-50
Search .................. - ........................................................ 7-56
Move
.................................................................. ~ ........ 7-58
Sensing ........................................................................ 7-60
Control
........................................................................ 7-63
Interrupt ....................................................................... 7-65
Input/Output ................................................................... 7-68
Section 8.
SOFTWARE SYSTEMS
GENERAL DESCRIPTION. . . . . . . . . . . . . . . . .. .. .. . .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. ... 8-1
3100, 3200, 3300 SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-1
3100, 3200, 3300 COMPASS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-2
3100,3200,3300 Data Processing Package ....................................... 8-3
3100,3200,3300 Utility ......................................................... 8-4
3100, 3200, 3300 COBOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. 8-4
3100, 3200, 3300 FORTRAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. 8-5
Generalized Sort/Merge
Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. 8-5
3100, 3200, 3300 BASIC System. . . . . . .. . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . .. . . .. 8-6
CODING PROCEDURES. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-7
Instruction
Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-7
Pseudo-Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
.. 8-9
Assembly Listing
Format ........................................................ 8-17
Error Codes .................................................................... 8-18
APPENDIX
A-Control Data 3100,3200,3300 Computer Systems Character Set
B- Supplementary Arithmetic Information
C- Programming Reference Tables
and Conversion Information
GLOSSARY, INSTRUCTION TABLES AND INDEX
v
Rev. B

FIGURE FIGURES
1-1 3100 Modular Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1-2 3101 Console. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-5
1-3 3200 Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 1-6
1-4 Computer Word
Character Positions and Bit Assignments .......................... 1-7
1-5 Storage Addressing
and Data Paths of Typical Installation ......................... 1-11
1-6
Parity Bit Assignments ......................................................... 1-13
2-1 Storage Module Control
Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
3-1 Principal Signals Between I/O Channel and External Equipment ................... 3-1
3-2
Satellite Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
5-1
Front View of Integrated Console. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-2
5~2 EUEL Register Display ......................................................... 5-3
5-3 ED Register Display . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 5-3
5-4
External Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
5-5
Internal Status Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-5
5-6
Temperature Warning Designations for an Expanded 3100 Computer, Front View .... 5-6
5-7 Console
Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
5-8 Breakpoint Switch Examples
.................................................... 5-13
5-9 Power Control
Panel ............................................................ 5-16
6-1 3192 Console
Typewriter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
6-2 Typewriter Control
Panel ....................................................... 6-3
7-1 Word-Addressed Instruction
Format .............................................. 7-1
7 -2 Character-Addressed Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-2
7-3 Indexing
and Indirect Addressing Routine Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-3
7-4 Operand Formats and Bit Allocations for MUAQ and DVAQ Instructions ............ 7-41
7-5 Operand
Formats and Bit Allocations for Floating Point Arithmetic Instructions ..... 7-45
7-6 Search Operation .............................................................. 7-57
7
-7 Move Operation ................................................................ 7-59
7-8 73 I/O Operation
with Storage ................................................... 7-73
7-9 74 I/O Operation
with Storage ................................................... 7-75
7-1075 I/O Operation with Storage ................................................... 7-77
7-11 76 I/O Operation
with Storage ................................................... 7-79
7-1273 I/O Operation
with A ......................................................... 7-81
7-1374 I/O Operation with A ......................................................... 7-83
7-1475 I/O Operation
with A ........................................................ 7-85
7-1576 I/O Operation
with A ........................................................ 7-87
8-1 COMPASS Coding Form
........................................................ ·8-19
8-2 FORTRAN Coding Form ........................................................ 8-19
~ev. B vi

TABLE TABLES
1-1 Optional Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
1-2 Characteristics
of 3100 Computer Registers ....................................... 1-10
1-3 Register File Assignments ...................................................... 1-13
2-1 Absolute Addresses ............................................................. 2-3
2-2 Auto LoadlAuto Dump Reserved Addresses. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
.. 2-4
2-3 Storage Protection Switch Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.. 2-5
2-4 Storage Protection Switch
Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
4-1
Interrupt Mask Register Bit Assignments ......................................... 4-3
4-2
Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-4
4-3 Representative
Interrupt Codes .................................................. 4-5
5-1 Keyboard Switch
Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-9
5-2 Console
Main-Frame Switches ................................................... 5-10
5-3 Power Control Panel Switch Functions ............... , .. " ........ , .............. 5-15
6-1 Console Typewriter Switches
and Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-4
6-2 Console Typewriter Codes
....................................................... 6-5
7
-1 List of Trapped Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-7
7-2 Instruction Synopsis
and Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-8
7-3
Summary ofInstruction Execution Times ......................................... 7-11
7-4
Interrupt Mask Register Bit Assignments ......................................... 7-61
7-4a
Bit Assignments for Interrupt Sensing Conditions ................................. 7-61
7-5
Internal Status Sensing Mask ................................................... 7-62
7
-6 Block Control Clearing Mask .................................................... 7-63
7-7
Pause Sensing Mask .................................................. , ......... 7-64
7-8
Interrupt Mask Register Bit Assignments ......................................... 7-65
7
-9 Modified I/O Instruction Words .................................................. 7-69
8-1 Instruction
Interpretations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-8
8-2 COMPASS Coding Form Description
............................................. 8-18
vii Rev. B

Section 1
SYSTEM DESCRIPTION
INTRODUCTION
The CONTROL DATA * 3100 is a medium-sized, solid-state, general-purpose digital
computing system. Advanced design techniques are used throughout the system to
provide expedient solutions for scientific, real-time, and data processing problems.
Modular packaging facilitates expansion of the basic 3100 System to accommodate
increasing customer needs.
The 3100 is upwards compatible with the CONTROL DATA 3200 and 3300 Computer
Systems; i.e., as computation requirements exceed the capabilities of the 3100 System,
the user may escalate to a 3200 or 3300 System without the necessity to revise existing
3100 programs. Its input/output characteristics are identical to the 3200, 3300, 3400,
3600
and 3800 Computer Systems - a fact which facilitates incorporating the 3100 into
a SATELLITE * configuration.
Various software systems are available for the 3100 System. The SCOPE operating
system is used in 3100 Systems to provide efficient job processing. SCOPE requires a
minimum of storage and time requirements. COMPASS, operating under the control
of SCOPE, is the assembly system used to assemble relocatable machine language
programs. Other applicable software includes FORTRAN, COBOL, the Data Processing
Package, Generalized Sort/Merge and Basic System. These systems are described in
the Software Section of this manual. Other software and hardware publications perti-
nent to 3100 Systems may be obtained from the nearest Control Data sales office listed
on the back cover of this manual.
A wide selection of peripheral equipment is available for use in a 3100 System. Equip-
ment that is applicable for 3100 Systems may be found in the 3000 Series Computer
System Peripheral Equipment Reference Manual, publication number 60108800.
This manual provides programming and operating information in conjunction with a
description of special features of the 3100. Reference information and supplementary
information may be found in the Appendix section.
COMPUTER MODULARITY
A 3100 Computer consists of various logic cabinet modules designed to perform specific
operations. If additional storage, input/output channels, or arithmetic capabilities are
desired for an existing installation, an appropriate module is integrated into the system.
The 3104 (Figure 1-1), described later in this section, constitutes the basic 3100 modular
configuration.
*Registered trademarks of Control Data Corporation
1-1

~~
l=r I
I
N
T SPACE
E
FOR 8K 4K BLOCK SPACE
FOR
G STORAGE STORAGE CONTROL OPTIONAL
MAIN CONTROL POWER
R
MODULE
MODUL E
AND
ARITHMETIC
AND
CONTROL
A (OPTIONAL) (8K
OPTIONAL)
INTERRUPT
MODULE
ARITHMETIC MODULE
PANEL
T
MOD ULE
r--
E
D
C
0
N
S
------ --- ---
------
0
L I/O
MOD ULE
I/O MODULE
E
CHANNELS
UNUSED
CHANNELS
2 AND 3 AREA
OAND 1
(O PTIONAL )
(1 OPTIONAL)
l--
l 1
Figure 1-1. 3100 Modular Configuration
Rev. 8 1-2

MAIN CONTROL AND ARITHMETIC MODULE
This module, standard in all 3100 systems, controls internal operations, executes 24-bit
precision fixed
point arithmetic and 48-bit precision fixed point addition and subtraction
instructions. Boolean, character word processing, and decision operations are also processed
by
this module. Floating point, BCD, and 48-bit precision multiplication and division in-
structions are classified as trapped instructions if the optional arithmetic module is absent
from the system. Trapped instructions may be processed under control of an interpretive soft-
ware routine.
BLOCK CONTROL AND INTERRUPT MODULE
Logic associated with this module controls Search and Move operations, external equip-
ment and typewriter 110, real-time referencing, and operations with the register file. In-
terrupt logic, also located in this module, processes Internal, 110, Trapped Instruction, and
Power Failure interrupts.
STORAGE MODULE
A unique 4,096-word memory module is standard in e:very 3100 System. A customer may
select combinationsofmagnetic core storage (MCS) modules to increase the total storage
capacity of his computer system to 8,192; 16,384 or 32,768 words. The following optional
storage modules are available:
• 3108-4,096-word (16,384 characters) MCS memory expansion unit. This unit
is used only to expand the standard 4,096 word memory to 8,192 words.
• 3109- 8,192-word (32,768 characters) MCS memory module (requires additional
chassis).
• 3103 -16,384-word (65,536 characters) MCS memory module (requires addi-
tional chassis).
Memory configurations are shown in Table 1-1.
TABLE 1-1. OPTIONAL MEMORY CONFIGURATIONS
Total Expanded Memory Modules Required in
Memory Capacity
Addition to 4K Memory in 3104
8K 3108
16K
3108 and 3109
32K 3108.3109 and 3103
INPUT! OUTPUT SUB-MODULES
Two types of I/O Channels are available:
3106 Communication Channel (12-bit)
3107 Communication Channel (24-bit)
3106
The 3106 is a bidirectional 12-bit, parallel data channel. A maximum of four 3106
channels may be used in a 3100 System and up to eight peripheral controllers may be
connected to each channel. Cabinet space is provided for mounting two 3106 channels
per I/O module.
1-3
Rev. B

3107
The 3107 is a bidirectional 24-bit, parallel data channel with twice the data transfer rate of
the standard 3106 I/O channel. One 3107 occupies the same cabinet space required for two
3106 channels. If a 3107 is installed in a system, the maximum number of 3106 channels is
limited to two and the 3107 is installed in the space reserved for channels 2 and 3.
OPTIONAL ARITHMETIC MODULE
The floating point/48-bit precision standard arithmetic option No. 10018 provides the
necessary logic to execute 36-bit precision coefficient floating point arithmetic. It also
permits the 48-bit precision multiply and divide instructions to be executed directly
by the hardware.
The BCD standard arithmetic option No. 10019 permits decimal numbers to be added.
subtracted, loaded, stored or sensed directly without the use of interpretive software.
When both standard arithmetic options are incorporated into a system, it is referred
to as the 3100 General Arithmetic Option No. 10020. If one or both options are absent,
the instructions pertaining to that option(s) can be executed by entering a trapped
routine and utilizing the appropriate software.
If either or both arithmetic options are present in a system, they are contained In
chassis 4 which is normally located between chassis 1 and 2.
CONSOLES
A choice of three consoles is available for use in 3100 Computer Systems. Two consoles
are provided with binary displays and identical programming switches. A third, the
standard 3200 console, provides octal register readouts.
Standard Integrated Console
The integrated console consists of an upright control panel and display assembly
mounted on the end of the main computer frame. This console features binary displays,
status indicators, programming switches, monitor loudspeaker, and a removable key-
board for remote operation. A CONTROL DATA 3192 On-Line Typewriter is compatible
for systems using an integrated console. Refer to the Consoles and Power Control
Panel section for a more detailed description of this console.
3101
The optional 3101 Desk Console is electrically identical to and replaces the integrated console.
It features a special display panel for status conditions and binary register representation.
The entry keyboard and on-line typewriter are integral parts of this console. A chair is
provided for
the computer operator. Refer to Figure 1-2.
3200 Console
The 3200 Console may be used in 3100 Systems to provide octal register displays. This
console is referred to as Standard Option No. 10013 when used in a 3100 System. If
the system incorporates the BCD arithmetic option, the ED register is displayed by
decimal digits with visual plus and minus signs. An operator's chair is also provided
with this console. A full view of a 3200 Console appears in Figure 1-3.
Rev. B 1-4

Figure 1-2. 3101 Console
1-5

~ ------- ~------ ---,-.&. r=J
Figure 1-3. 3200 Console
1-6

POWER CONTROL PANEL
The Power Control Panel enables the computer operator to initially connect power to the
main computer, typewriter, and groups of peripheral equipment. Semipermanent storage
protection switches are located on the upper section of this panel. Operating time and main-
tenance time meters and the main equipment circuit breakers are also mounted on the control
panel.
Detailed information pertaining to the Power Control Panel appears in Section 5.
3104 COMPUTER
The 3104 is the basic 3100 Computer configuration. A 3104 consists of a Main Control and
Arithmetic module, Block Control and Interrupt module, single channel I/O module, 4,096
Word Storage module, Integrated Console, and a Power Control Panel. The basic 3104 is
expanded by
adding I/O channels, adding arithmetic option(s), and/or increasing the system's
magnetic core storage capacity to a maximum of 32,768 words. Either desk console may be
substituted for the Integrated Console.
COMPUTER ORGANIZATION
COMPUTER WORD FORMAT
The standard 3100 computer word consists of 24 binary digits. Each word is divided
into four 6-bit characters. In storage, an odd parity bit is generated and checked for
each of the four characters, lengthening the storage word to 28 bits. Figure 1-4 illus-
trates the bit assignments of a computer word in storage.
27 26 25 24 23
18 17 12 11 06 05 00
Character 0 Character 1 Character 2 Character 3
~'~--------------------~y~----------------------~/
Panty bits Character designators
Figure 1-4. Computer Word Character Positions and Bit Assignments
REGISTER DESCRIPTIONS
A Register (Arithmetic)
The A register (accumulator) is the principal arithmetic register. Some of the more
important functions of this register are:
• All arithmetic and logical operations use the A register in formulating a result.
The A register is the only register with provisions for adding its contents to
the contents of a storage location or another register.
• A may be shifted to the right or left separately or in conjunction with Q. Right
shifting is end-off; the lowest bits are discarded and the sign is extended. Left
shifting is end-around; the highest order bit appears in the lowest order stage
after each shift; all other bits move one place to the left.
• The A register holds the word which conditions jump and search instructions.
1-7

Q Register (Arithmetic)
The Q register is an auxiliary register and is generally used in conjunction with the
A register.
The principal functions of Q are:
• Providing temporary storage for the contents of A while A is used for another
arithmetic operation.
• Forming a double-length register, AQ.
• Shifting to the right or left, separately or in conjunction with A.
• Serving as a mask register for 06, 07, and 27 instructions.
Both A and Q may load or be loaded from any of the three index registers without the
use of storage references.
X Register (Arithmetic)
The X register is a transfer register, used only for internal instruction processing.
Contents of this register cannot be displayed by any external indicators.
F Register (Main Control)
The program control register, F, holds an instruction during the time it is being exe-
cuted. During execution, the program may modify the instruction in one of three ways:
• Indexing (Address Modification)-A quantity in one of the index registers
(B
b) is
added to the lower 15 bits of F for word-addressed instructions, or to
the lower 17 bits of F for character-addressed instructions. The signs of Bb
and F are extended for the addition process.
• Indirect Addressing - The lower 18 bits of F are replaced by new a, b, al1d m
designators from the original address M (modified if necessary, M = m+Bb ).
• Indirect Addressing (load and store index instructions)- Bits 00-14 and 17 of
F are replaced by new a and m designators from the original address M (no
modification possible).
After executing an instruction, a Normal Exit, Skip Exit or ·Jump Exit is performed.
F is displayed on the console whenever the keyboard is inactive and the computer is
not in the GO mode.
C Register (Main Control)
Quantities to be entered into the A, Q, B or P registers or into storage from the entry
keyboard are temporarily held in the Communication (C) register until the TRANSFER
switch is pushed. If an error is made while entering data into the Communications
register, the KEYBOARD CLEAR switch may be used to clear this register.
The C register holds words read from storage during a Sweep or Read Storage opera-
tion. The contents of C are displayed on the console whenever the keyboard is active.
P Register (Main Control)
The P register is the Program Address Counter. It provides program continuity by
generating in sequence the storage addresses which contain the individual instructions.
During a Normal Exit the count in P is incremented by 1 at the completion of each
instruction to specify the address of the next instruction. These addresses are sent via
the S (address) Bus to the specified storage module where the instruction is read. A
Skip Exit advances the count in P by 2, bypassing the next sequential inst~uction and
executing the following one. For a Jump Exit, the execution address portion of the jump
instruction is entered into P, and used to specify the starting address of a new sequence
of instructions.
1-8

Bb Registers (Main Control)
The three index registers, Bl, B2 and B3, are used in a variety of ways, depending on the
instruction. In a majority of the instructions they hold quantities to be added to the execution
address (M=m+ Bb). The Bb registers have no provision for arithmetic operations.
Data Bus Register (DBR-Main Control)
A 24-bit Data Bus register is used to temporarily hold the data received from storage, the
Communication register and other logic areas. It is a nondisplayed and nonaddressable
register.
During character-addressed or input/output operatIOns, data entering the DBR may be
shifted one, two,
or three character positions during the transfer to reach the correct character
position within the DBR.
E Register
The optional arithmetic register, E, is present in a system whenever one of the two
optional arithmetic logic packages is present. Its characteristics and functions depend
upon whether it is being used for floating point/48-bit precision or for BCD operations.
During floating point/48-bit precision operations, the E register is divided into two parts:
EU and EL (EUpper and ELower)' each composed of 24 bits. It is used as follows:
• 48-bit precision multiplication; holds the lower 48 bits of a 96-bit product.
• 48-bit precision division; initially holds the lower 48 bits of the dividend; upon
completion, holds the remainder.
• Floating point multiplication; holds the residue of the coefficient of the 48-
bit product.
• Floating point division; holds the remainder.
During BCD operations the E register is designated the ED register (EDecimal). The
unique decimal digits can be expressed in 4 bits, i.e., 810 = lOs and 910 = lIs. Accordingly, ED
is extended from 48 to 53 bits in order to handle 13 of these 4-bit characters, plus one
sign bit. This register is used in conjunction with storage to perform· BCD addition
and subtraction.
D Register
The D register is a field length register and is used in conjunction with loading, storing,
adding, and subtracting numeric BCD characters. This register is set to a field length
of 1 to 12 characters by executing a SET (70.7) instruction. The field length remains
the same until it is changed by another SET instruction.
The D register is present only when the BCD arithmetic option is incorporated into
a system. The contents of the D register cannot be displayed.
S Register (Storage)
The S register holds the address of the storage word currently being referenced. It is displayed
on the Storage Module control panel.
Z Register (Storage)
The Z register is the Storage Resoration and Modification register. Data stored or being
transferred to or from the address specified by the S register must pass through Z. The entire
storage word including the four parity bits is represented by the Z register and is displayed
on the Storage Module control panel.
1-9
Rev. 8

:::0
CD
~
OJ
*
**
***
****
TABLE 1-2. CHARACTERISTICS OF THE 3100 COMPUTER REGISTERS
REGISTER
FUNCTION
BIT
MODULUS
COMPLEMENT ARITHMETIC
RESULT
DESIGNATION
CAPACITY
NOTATION PROPERTIES
Main
A Arithmetic
24
224_1
one's
additive signed*
register
Auxiliary
Q
Arithmetic 24
224_1
one's additive signed*
register
Program i
F** Control
24
224_1
*** ***
***
register
Communica-
C** tions 24
224_1
register
.l!'.l!'.l!'.l!'
Program
p
Address 15
2
15
_1
register
81, B2, B3
Index
15
2
15
_1
one's
additive
unsigned
registers
Storage
S Address
13
213_1
register
Storage
28
Z Data (includes 4
224_1
register parity bits)
****
Arithmetic
X Transfer
24
224_1
register
EU and EL EUpper and
ELower octal
48
2
48
_1
one's
additive signed*
register
ED
53 (include
ED (BCD) sign and ±
10
13
absolute additive
signed
register overflow digit)
0 Field Length 4 24_1
one's
~.l!'~~
register
Since the A, Q, and EUEL register contents are all treated as signed quantities, the capacity of these registers is limited to the following values:
A::; 2
23
_1; Q::; 2
23
_1; EUEL::;: 24L 1. When the arithmetic result in A, Q, or EUEL is zero, it is always represented by positive zero.
Dual purpose register.
Only the lower 15 or 17 bits of F are modified depending on whether word or character addressing is being used. The results are unsigned.
Information not applicable.

DATA BUS AND'S' BUS
The Data Bus provides a common path over which data must flow to the storage,
arithmetic, console typewriter and I/O sections of the computer. These sections are
connected in parallel to the Data Bus. During the execution of each instruction, Main
Control determines which data transfer path is activated.
An odd parity bit is generated for the lower byte of each word as it leaves the DBR
during I/O operations. In the case of a 3107 I/O Channel, parity for the upper byte of
data is generated in the channel itself rather than in the Data Bus.
The S or Address Bus is a data link between Main Control and storage for transmitting
storage addresses. Inputs to the S Bus are from the P register, F register, Block Con-
trol and the Breakpoint circuits. Figure 1-5 illustrates the relevance of the Data Bus
and S Bus in a typical 3100 installation.
Storage Address S Bus
-
I T I
3108 3104
13200~;:-1
3109
I 3101 I
Storage Computer
.. -----+1 Desk I Storage
Module (Includes Standard I I
Module
I Console I
(4K)
4K Memory)
!_ i'1>.!i~n~~J
(8K)
1 Data Bus J
--
I T -I T
3106 3106
3106 3106
(may be a single 3107)
4 bidirectional data channels
Figure 1-5. Storage Addressing and Data Paths of Typical Installation
BLOCK CONTROL
Block Control is a unique control section within a 3100 Computer. In conjunction with
the Register File and program control, it directs the following:
• External equipment I/O operations~
• SearchlMove instruction processing.
• Real-Time clock referencing.
• Console typewriter I/O operation.
• Storage in the Register File.
All operations with Block Control result from requests to Block Control. The requests
are classified into two types: program requests and block operation requests.
1-11

Program requests are produced as the direct result of a programmed instruction. An
instruction of this type may perform the following:
1. Initiate the processing of a block of data,
2. Terminate the processing of a block of data,
3. Direct inter-register transfers in conjunction with the Register File,
4. Transmit Connect or Function commands to I/O channels.
Any request to Block Control, except for Connect or Function, results in one or more
Register File references. Block operation requests process blocks of data as directed by
the initial instruction.
Priority access is established for all Block Control operations with one exception: pro-
gram requests have either first or last priority. Last priority is granted only if a channel
request occurs almost simultaneously with the program request. The order of priority,
with program request listed first, is as follows:
1. Program request.
2. Channel 0 request.
3. Channel 1 request.
4. Channel 2 request.
5. Channel 3 request.
6. Real-time clock request.
7. Typewriter request or Read-Store or Write-Store with Register File request.
8. Search or Move request.
Every Block Control cycle normally completes the operation specified by the request.
A Move operation is the only possible exception. Due to the length of time required for
the Move operation cycle, it may be terminated in the middle of its cycle by a Channel
request. The aborted Move operation cycle results in no loss of data. The 'next complete
Move operation cycle moves the word or character of the aborted cycle.
INTEGRATED REGISTER FILE
The Integrated Register File is a 6410 word (24 bits per word) memory integrated into
the upper 64 addresses of storage. Although the programmer has access to all registers
in the file with the 53 instruction, certain registers are reserved for specific purposes
(see Table 1-3). All reserved registers may be used for temporary storage if their use
will not disrupt other operations that are in progress. The contents of any register in
the file may be examined by transferring them to the A register. Register 77 corresponds
to the uppermost storage address.
REAL-TIME CLOCK
The real-time clock is a 24-bit counter that is incremented each millisecond to a maxi-
mum period of 16,777,216* milliseconds. After reaching its maximum count, the clock
returns to zero and the cycle is repeated continuously. The clock, which is controlled
by a 1 kilocycle signal, starts as soon as power is applied to the computer. The current
time is stored in register 22 of the Register File. It is removed from storage, updated,
and compared with the contents of register 32 once each millisecond. When the clock
time equals the time specified by the clock mask, an interrupt is set. When necessary,
the real-time clock may be reset to any 24-bit quantity including zero by loading A and
then transferring (A) into register 22.
*16,777,216 milliseconds equals approximately 4 hours and 40 minutes.
1-12

Register
Numbers
00-03
04-07
10-13
14-17
20
21
22
23
24-27
30
31
32
33
34-77
PARITY
TABLE 1-3. REGISTER FILE ASSIGNMENTS
Register Function
Modified liD instruction word containing the current character address
(channel 0-3 control)
Temporary storage
Modified 110 instruction word containing the last character address ± 1,
depending on the instruction (channel 0-3 control)
Temporary storage
Search instruction word containing the current character address (search control)
Move instruction word containing the source character address (move control)
Real-time clock, current time
Current character address (typewriter control)*
Temporary storage
Instruction word containing the last character address +1 (search control)
Instruction word containing the destination character address (move control)
Real-time clock, interrupt mask
Last character address +1 (typewriter control)*
Temporary storage
Parity bits are generated and checked in 3100 systems for the following two conditions:
1 Whenever a data word is read from or written into storage.
2 When a data word is transferred via an I/O channel.
Storage Parity
A parity bit is generated and checked for each 6-bit character of a storage word. Refer
to Figure 1-6.
12 11
Parity bit for character 3
Parity bit for character 2
Parity bit for character 1
Parity
bit for character 0
Figure 1-6. Parity Bit Assignments
*The upper 7 bits of registers 23 and 33 should contain zeros.
1-13
06 05 00
3
Rev. B