CyClone COMPACTPCI-810 User manual

The information in this document has been carefully checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, Cyclone Microsystems, Inc. reserves the right to make
changes to any products herein to improve reliability, function, or design. Cyclone Microsystems, Inc. neither
assumes any liability arising out of the application or use of any product or circuit described herein, nor does it
convey any license under its right or the rights of others.
Revision 1.1, June 2001
Cyclone P/N 800-0810
Copyright 2001 by Cyclone Microsystems, Inc.
COMPACTPCI-810
SYSTEM CONTROLLER
USER’S MANUAL
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CONTENTS
PCI-810 User’s Manual i
Revision 1.1, June 2001
CHAPTER 1
1.1 INTRODUCTION..............................................................................................................................1-1
1.2 FEATURES......................................................................................................................................1-2
1.3 OVERVIEW......................................................................................................................................1-3
1.4 SPECIFICATIONS............................................................................................................................1-3
1.5 ENVIRONMENTAL...........................................................................................................................1-4
1.6 PHYSICAL ENVIRONMENT............................................................................................................1-5
1.7 REFERENCE MANUALS.................................................................................................................1-6
CHAPTER 2
2.1 MPC8240 PROCESSOR..................................................................................................................2-1
2.2 BYTE ORDERING............................................................................................................................2-1
2.3 RESET VECTOR..............................................................................................................................2-1
2.4 POWERPC MPC603E CORE CACHE, BUFFERS, ARRAYS.........................................................2-1
2.5 MEMORY MAP.................................................................................................................................2-2
2.6 INTERRUPTS...................................................................................................................................2-3
2.6.1 Shared PMC Interrupts........................................................................................................2-3
2.6.2 MPC8240 Interrupt Registers..............................................................................................2-4
2.6.3 Error Handling and Exceptions............................................................................................2-5
CHAPTER 3
3.1 SDRAM.............................................................................................................................................3-1
3.1.1 Upgrading SDRAM..............................................................................................................3-1
3.1.2 SDRAM Configurations Installation and Removal of Memory Modules..............................3-1
3.2 FLASH ROM.....................................................................................................................................3-2
3.3 CONSOLE SERIAL PORT...............................................................................................................3-2
3.4 COUNTER/TIMERS .........................................................................................................................3-3
3.5 POWER SUPPLY MONITORING....................................................................................................3-3
3.6 FAN MONITORING..........................................................................................................................3-4
3.7 LEDS ................................................................................................................................................3-5
3.8 PCI INTERFACE..............................................................................................................................3-5
3.8.1 Primary PCI Arbitration........................................................................................................3-5
3.8.2 Secondary PCI Arbitration...................................................................................................3-6
3.8.3 DMA Channels....................................................................................................................3-6
3.8.4 Message Unit.......................................................................................................................3-6
3.8.5 JTAG/COP Support.............................................................................................................3-7
3.9 GEOGRAPHIC ADDRESSING ........................................................................................................3-7
3.10 ETHERNET PORTS.........................................................................................................................3-8
3.10.1 82559 Ethernet Controller ...................................................................................................3-8
3.10.2 Ethernet Port LEDs..............................................................................................................3-8
3.10.3 Ethernet Port Connector......................................................................................................3-9
3.11 I2C BUS ............................................................................................................................................3-9
3.11.1 SDRAM EEPROM...............................................................................................................3-9
3.11.2 Temperature Sensors........................................................................................................3-10
3.11.3 Watchdog Timer................................................................................................................3-10
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ii PCI-810 User’s Manual
Revision 1.1, June 2001
3.12 BOARD ID REGISTER...................................................................................................................3-10
CHAPTER 4
4.1 INTRODUCTION..............................................................................................................................4-1
4.2 EMBEDDED UTILITIES MEMORY BLOCK.....................................................................................4-1
4.3 ENDIAN CONSIDERATIONS...........................................................................................................4-2
4.4 PCI CONFIGURATION ....................................................................................................................4-2
4.4.1 pSOS PCI Device Driver Interface......................................................................................4-3
4.5 EPIC INTERRUPT PROGRAMMING...............................................................................................4-3
4.5.1 Connecting and Disconnecting Interrupt Handlers in pSOS................................................4-4
4.6 LM75 TEMPERATURE SENSORS..................................................................................................4-5
APPENDIX A
A.1 INTRODUCTION.............................................................................................................................A-1
A.2 PHYSICAL ATTRIBUTES...............................................................................................................A-1
A.3 PMC MODULE SIGNAL DEFINITIONS ..........................................................................................A-1
A.4 PMC MODULE CONNECTOR........................................................................................................A-2
APPENDIX B
B.1 INTRODUCTION.............................................................................................................................B-1
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CONTENTS
CPCI-810 User’s Manual iii
Revision 1.1, June 2001
LIST OF FIGURES
Figure 1-1. CPCI-810 Block Diagram ....................................................................................................1-1
Figure 1-2. Physical Configuration.........................................................................................................1-5
Figure 2-1. CPCI-810 Memory Map.......................................................................................................2-2
Figure 3-1. POWER SUPPLY #0 STATUS REGISTER (READ ONLY)................................................3-3
Figure 3-2. POWER SUPPLY #1 STATUS REGISTER (READ ONLY)................................................3-4
Figure 3-3. FAN STATUS REGISTER (READ ONLY)...........................................................................3-4
Figure 3-4. LED Register Bitmap, FF20 0000H.....................................................................................3-5
Figure 3-5. MPC8240 Processor DMA Controller..................................................................................3-6
Figure 3-6. COP Header........................................................................................................................3-7
Figure 3-7. Geographic Addressing Register, FF60 0000H...................................................................3-8
Figure 3-8. Watchdog Register, FF10 0000h.......................................................................................3-10
Figure 3-9. Board Identification Registers, FF70 0000h......................................................................3-10
Figure 4-1. Embedded Utilities Memory Block.......................................................................................4-2
Figure 4-2. PCI_LOC Structure Definition..............................................................................................4-3
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iv CPCI-810 User’s Manual
Revision 1.1, June 2001
LIST OF TABLES
Table 1-1. CPCI-810 Power Requirements ..........................................................................................1-4
Table 1-2. Environmental Specifications..............................................................................................1-4
Table 2-1. Serial Interrupt Assignment .................................................................................................2-3
Table 2-2. PMC Module Interrupt Mapping...........................................................................................2-4
Table 2-3. PMC IDSEL Assignments....................................................................................................2-4
Table 2-4. Error Priorities......................................................................................................................2-5
Table 3-1. Console Port Connector......................................................................................................3-2
Table 3-2. UART Register Addresses ..................................................................................................3-2
Table 3-3. 100BaseTx Connector ........................................................................................................3-9
Table 3-4. I2C Device Addresses .........................................................................................................3-9
Table 4-1. CPCI-810 Interrupt Vectors.................................................................................................4-4
Table A-1. PMC Clock & Arbitration Assignment.................................................................................A-1
Table A-2. PMC Interrupt Assignment.................................................................................................A-2
Table A-3. P21 PMC Module Connector Pinout...................................................................................A-2
Table A-4. P22 PMC Module Connector Pinout...................................................................................A-3
Table B-1. CPCI-810 J2 Definition.......................................................................................................B-1
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CPCI-810 User’s Manual 1-1
Revision 1.1, June 2001
CHAPTER 1
GENERAL INTRODUCTION
1.1 INTRODUCTION
The CPCI-810 is a high-performance CompactPCI System Controller. A block diagram is shown in
Figure 1-1.
The board is based on the MPC8240 PowerPCintegrated processor. The MPC8240 has a processor
core based on the PowerPC603elow-power microprocessor, and also performs many peripheral
functions on chip. The peripheral logic integrates a PCI bridge, memory controller, DMA controller,
interrupt controller, I2O controller, and an I2C controller. I/O expansion is provided with a PMC
Module. The PMC Module location allows the CPCI-810 to be configured for custom applications.
Additionally, the CPCI-810 contains two Intelligent 10/100BaseT Ethernet Controllers and can be used
as a processing engine for an embedded systems platform, which requires Ethernet connectivity.
Software development tools for PowerPC processors are available from a variety of vendors, and Board
Support Packages (BSPs) for the PSOS operating system is available from Cyclone.
Figure 1-1. CPCI-810 Block Diagram
PMC
Module
64 to 128
Mbytes
SDRAM
32-bit Secondary PCI Bus
PCI-to-PCI
Bridge
Ethernet
I/F 1
64-bit CompactPCI Bus
MPC8240
Processor
2 Mbytes
Flash ROM
Ethernet
I/F 0
Console
Serial Port
JTAG
I/F Watchdo
g I/F
CPCI Slot 6
CPCI Slot 0
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GENERAL INTRODUCTION
1-2 CPCI-810 User’s Manual
Revision 1.1, June 2001
1.2 FEATURES
•MPC8240 Processor The microprocessor is Motorola’s integrated MPC8240 PowerPC.
The device integrates a Motorola 32-bit superscalar PowerPC 603e
core, running at 250 MHz internally, and a Peripheral Components
Interconnect (PCI). The core boasts a 16 Kbyte instruction cache, a
16 Kbyte data cache and floating-point support. Memory can be
accessed through the memory controller to the core processor or
from the PCI bus.
•21154 PCI-to-PCI Bridge The 21154 has a 64-bit primary bus interface and a 64-bit
secondary interface. The 21154 primary bus interfaces with the 64-
bit CompactPCI bus and the secondary bus interfaces with the 32-
bit PCI bus on the MPC8240. This allows the CPCI-810 to
function as a system controller in a CompactPCI system.
•SDRAM 64 MBytes of SDRAM expandable to 192 MBytes via a 144 pin
SoDIMM running at 100MHz.
•PMC Module The CPCI-810 has one location for a 32-bit PMC Module. The
module can contain I/O interfaces to customize the CPCI-810 for
different applications. The PMC Module resides on the PCI bus of
the MPC8240 and can be accessed by the MPC8240 or a host on
the CompactPCIbus. Devices on the PMC Module can DMA
data into local memory or through the bridge to host memory.
•CompactPCIInterface The CPCI-810 meets the PICMG Rev. 1.0 Specification for system
slot adapters. The PCI bus runs at 33MHz.
•Flash ROM 2 Mbytes of in-circuit sector-programmable Flash ROM.
•Ethernet Ports Two 10/100BaseTx ethernet ports are provided. Each port supports
up to 100Mbps a uses a RJ45 style module phone jack
•Console Serial Port An RS-232 serial port is provided for a console terminal or
workstation connection. The serial port supports up to 115 Kbps
and uses a phone jack to DB25 cable supplied with the CPCI-810
board.
•LM75 Two LM75s are provided for temperature monitoring.
•Fan Monitoring Fan monitoring is provided for two separate fan frequency inputs.
•Timers Four 31-bit timers are available to generate interrupts.
•DMA Controller The MPC8240 supports 2 separate DMA channels for high
throughput data transfers between PCI bus agents and the local
SDRAM memory.
•I2O Messaging The CPCI-810 supports the I
2O specification for interprocessor
communication.
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GENERAL INTRODUCTION
CPCI-810 User’s Manual 1-3
Revision 1.1, June 2001
1.3 OVERVIEW
The CPCI-810 is 6U CompactPCI System adapter card with support for one 32-bit 3.3V signaling PMC
Module. PMC Modules are available from many vendors, including Cyclone and the PMC interface
specification is included in Appendix A for those who wish to design their own PMC Modules.
The CPCI-810 is configured as a System controller board. Therefore, the CPCI-810 provides the
interrupt, arbitration, clocking and reset function for the other (peripheral) adapters in a CompactPCI
system.
The CPCI-810 has two PCI buses. The Primary PCI bus is the CompactPCI bus. The Secondary PCI
bus supports the PMC module and the two Ethernet interfaces.
The primary PCI interface is 64-bit data. The CPCI-810 controller also has a 64-bit data path to
memory. The secondary (local) PCI bus is a 32-bit data connecting to the PMC Module and also to the
32-bit data Ethernet controllers.
The CPCI-810 interfaces to the CompactPCI  bus using an Intel 21154 PCI-to-PCI Bridge. This
device complies with the PCI Local Bus Specification, revision 2.1, provides concurrent bus operation,
allows buffering for both read and write transactions and provides the arbitration for the CompactPCI
bus devices.
The CPCI-810 provides for a number of system hardware monitors. There are two circuits provided to
monitor the health of power supplies. There are also two circuits provided to monitor a frequency
output from two fans. Additionally, two LM75s are provided to monitor temperature.
The Flash ROM on the CPCI-810 can be reprogrammed by software through the JTAG/COP interface.
Utilities to perform this programming are available from software development tool vendors.
Additional information on the JTAG/COP interface can be found in section 3.8.4
1.4 SPECIFICATIONS
Physical Characteristics The CPCI-810 is a single slot, double high CompactPCI  card with a
system slot interface. This product is equipped with an Intel i960
microprocessor and 1 PMC location. The PMC has P3 I/O capability.
Height: 9.187” (233.35mm) Double Eurocard (6U)
Depth: 6.299” (160mm)
Width: .8” (20.32mm)
Power Requirements The CPCI-810 requires +5V, +12V, -12V and +3.3V from the
CompactPCI  backplane J1 connector.
The following figures do not include the power consumption of any PMC Module installed.
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GENERAL INTRODUCTION
1-4 CPCI-810 User’s Manual
Revision 1.1, June 2001
Table 1-1. CPCI-810 Power Requirements
1.5 ENVIRONMENTAL
The CPCI-810 should be operated in a CompactPCI card cage with good air flow. The board can be
operated at ambient air temperature of 0-55 degrees Celsius, as measure at the board.
Table 1-2. ENVIRONMENTAL SPECIFICATIONS
Voltage Current Typical Current Maximum
+3.3V 3.10 Amps 4.30 Amps
+5V 0.128 Amps 0.129 Amps
+12V 0 Amps 0 Amps
-12V 0 Amps 0 Amps
Operating Temperatures 0 to 55 Degrees Celsius
Relative Humidity (non-condensing) 0-95%
Storage Temperatures -55 to 125 Degrees Celsius
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GENERAL INTRODUCTION
CPCI-810 User’s Manual 1-5
Revision 1.1, June 2001
1.6 PHYSICAL ENVIRONMENT
Figure 1-2. Physical Configuration
Figure 1-2 is a physical diagram of the CPCI-810 Adapter, showing the location designators of jumpers,
connectors, and ICs. Refer to this figure when component locations are referenced in the manual text.
1
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GENERAL INTRODUCTION
1-6 CPCI-810 User’s Manual
Revision 1.1, June 2001
1.7 REFERENCE MANUALS
MPC8240 Integrated Processor User’s Manual
Order Number MPC8240UM/D Rev. 0
Motorola Literature Distribution
P.O. Box 5405
Denver, CO 80217
[phone]
PowerPC Microprocessor Family:
The Programming Environments for
32-BIT Microprocessors, Rev. 1
Order Number MPCFPE32B/AD
Motorola Literature Distribution
P.O. Box 5405
Denver, CO 80217
[phone]
TL16C550C UART
Texas Instruments
http://www.ti.com/sc/docs/general/dsmenu.htm
IEEE STD P1386, Draft 2.0
IEEE STD P1386.1, Draft 1.5
Institute of Electrical and Electronics Engineers
PO Box 1331
445 Hoes Lane
Piscataway, NJ 08855-1331
82559 Software Developers Manual
Order Number 743892-002
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
[phone]
LM75 Digital Temperature Sensor and
Thermal Watchdog
National Semiconductor Corporation
1111 West Bardin Road
Arlington, TX 76017
[phone]
CompactPCI  Specification
PCI Industrial Computers Manufacturing Group
301 Edgewater Place, Suite 220
Wakefield, MA 01880
[phone]
[phone] Fax
PCI Local BIOS Specification, Revision 2.1
PCI Special Interest Group
2575 NE Kathryn Street #17
Hillsboro, OR 97214
[phone] (U.S.)
[phone] (International)
[phone] (Fax)
I2O Specification, Revision 1.0
I2O Special Interest Group
[phone]
http://www.i2osig.org
CompactPCI  Hot Swap Specification, PICMG
2.1, R1.0
PCI Industrial Computers Manufacturing Group
301 Edgewater Place, Suite 220
Wakefield, MA 01880
[phone]
[phone] Fax
PMC on CompactPCI  Specification, PICMG
2.3, R1.0
PCI Industrial Computers Manufacturing Group
301 Edgewater Place, Suite 220
Wakefield, MA 01880
[phone]
[phone] Fax
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CPCI-810 User’s Manual 2-1
Revision 1.1, June 2001
CHAPTER 2
MPC8240 PROCESSOR
2.1 MPC8240 PROCESSOR
The MPC8240 contains a PowerPC 603e core processor. The core is configured to run at 250 MHz.
This RISC processor utilizes a superscalar architecture that can issue and retire as many as three instruc-
tions per clock. The core features independent 16 Kbyte, four-way set-associative, physically addressed
caches for instructions and data and on-chip instruction and data memory management units (MMUs).
2.2 BYTE ORDERING
The CPCI-810 is designed to run in big endian mode. The byte ordering determines how the core
accessses local memory and the PCI bus. Big endian stores the most significant byte in the lowest
address.
2.3 RESET VECTOR
The 8-bit wide Flash ROM is located in the address range FFE0 0000h through FFFF FFFFh. See
Figure 2.1, the CPCI-810 memory map. The MPC8240 reset vector is located at address FFF0 0100h.
This reset vector location, which contains a branch to the rest of the boot code, is essentially in the
middle of the ROM device. This positioning results in a break up of continuous memory space and
approximately 50% reduction in usable space for boot code. To better utilize this device, the CPCI-810
re-maps the reset vector to FFE0 0100h by inverting memory address 20 (A20) for the first two
processor accesses to memory. These accesses are an absolute jump instruction to the beginning of boot
code. After this jump A20 functions normally. Utilizing this method the majority of the 2 Mbyte Flash
ROM can be used.
2.4 POWERPC MPC603E CORE CACHE, BUFFERS, ARRAYS
The processor core provides independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory management units
(MMUs). The MMUs contain 64-entry, two-way set associative, data and instruction lookaside buffers
(TLB) that provide support for demand-paged virtual memory address translation and variable-sized
block translation. The processor also supports block address translation (BAT) arrays of four entries
each.
As an added feature to the MPC603e core, the MPC8240 can lock the contentes of one to three ways in
the instruction and data cache (or the entire cache).
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MPC8240 PROCESSOR
2-2 CPCI-810 User’s Manual
Revision 1.1, June 2001
2.5 MEMORY MAP
Figure 2-1 shows the CPCI-810 memory map.
Figure 2-1. CPCI-810 Memory Map
Flash ROM
On-board Devices
PCI INT ACK
PCI Config DATA
PCI Config ADDR
PCI I/O Space
PCI Memory Space
Reserved
DRAM
FF40 0000h
FF50 0000h
FEF0 0000
FEC0 0000
FEE0 0000
4000 0000
FFFF FFFF
FFE0 0000
FF00 0000
FE00 0000
FF30 0000h
FF10 0000h
8000 0000 FF20 0000h
FF60 0000h
0000 0000
FF00 0000h
Board ID Register
(read only)
Geographic Address
(read only)
Fan Status (read only)
Power Supply #1
Status (read only)
Power Supply #0
Status (read only)
LED Register (write only)
Watchdog Timer
UART
FF70 0000h
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MPC8240 PROCESSOR
CPCI-810 User’s Manual 2-3
Revision 1.1, June 2001
2.6 INTERRUPTS
The CPCI-810 interrupt scheme is based upon the MPC8240 processor’s embedded programmable
interrupt controller (EPIC). The EPIC unit is set in the serial interrupt mode. The serial interrupt mode
allows for a maximum of 16 external interrupts. Table 2-1 shows the assignment for the serial
interrupts.
The EPIC interface also contains several internal interrupt sources. These include the four global
timers, the two DMA channels, the I2C bus, and from the Message Unit.
In addition to the EPIC interface, errors detected by the MPC8240 are reported to the processor core by
asserting an internal machine check signal Many of the errors detected in the MPC8240 cause
exceptions to be taken by the processor core. The error reporting is provided for three of the primary
interfaces, processor core interface, memory interface, and the PCI interface.
Table 2-1. Serial Interrupt Assignment
2.6.1 Shared PMC Interrupts
The PMC interrupts, INTA, INTB, INTC, and INTD, are received on serial interrupts 4 through 7. To
remain in compliance with the PCI-to-PCI Bridge Specification, Cyclone has implemented the
following SPCI interrupt mapping scheme.
EPIC Serial Interrupt Interrupt Source Vector Number Polarity
0Primary PCI INTA 0x10 0
1Primary PCI INTB 0x11 0
2Primary PCI INTC 0x12 0
3Primary PCI INTD 0x13 0
4PMC INTA 0x14 0
5PMC INTB 0x15 0
6PMC INTC 0x16 0
7PMC INTD 0x17 0
8Ethernet 0 INT 0x18 0
9Ethernet 1 INT 0x19 0
10 Temperature INT 0x1A 0
11 ENUM 0x1B 0
12 UART INT 0x1C 1
13 Fan INT 0x1D 0
14 Power Supply INT 0x1E 0
15 Not Used 0x1F x
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MPC8240 PROCESSOR
2-4 CPCI-810 User’s Manual
Revision 1.1, June 2001
Each PMC module designed by Cyclone Microsystems follows the interrupt mapping scheme described
in Table 2-2. Note that each PMC interrupt pin is mapped in a different way to both of the two possible
PCI devices on the PMC module. This is to prevent interrupt sharing whenever possible. Users wishing
to design their own PMC modules should follow this convention if they would like to take advantage of
the PSOS driver interrupt dispatch support.
Table 2-2. PMC Module Interrupt Mapping
The IDSEL assignments for each device on the PMC module are described in Table 2-3. IDSEL
Assignments
Table 2-3. PMC IDSEL Assignments
2.6.2 MPC8240 Interrupt Registers
The MPC8240 processor has several different EPIC register maps to facilitate the handling of interrupts
which are briefly mentioned below. These registers occupy a 256 Kbyte range of the embedded utilities
memory block (EUMB) and can be read and written by software. Please refer to the Motorola
MPC8240 User’s manual for more detail.
Global EPIC Registers Provides programming control for resetting, configuration and initial-
ization of the external interrupts. Additionally, a vector register is
provided to be returned to the processor during an interrupt
acknowledge cycle for a spurious vector.
Global Timer Registers Each of the four global timers have four individual configuration
registers. The registers are the Current Count register, the Base Count
register, the Vector/Priority register, and the Destination register.
Interrupt Source This group of registers are made up of the vector/priority and
Configuration destination registers for the serial and internal interrupt sources. This
includes the masking, polarity, and sense.
Processor-Related Registers This group describes the processor-related EPIC registers. They are
made up of the Current Task Priority register, the Interrupt
Acknowledge register, and the End of Interrupt register.
PMC Intpin IDSEL0 Interrupts IDSEL1 Interrupts
INTA INTA INTD
INTB INTB INTA
INTC INTC INTB
INTD INTD INTC
PMC IDSEL Pin PMC IDSEL Assignment
IDSEL0 AD12
IDSEL1 AD13
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MPC8240 PROCESSOR
CPCI-810 User’s Manual 2-5
Revision 1.1, June 2001
2.6.3 Error Handling and Exceptions
Errors detected by the MPC8240 are reported to the processor core by asserting an internal machine
check signal (mpc#). The MPC8240 detects illegal transfer types from the processor, illegal Flash write
transactions, PCI address and data parity errors, accesses to memory addresses out of the range of
physical memory, memory parity errors, memory refresh overflow errors, ECC errors, PCI master-abort
cycles, and PCI received target-abort errors. Table 2-4 describes the relative priorities and recoverablity
of externally-generated errors and exceptions.
Table 2-4. Error Priorities
Priority Exception Cause
0Hard reset Power-on reset, CompactPCI chassis reset switch or via
JTAG controller
1Machine check Processor transaction error, or Flash error
2Machine check PCI address parity error or PCI data parity error when the
CPCI-810 is acting as the PCI target
3Machine check Memory select error, memory refresh overflow, or ECC error
4Machine check PCI address parity error or PCI data parity error when the CPCI-810 is acting as the PCI master, PCI master-abort, or
received PCI target-abort
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CPCI-810 User’s Manual 3-1
Revision 1.1, June 2001
CHAPTER 3
HARDWARE
3.1 SDRAM
The CPCI-810 is equipped with 64 Mbytes of SDRAM. The memory is made up of nine 64 Mbit (8M
x 8) devices. The extra eight bits are for ECC data. Memory may be expanded by adding up to 128
Mbytes of SDRAM to the 144 pin SoDIMM socket for a maximum of 196 Mbytes. The SDRAM is
accessible by the processor and the PCI bus.
The CPCI-810 uses 72-bit SDRAM with ECC or 64-bit SDRAM without ECC. SDRAM memory bus
requires a four-beat data burst. The memory controller unit (MCU) of the CPCI-810 supports SDRAM
burst lengths of four. A burst length of four enables seamless read/write bursting of long data streams
as long as the MCU does not cross the page boundary. Page boundaries are naturally aligned 2 Kbyte
blocks. 72-bit SDRAM with ECC running at 100 MHz allows a maximum throughput of 800 Mbytes
per second.
16 Mbyte, 64 Mbyte, and 128 Mbyte SDRAM devices are supported. The MCU keeps four pages open
simultaneously. Simultaneously open pages allow for greater performance for sequential access,
distributed across multiple internal bus transaction.
3.1.1 Upgrading SDRAM
The CPCI-810 is equipped with 64 Mbytes of SDRAM with ECC mounted on the card. The memory
may be expanded by inserting an additional 16 Mbyte to 128 MByte module into the 144 pin SoDIMM
socket. Only 144 pin +3.3V SDRAM modules with or without ECC rated for 100 MHz operation
should be used on the CPCI-810.
3.1.2 SDRAM Configurations Installation and Removal of Memory Modules
Installation or removal of DIMMs on the CPCI-810 is a simple procedure and requires no special tools.
The CPCI-810 should be removed from the host system before its memory configuration is changed,
and care must be taken to avoid static discharge while contacting the board. A properly connected
grounding strap should be worn while installing or removing memory modules on the CPCI-810
adapter.
Memory modules are removed by rotating the latches located on each end of the SoDIMM socket
outward, away from the module. As the latches are moved outward, the module will be ejected from the
socket.
To install a memory module, first identify its proper orientation. Each module is keyed with a pair of
notches in the card edge of the PC board that correspond to tabs in the socket. With the correct
orientation established and the latches in their outward position, begin to slide the module into the
socket. The two card edge corners of the module mate with the slots in each latch first. By pressing the
module and socket together, the module should snap into the socket. Check that the latches are in their
fully closed (inward) position.
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HARDWARE
3-2 CPCI-810 User’s Manual
Revision 1.1, June 2001
3.2 FLASH ROM
The CPCI-810 provides 2 Mbytes of sector-programmable Flash ROM for non-volatile code storage.
The Flash ROM is located in local memory space at address FFE0 0000h through FFFF FFFFh. The
mapping ensures that, after a reset, the MPC8240 processor can execute the hard reset exception handler
located at FFF0 0100h.
3.3 CONSOLE SERIAL PORT
A single console serial port with an RS-232 line interface has been included on the CPCI-810. The port
is connected to a RJ-11 style phone jack on the adapter, and can be connected to a host system using the
included phone jack to DB-25 cable (Cyclone P/N 530-2006). The pinout of the console connector is as
shown in Table 3-1.
Table 3-1. Console Port Connector
The serial port is based on a 16C550 UART clocked at 1.843 MHz. The device may be programmed to
use this clock with the internal baud rate counters. The serial port is capable of operating at speeds from
300 to 115200 bps, and can be operated in interrupt-driven or polled mode. The 16C550 register set is
shown in Table 3-2. For a detailed description of the registers and device operation refer to the 16C550
databook.
Table 3-2. UART Register Addresses
Pin Signal Description
1Not Used
2GND Ground
3TXD Transmit Data
4RXD Receive Data
5Not Used
6Not Used
Address Read Register Write Register
FF00 0000H Receive Holding Register Transmit Holding Register
FF00 0008H Unused Interrupt Enable Register
FF00 0010H Interrupt Status Register FIFO Control Register
FF00 0018H Unused Line Control Register
FF00 0020H Unused Modem Control Register
FF00 0028H Line Status Register Unused
FF00 0030H Modem Status Register Unused
FF00 0038H Scratchpad Register Scratchpad Register
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CPCI-810 User’s Manual 3-3
Revision 1.1, June 2001
3.4 COUNTER/TIMERS
The MPC8240 processor is equipped with four 31-bit on-chip counter/timers which count at 1/8 the
frequency of the SDRAM_CLK signal or 12.5MHz. Users should refer to the Processor User’s Manual
for the functionality and programming of the counters. The timers can be individually programmed to
generate interrupts to the processor when they count down to zero. Two of the timers, timer2 and
timer3, can be set up to automatically start periodic DMA operations for DMA channels 0 and 1,
respectively, without using the processor interrupt mechanism.
3.5 POWER SUPPLY MONITORING
Two circuits are provided for monitoring the health of power supplies. Additional inputs to the
CompactPCI connector define pins for degraded, failed and detected power supplies. The definition for
the CompactPCI connector J2 is provided in Appendix B. A failed or degraded power supply, as long
as it is detected, will cause an interrupt to the processor. Additionally, the state of the power supply as
defined by POWERGOOD, i.e. the power supply is neither degraded or failed, is displayed in a green
LED. Figures 3-1 and 3-2 show the register bit definition for the two power supply status registers.
Figure 3-1. POWER SUPPLY #0 STATUS REGISTER (READ ONLY)
PS0 Failed (1)
PS0 Detected
PS0 Degraded
(Read Only)
76543210
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HARDWARE
3-4 CPCI-810 User’s Manual
Revision 1.1, June 2001
Figure 3-2. POWER SUPPLY #1 STATUS REGISTER (READ ONLY)
3.6 FAN MONITORING
Two circuits are provided for the monitoring of two fan frequencies inputs. As in the case of the power
supply monitoring signals, additional inputs to J2 have been defined for the two fan inputs. Refer to
Appendix B for their pin locations. The fan monitoring circuits will provide an interrupt to the
processor if the frequency of the fan output falls below approximately 8K RPM. Green LEDs are
provided for fan interrupt status. If a fan frequency input causes an interrupt, the corresponding LED is
turned off. Figure 3-3. shows the register bit definition for the fan status register.
Figure 3-3. FAN STATUS REGISTER (READ ONLY)
PS1 Failed (1)
PS1 Detected
(Read Only)
76543210
Fan 0
Fan 1
(Read Only)
(1) Failed
76543210
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