Dynatem CPU-71-10 User manual

USER MANUAL
CPU-71-10 (DPD/RPD/XPD)
VMEbus Intel® Core™ Duo
Single Board Computer
DPDMAN103A U
p
dated 14 Dec 2012

CPU-71-10 (XPD) User’s Manual Rev. 1.03
Revised to fix JP8 description
December 2012
Dynatem
23263 Madero, Suite C
Mission Viejo, CA 92691
Phone: [phone]
Fax: [phone]
www.dynatem.com

Dynatem CPU-71-10 (XPD) VMEbus Core 2 Duo Processor Board – User’s Manual i
Table of Contents
1. Features 1
2. Related Documents 3
3. Hardware Description 5
3.1 Overview 5
3.2 Processor 6
3.3 Chipset 6
3.4 DRAM 7
3.5 Intel 82571EB Dual Gigabit Ethernet Controller 7
3.6 Silicon Motion SM712 Graphics Processor 8
3.7 Tundra Universe IID CA91C142D PCI-VMEbus Interface 9
3.8 PCI Mezzanine Card (PMCX) and XMC Expansion 12
3.9 Intel’s FW82802A Firmware Hub Holds the System BIOS In Flash Memory 12
3.10 Clock Drivers 12
3.11 Reset Circuitry 13
3.12 Watchdog Timer Operation 14
4. Installation 15
4.1 Jumper Selectable Options 15
4.2 CompactFlash Drive Installation 17
4.3 PCI Mezzanine Card (PMC) Installation 17
4.4 VMEbus Chassis Installation 17
4.5 Front Panel Connectors and Reset Switch 18

ii CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
A. Connector Pin-outs 19
A.1 Front Panel USB Connector (USB1 & USB2) 20
A.2 1000BaseTX Fast Ethernet Front Panel Connector (J1) 20
A.3 CompactFlash Interface Connector (J3) 21
A.4 VMEbus Connectors (P1, P2, and P0) 22
A.5 PCI-X Mezzanine Card Connectors (JN1, JN2, JN3, and JN4) and XMC Connector (J15) 25
B. BIOS & Setup 31
B.1 Redirecting to a Serial Port 31
B.2 Setup Menus 31
B.3 Navigating Setup Menus & Fields 32
B.4 Main Setup Menu 33
B.5 Exit Setup Menu 34
B.6 Boot Setup Menu 35
B.7 POST Setup Menu 37
B.8 PnP Setup Menu 39
B.9 Super I/O (SIO) Setup Menu 40
B.10 Features Setup Menu 41
B.11 Firmbase Setup Menu 42
B.12 Miscellaneous Setup Menu 44
C. Power and Environmental Requirements 47
D. XPDPTB Rear Plug-in I/O Expansion Module for the XPD 49
D.1 XPDPTB Connector Pin-outs 50

Chapter 1 – Features
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 1
1. Features
The CPU-71-10 (also known as the XPD / DPD / RPD) is a single-slot 6U VMEbus Single Board Computer (SBC).
The XPD offers full PC performance with a Core Duo processor. The XPD is available in two versions: the lower
cost DPD for standard industrial applications and the 1101.2 compliant, conduction-cooled RPD with wedgelocks,
stiffener bar, and a full board heatsink for rugged applications. When referring to attributes of both versions, we
will use the common name XPD. The XPD employs Intel’s embedded technology to assure long-term availability.
Features of the XPD include:
A 1.5 GHz Intel® Core2™ Duo L7400 processor with 4 MB of L2 cache
Single-slot VMEbus operation with on-board CompactFlash disk for bootable mass storage and front panel
connectors for two USB 2.0 ports, two Fast Ethernet ports, and XPD & PMC I/O
An IDE port, four RS232 COM ports, PS/2 Mouse & Keyboard, two USB ports, and PMC I/O are routed out to
the backplane via the P2 connector
Two Serial ATA ports, VGA graphics, two Gbit Ethernet ports (Vita 31.1 compliant) and PMC/XMC I/O are
routed to the P0 connector

Chapter 1 – Features
2 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
The Intel® E7520 Memory Controller Hub (MCH) and Intel® 6300ESB I/O Controller Hub (ICH) provide
high-speed memory control, 16 lanes of PCI Express I/O, integrated I/O like Serial ATA, USB 2.0, IDE
supporting Ultra 100 DMA Mode for transfers up to 88.88 MB/sec, and 64 bit PCI-X bus transfers at 66 MHz
Silicon Motion’s SM712 VGA Controller
Two Intel 82571EB Ethernet Controllers with a x4 PCI Express interface, each offering two
10/100/1000BaseTX support; two ports are routed to P0 in compliance with Vita 31.1 for backplane fabric
switching while the other two are routed to the front panel
4 GB of DDR2-400 DRAM provided on-board
Tundra Universe IID PCI-VMEbus Interface provides 64-bit VMEbus transfer rates over 30 MB/sec. Integral
FIFOs permit write-posting to maximize available PCI and VMEbus bandwidth. Full Slot 1 (System
Controller) functionality is provided
PCI Mezzanine Card (PMC) expansion supports 64 bits @ up to 66 MHz
A second PCI Mezzanine Card (PMC) expansion supports 64 bits @ up to 66 MHz and can also support an MC
module with up to x8 PCI Express
Secondary IDE port for CompactFlash on-board for flash-based or mechanical mass storage for 1 slot booting
General Software’s Version 6.0 flash-based system BIOS
PXE for diskless booting over Ethernet
Programmable watchdog timer for system recovery and a CPLD for LED control, Geographical Addressing,
and Built-In Test (BIT) status and control
Operating System (OS) and driver support, including Windows NT, Embedded NT, XP, QNX, VxWorks,
Linux, Solaris, and pSOS+.

Chapter 2 – Related Documents
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 3
2. Related Documents
Listed below are documents that describe the Pentium processor and chipset, and the peripheral components used on
the XPD. Either download from the Internet or contact your local distributor for copies of these documents.
The XPD uses the L2400 Low Voltage Core Duo. For information on this processor, go to:
http://ark.intel.com/products/28026?wapkw=l7400
For the ICH component in the 6300ESBchipset get the Intel ® 6300ESB I/O Controller Hub Datasheet. It is document
number 300641-002.
ftp://download.intel.com/design/intarch/datashts/30064102.pdf
For information on the E7520 MCH component in the chipset, please go to:
http://www.intel.com/design/chipsets/embedded/e7520_7320.htm
For data sheets on I/O controllers:
82571EB Fast Ethernet PCI Controller
http://www.intel.com/design/network/products/lan/controllers/82571eb.htm
VMEbus Interface Components Manual
Tundra Semiconductor Corporation; Universe IID revisions are found at www.tundra.com
The following documents provide information on the PC architecture and I/O:
PCI Local Bus Specification, Revision 2.2
http://www.pcisig.com/specifications/
PCI-X Specification, Revision 1.0A
http://www.pcisig.com/specifications/
System Management Bus Specification (SMBus), Revision 1.1
http://www.smbus.org/specs/
Universal Serial Bus Specification
http://www.usb.org/developers
The following documents cover topics relevant to the VMEbus and can be purchased through VITA:
IEEE Std 1014-1987, IEEE Standard for a Versatile Backplane Bus: VMEbus
The Institute of Electrical and Electronic Engineers
345 East 47th Street
New York, NY 10017
[phone]
Wade D. Peterson, The VMEbus Handbook
VITA
10229 North Scottsdale Road, Suite B
Scottsdale, AZ 85253
[phone]

Chapter 2 – Related Documents
4 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
The following documents are the current draft standards for the PCI Mezzanine Card (PMC) and XMC cards:
IEEE Draft Std P1386/2.0, Draft Standard for a Common Mezzanine Card Family: CMC
The Institute of Electrical and Electronic Engineers
345 East 47th Street
New York, NY 10017
[phone]
IEEE Draft Std P1386.1/2.0, Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards:
PMC
The Institute of Electrical and Electronic Engineers
345 East 47th Street
New York, NY 10017
[phone]
VITA 42.0, XMC Switched Mezzanine Card Auxiliary Standard
VITA
10229 North Scottsdale Road, Suite B
Scottsdale, AZ 85253
[phone]

Chapter 3 – Hardware Description
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 5
3. Hardware Description
3.1 Overview
The block diagram of the XPD is shown below. The sections that follow describe the major functional blocks of the
XPD.

Chapter 3 – Hardware Description
6 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
3.2 Processor
The XPD supports a Core Duo processor at 1.66 GHz. The Intel Core Duo processor with 2 MB of L2 cache is the
first dual core processor available for mobile and embedded applications. Features include:
667 MHz front side bus (limited by the E7520 FSB).
On-die 4 MB of L2 cache with Advanced Transfer Cache Architecture.
On-die, primary 32-KB instruction cache and 32-KB write-back data cache.
Second-generation Streaming SIMD Extensions 2 (SSE2) and streaming SIMD Extensions 3 (SSE3)
Supports Intel® Architecture and Dynamic Execution.
For further information on the Core2 Duo processor available from Intel Corporation, search at:
http://ark.intel.com/products/28026?wapkw=l7400
The Intel® Core™ Duo processor was designed to deliver high, dual processor high performance with low power
consumption. With its 65 nm processing technology and 2 MB of L2 advanced transfer cache, the Core Duo offers
more performance per Watt. The Thermal Design Power (TDP) is 15 W. Advanced power management included
Enhanced Intel SpeedStep Technology are supported. SpeedStep enables clock and core voltage throttling based on
temperature or processor loading.
The processor’s 667 MHz Front Side Bus utilizes a split-transaction, deferred reply protocol. The FSB uses a
Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per
bus clock. The address bus can deliver addresses twice per clock cycle. Together, the 4X data bus and 2X address
bus provide a data bus bandwidth of up to 5.33 GB/second.
3.3 Chipset
The Intel® E7520 Memory Controller Hub (MCH) and Intel® 6300ESB I/O Controller Hub (ICH) chipset provide
memory control, mass storage and basic I/O, and standard PC system resources including the real time clock, NV-
RAM, timers, thermal management, and interrupt management. Also, the MCH provides 24 lanes of PCI Express
expansion (16 of which are implemented on the XPD) for high-speed expansion through the two dual 1000BaseTX
controller chips and the XMC site.. The ICH supports a 32 bit @ 33 MHz PCI bus, to support the Universe
VMEbus interface controller and the Silicon Motion SM712 graphics chip, and a 64 bit @ 66 MHz PCI-X bus for
user I/O expansion through the two PMC sites. The ICH also provides a Low Pin Count (LPC) interface for the
BIOS flash chip and for Super I/O and an SMBus interface for on-board resources like the DRAM circuit’s SPD
PROMs and the thermal monitors.
The MCH supports a base system bus frequency of 200 MHz. The address and request interface is double pumped
to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz. This provides a matched system
bus address and data bandwidth of 6.4 GB/s. The E7520 (MCH) provides a 400 MHz interface to DDR2 RAM (72
bits wide with ECC). The XPD can be populated with one or two banks of DRAM for 2 GB or 4 GB of total
memory respectively. Each bank is serviced by a separate channel from the MCH that function in lock-step mode.
Memory controller features include:
Memory mirroring allows for two copies of all data in the memory subsystem (one on each channel) to be
maintained.
Hardware periodic memory scrubbing, including demand scrub support.

Chapter 3 – Hardware Description
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 7
Retry on uncorrectable memory
ECC is supported
DDR2-400 DRAM is supported on-board
The 6300ESB I/O Controller Hub (ICH) provides most of the XPD’s on-board I/O and it’s the XPD’s PCI-X
expansion bridge. The ICH is designed as a low-power, high-performance I/O hub that features:
64-bit @ 66 MHz PCI-X expansion that is used on the XPD for the two on-board PMC-X slots.
Four USB 2.0 compliant ports: two of which are routed to the front panel while the other twoare routed to
the P2 connector to the backplane.
Integrated IDE controller supports Ultra 100 DMA Mode Transfers up to 100 MB/sec read cycles and
88.88 MB/sec write cycles for a CompactFlash drive on-board and a primary IDE port that is routed
through P2 to the XPDPTB
Two Serial ATA ports providing 150 MB/sec data rates are routed through P0
Standard PC functionality like a battery-backed RTC and 256-bytes of CMOS RAM, Power Management
Logic, Interrupt Controller, Watchdog Timer, AC’97 CODEC, Integrated 16550 compatible UART’s, and
multimedia timers based on the 82C54
For further information, see the documents referenced in Section 2
3.4 DRAM
The XPD supports two 72-bit wide, DDR2-400 memory interface channels with a memory bandwidth of 6.4 GB/s
with ECC. The XPD can be populated to support 2GB or 4GB of DRAM.
3.5 Intel 82571EB Dual Gigabit Ethernet Controller
The XPD supports two Intel® 82571EB Gigabit Ethernet Controllers, one provides two Vita 31.1 compliant Gigabit
LAN ports to the backplane while the other provides two that are accessible from the front panel. The 82571EB is a
single, compact component with two fully integrated Gigabit Ethernet Media Access Control (MAC) and physical
layer (PHY) ports. This device uses the PCI Express* architecture (Rev. 1.0a), and also enables a dual-port Gigabit
Ethernet implementation in a very small area, which is useful for embedded designs with critical space constraints.
The Intel 82571EB Gigabit Ethernet Controller provides two IEEE 802.3 Ethernet interfaces for 1000BASE-T,
100BASE-TX, and 10BASE-T applications. In addition to managing MAC and PHY Ethernet layer functions, the
controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers.
The Intel 82571EB Gigabit Ethernet Controller for PCI Express is designed for high performance and low memory
latency. The device is optimized to connect to the E7520 MCH using four PCI Express lanes. Alternatively, the
controller can connect to an Input/Output (I/O) Control Hub (ICH) that has a PCI Express interface. Wide internal
data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a
parallel and pipelined logic architecture optimized for Gigabit Ethernet and for independent transmit and receive
queues, the controller efficiently handles packets with minimum latency. The controller includes advanced interrupt-
handling features and uses efficient ring-buffer descriptor data structures, with up to 64 packet descriptors cached
on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition, using
hardware acceleration, the controller offloads tasks from the host, such as checksum calculations for transmission
control protocol (TCP), user datagram protocol (UDP), and Internet protocol (IP); header and data splitting; and
TCP segmentation.

Chapter 3 – Hardware Description
8 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
The Intel 82571EB offers the following features:
10, 100, and 1000BaseTX support with auto-negotiation
Uses x4 PCI Express from MCH
Dual 48 KB configurable RX and TX packet FIFOs
Built-in Phyceiver
Serial EEPROM for non-volatile Ethernet address storage
Both 10/100/1000BaseTX ports of one 82571EB device are brought out to the P0 backplane connector in
compliance with the VITA 31.1 specification. VITA 31.1permits fabric switching on the backplane where 31.1
compliant SBC’s can communicate with each other and with an external network through switch modules that are
located at either end of the backplane. Optionally these two 1 Gb Ethernet ports are brought to industry standard
RJ-45 connectors on Dynatem’s rear I/O plug-in module (XPDPTB).
The two Ethernet ports provided by the DPD’s 2nd 82571EB are accessible from the front panel.
Technical documents on Intel’s 82571EB Dual Gigabit Ethernet Controller are available at:
http://www.intel.com/design/network/products/lan/docs/82571eb_docs.htm
3.6 Silicon Motion SM712 Graphics Processor
The Silicon Motion SM712 processor generates VGA graphics which are routed to the P0 backplane connector. A
VGA connector is provided by the optional XPDPTB rear-I/O module.
The SM712’s features include:
Up to 1280x1024 or higher resolution with programmable PLL (SM712 up to 1024x768)
128-bit 2D graphic engine
4MB embedded SDRAM
The SM712 offers low power graphics for limited GUI purposes. It attaches to the system via the ICH’s 32 bit @
33 MHz PCI bus.
Silicon Motion SM712 Signal PCI Bus Connection
Bus PCI
IDSEL AD17
REQ# REQ1#
GNT# GNT1#
INTR# INTB#

Chapter 3 – Hardware Description
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 9
3.7 Tundra Universe IID CA91C142D PCI-VMEbus Interface
The PCI-VMEbus interface, based on the Tundra Universe IID CA91C142D, offers the following features:
High-performance 64-bit VMEbus interface.
Integral FIFOs for write-posting allow the Universe IID to quickly relinquish the bus.
Programmable DMA controller with linked list support.
Full VMEbus system controller functionality.
Complete VMEbus address and data transfer modes: A32/A24/A16 master and slave; D64
(MBLT)/D32/D16/D08 master and slave.
The block diagram of the PCI-VMEbus interface is shown below:
PCI-VMEbus Interface Block Diagram
VMEbus P1 Connector
VMEbus P2 Connector
Reset Circuitry I/O Controller Hub ICH
Universe IID
CA91C142D
Buffers
Buffers
Buffers
Buffers
Buffers
IRQx*, BRx*
AM0* – AM5*
AS, DS0*, DS1*, Ctrl
D00 – D31
A01 – A31, LWORD*
Low Pin Count (LPC) Bus
IDE
PCI Bus
VMEbus
P2 User Defined Pins
IDSEL is
AD19 INTG#, REQ1#, GNT1#
AD[31:0]

Chapter 3 – Hardware Description
10 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
As shown in the block diagram, several peripheral signals are routed to the user-defined pins of the VMEbus P2
connector: the IDE bus and the LPC bus which routes to a Super I/O chip on the XPDPTB rear plug-in card for I/O
expansion. The VMEbus P1 and P2 connector pin-outs are given in Appendix A.
The Universe IID CA91C142D can act as a PCI bus initiator (master) or target (slave), and a VMEbus master or
slave. The Universe IID is capable of generating interrupts on the VMEbus, and can act as a VMEbus interrupt
handler. The Universe IID provides full VMEbus system controller functionality. The XPD reset circuitry is tied to
the Universe IID, since the XPD can generate the VMEbus SYSRESET* signal as well as be reset by another
VMEbus board that asserts the SYSRESET* signal. The XPD reset circuitry is discussed in detail in Section 3.12.
This section is intended to supplement the VME-to-PCI Bus Bridge Manual User Manual (downloadable from
www.tundra.com), which contains comprehensive descriptions of the operation and programming of the Universe
IID. That manual provides the necessary information to understand the operating modes of the Universe IID:
XPD-initiated transfers (PCI slave, VMEbus master).
Other VMEbus master-initiated transfers (PCI master, VMEbus slave).
DMA controller transfers (PCI master, VMEbus master).
VMEbus interrupt generation.
VMEbus interrupt handling.
System controller functionality.
Register programming via the PCI bus and the VMEbus.
Coupled and uncoupled transfers between the PCI bus and the VMEbus.
4 mailboxes and 8 semaphores.
VMEbus arbitration.
The Universe IID Control and Status Registers (UCSRs) are used for the configuration of the Universe IID. These
registers form a 4 KB block, divided into three groups:
PCI Configuration Space (PCICS).
Universe IID Device Specific Status Registers (UDSRs).
VMEbus Control and Status Registers (VCSRs).
These registers are accessible (to varying degrees) via three address spaces:
PCI Configuration Space – Only the PCICS register block is accessible in this space.
PCI Memory Space – The entire 4 KB UCSR block is accessible in this space.
VMEbus A32/A24/A16 Space – The entire 4 KB UCSR block is accessible in this space.

Chapter 3 – Hardware Description
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 11
During initialization, the system BIOS maps PCI peripherals that require space beyond the PCI configuration space
into the memory space or I/O space. The Universe IID UCSR block is 4 KB in size and must be aligned on a 64 KB
boundary. The total I/O space of an Intel processor is 64 KB and many of the common PC peripherals are found in
the first 1 KB of this space. Thus, a request for a 64 KB block of I/O space for the Universe IID registers would be
denied by the system BIOS, leaving the Universe IID unmapped. To avoid this situation, the Universe IID offers a
power-up option to map its registers into the memory space. This is accomplished on the XPD by tying the VA[1]
line high via a pull-up resistor.
There are two mechanisms to access the UCSR block from the VMEbus. The first is the VMEbus Register Access
Image (VRAI) method, which is defined by the following registers in the Universe IID User’s Manual:
Field Register Bits Description
Address Space VAS in Table A.76 A32, A24, or A16
Base Address BS[31:12] in Table A.77 Lowest address in the 4 KB slave image
Slave Image Enable EN in Table A.76 Enable VMEbus Register Access Image
Mode SUPER in Table A.76 Supervisor and/or Non-Privileged
Type PGM in Table A.76 Program and/or Data
The reset state of the VAS, BS[31:12], and EN fields can be configured as power-up options. On the XPD, all of
these fields reset to 0. Thus, the VRAI method must be configured and enabled by accessing the Universe IID
registers in the memory space.
The second mechanism for accessing the UCSR block from the VMEbus is the CS/CSR method, which is defined
by the following registers in the Universe IID section of the User’s Manual:
Field Register Bits Description
Base Address BS[23:19] in Table A.84 Base address of Universe IID 512 KB slot
Slave Image Enable EN in Table A.78 Enable CS/CSR image
The BS[23:19] and EN fields reset to all 0s, and the EN bit can be set by the VME64 Auto ID process. Thus, the
CR/CSR method must be configured by accessing the Universe IID registers in the memory space.
The PCI signals specific to the Tundra Universe IID CA91C142D are routed from the PCI bus of the ICH and they
are shown below:
Tundra Universe IID CA91C142D
Signal PCI Bus Connection
Bus PCI
IDSEL AD16
REQ# REQ0#
GNT# GNT0#
LINT0# INTA#
LINT1# Pulled Up

Chapter 3 – Hardware Description
12 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
3.8 PCI-X Mezzanine Card (PMCX) and XMC Expansion
The XPD supports two PCI-X Mezzanine Card (PMC-X) sites on-board. Site #1 also supports x8 XMC cards. Site
#1 routes I/O from J14 out through the P2 connector (please see Appendix A) or it can be accessed from the front
panel. Site #2 routes I/O from J24 to the P0 backplane connector and/or to the front panel.
3.9 Intel’s FW82802AC Firmware Hub Holds the System BIOS In Flash Memory
The Intel FW82802AC uses a 5-pin interface and provides 1 MByte of flash memory for the system BIOS. This
device can fill the 1 MB real mode memory map so only a portion its upper 256 MB is used. The FW82802AC’s 1
MB of memory space is segmented into sixteen parameter blocks of 64 KB each. The XPD powers up into real
mode and the BIOS is eventually shadowed into system DRAM after booting through the BIOS.
The ICH provides the 5-pin interface to the E82802AC. The upper 256 KB of the E82802AC is located from
000C0000 - 000FFFFF and its full 1 MB of memory is aliased from FFF00000 – FFFFFFFF where it can be fully
accessed after booting up through the BIOS.
Here’s a link to a datasheet for the 82802AC:
ftp://download.intel.com/design/chipsets/datashts/29065804.pdf
3.10 Clock Drivers
The clock driver circuitry is shown below:
The clocks are generated by the 932S208, which is driven by a 14.31818 MHz crystal. DRAM clocks are
synthesized by the MCH and Hub Interface and PCI(-X) clocks are produced by the ICH. A 32.768 KHz Crystal
drives the Real Time Clock (RTC) on the ICH. The Fast Ethernet port provided to the front panel by the 82571EB
and the two 1 Gb Ethernet ports provided to the backplane by the 82571EB require separate 25.0 MHz oscillators
(one of the two oscillators is also used for the watchdog timer clock). A 64.0 MHz oscillator drives the Universe
IID CA91C142D VMEbus circuitry.
Clock Driver Circuitry
14.31818 MHz
Crystal
32.768 KHz
Crystal
48 MHz
Routed to ICH for
USB and UART’s and
to the MCH for
Graphics
932S208
To ICH for
Real Time
Clock
To ICH for USB & Serial
To MCH for dot clocks
64.0 MHz
Oscillator To Universe
IID CLK64
Two 25.0 MHz
Oscillators
To Ethernet
Controllers
82571EB &
82571EB and
To MCH for SDRAM Clocks
100 MHz differential
clocks for MCH, ICH,
ITP, & CPU clocks ICH
ITP Port
Core Duo CPU

Chapter 3 – Hardware Description
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 13
3.11 Reset Circuitry
The reset circuitry is shown below:
Reset Circuitry
DS1232
ICH
Universe IID CA91C142D
VME_RESET#
RST#
VCSR_CLR[RESET]
VCSR_SET[RESET]
MISC_CTL[SW_LRST]
MISC_CTL[SW_SYSRST]
PWRRST#
VRSYSRST#
VXSYSRST
LRST#
Pull-up
Front Panel Reset Switch
+5 VDC Monitor
Reset Registers,
State Machines
Core Duo “soft” reset
PCI peripherals
Core Duo “hard” reset
VMEbus
SYSRESET
INIT
PCIRST#
SYSRESET#
Reset Control Register
PB1
General Purpose Output
Re
g
ister’s GPIO20
Watchdog
Strobe
NAND Gate
WDT
_
CLKEN
JP4
14.318 MHz
Clock
Open Drain
Buffer
3.3V Reset
Vcore
Monitor
PWRGD
_
VR
JP2
LTC1778

Chapter 3 – Hardware Description
14 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
There are eight ways to perform a hard reset of the XPD:
The DS1232 senses that the +5 VDC supply has dropped too low, asserting a PWROK signal to the ICH. This
signal resets the processor and the Chipset and, ultimately, all PCI and PCI-X peripherals. The output of the
DS1232 runs through the Universe IID (If the board is delivered without the VMEbus interface circuitry (the
XPD) this path is replaced with a bypass 0 ohm resistor).
A DS1233 monitors the on-board 3.3 VDC, regulated from the 5.0 VDC off the backplane, and provides
proper power sequencing for the CPU.
The local on-board voltage regulator for the CPU’s core voltage will generate a reset if its output voltage is out
of range through signal PWRGD_VR.
The front panel reset switch, PB1, is pressed, which also asserts a PWROK signal from the DS1232 and resets
the XPD.
Another VMEbus board asserts SYSRESET*, which asserts the Universe IID VRSYSRST# input and, if
Jumper SW1-1 is closed, will reset the XPD.
The SW_SYSRST bit in the MISC_CTL register of the Universe IID is set by code running on the XPD
processor. This asserts the VMEbus SYSRESET* signal if SW1-2 is closed. If SW1-1 is open the XPD can
reset the VMEbus without resetting itself.
The SW_LRST bit in the MISC_CTL register of the Universe IID is set by code running on the XPD processor.
This performs a local hard reset, via signal LRST#, of the XPD board circuitry. If SW1-2 is open LRST# will
reset the XPD without asserting a VMEbus SYSRESET* signal.
Another VMEbus master sets the RESET bit in the VCSR_SET register of the Universe IID over the VMEbus.
In this case the LRST# signals remains asserted until the RESET bit of the VCSR_CLR register of the Universe
IID is set by another VMEbus master over the VMEbus.
The Reset Control Register in the ICH can be set appropriately by code running on the XPD processor.
Let the watchdog timer time out; see Section 3.12 below.
For further information on the peripherals that play a part in the reset circuitry, refer to ICH datasheet that’s
referenced in Section 2.
3.12 Watchdog Timer Operation
The XPD’s DS1232 if the watchdog timer is enabled and times out.
The XPD’s watchdog timer is controlled by one general-purpose output line (GPIO20) that is asserted by the ICH.
The DS1232 has a strobe input pin that must see an active clock. If no clock pulse is generated to the pin within
500 milliseconds, the entire XPD board will be reset. As long as GPIO20 is high, a 14.31818 MHz clock will be
present at the strobe input.
To use the watchdog timer, drive GPIO20 low, thereby turning off the 14.31818 MHz clock to the DS1232’s strobe
input, and write a software routine that will bring GPIO20 high before 500 milliseconds elapses. GPIO20 is
controlled by bit 20 in the ICH’s GP_LVL register. GPIO20 reflects the status of bit 20: GPIO20 is high if bit 20 is
at logic 1 and it is low if bit 20 is at logic 0. GPIO20 is high at reset so the watchdog timer will only be activated
when the user drives bit 20 of the GP_LVL register low. For instructions on programming the GP_LVL register,
refer to the Intel® 6300ESB I/O Controller Hub Data Sheet from Intel Corporation, Document # 300641-002.

Chapter 4 – Installation
CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual 15
4. Installation
The following sections cover the steps necessary to configure the XPD and install it into a VMEbus system for
single-slot operation. This chapter should be read in its entirety before proceeding with the installation.
4.1 Selectable Options
This section explains how to set up user configurable jumpers and how to install CompactFlash drives and PMC
modules.
The XPD is shipped in an antistatic bag. Be sure to observe proper handling procedures during the configuration
and installation process, to avoid damage due to electrostatic discharge (ESD).
The XPD contains eight jumpers. JP3 is located near JN1 for the second PMC site. Jumpers JP1 through JP8
(minus JP3) are arranged in order as shown below:
PMC/XMC Site 1 PMC Site 2
CompactFlash Drive
JP1JP3 JP8

Chapter 4 – Installation
16 CPU-71-10 (XPD/RPD/DPD) VMEbus Core 2 Duo Processor Board – User’s Manual
The XPD offers a number of user configurable hardware options.
Jumpers Description
JP1 VMEbus Slot 1 Controller when open
JP2 XPD drives SYSRESET to the VMEbus when closed
JP3 Determines VIO for the two PMC sites (1 – 2 for 3.3 VDC; 2 – 3 for 5.0 VDC)
JP4 XPD is reset by the VMEbus SYSRESET when closed
JP5 Close momentarily to flush RTC and NV-RAM and revert to BIOS defaults
JP6 Bit Control 1 (grounded when shunted)
JP7 Bit Control 0 (grounded when shunted)
JP8 MUST STAY OPEN (on-board BIOS is disabled when closed)
SW2-1 through SW2-4 DDC Routing for DVI-I Interface (set at the factory)
JP2 lets an XPD SYSRESET reset the VMEbus when closed. When open, the XPD cannot drive a SYSRESET to
other modules on the VMEbus. The Universe IID only drives SYSRESET when the XPD is a Slot 1 Controller.
VMEbus SYSRESET Out Selection JP2
XPD Won’t Drive SYSRESET to the VMEbus Open
XPD Drives SYSRESET to the VMEbus Closed
VMEbus SYSRESET Out Selection
When a VMEbus module occupies slot 1 of the VMEbus chassis (the slot to the extreme left), it must operate as
system controller (act as multiprocessing arbiter and generate utility bus signals). JP1 configures the VMEbus
System Controller functionality of the Universe IID, as shown below:
VMEbus System Controller JP1
Enabled Open
Disabled Closed
VMEbus System Controller Configuration
Jumper JP3 selects the VIO routed to the XPD’s two PMC modules. The VIO pins determine the signaling voltage
on the PMC modules’ PCI interface. Refer to the PMC modules’ reference manuals to ascertain the recommended
VIO. Shunting pins 1 & 2 of JP1 provides a VIO of 3.3 VDC. Shunting pins 2 & 3 routes 5 VDC to the VIO pins
on the PMC modules.
VIO Voltage Level JP3
3.3 VDC 1-2
5 VDC 2-3
Battery Voltage Supply Selection
JP4 lets VMEbus SYSRESET reset the XPD when closed. When open, a VMEbus SYSRESET from other modules
will not reset the XPD.
VMEbus SYSRESET In Selection JP4
XPD Won’t Receive SYSRESET from the VMEbus Open
XPD Receives SYSRESET from the VMEbus Closed
VMEbus SYSRESET In Selection