Emerson MVME3100 Series User manual

MVME3100 Single Board Computer
Programmer’s Reference
6806800G37A
April 2008

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MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 3
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Board Description and Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.1 Default Processor Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.2 MOTLoad’s Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.3 VME Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.4 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.5 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.6 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.7 System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.8 Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.9 PCI Bus Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3.10 Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.11 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.12 PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3.13 PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.14 Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.15 Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.3.16 External Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.1 Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.3.16.3 Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.3.16.4 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.3.17 Geographical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2 Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2 MPC8540 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 Local Bus Controller Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.5 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.6 User Configuration EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7 VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8 RTM VPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.9 Ethernet PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.10 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contents

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Contents
4
2.11 PCI IDSEL Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.12 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.13 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.14 MPC8540 Real-Time Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.15 MPC8540 LBC Clock Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
A.1 Emerson Network Power - Embedded Computing Documents . . . . . . . . . . . . . . . . . . . . . . . . 45
A.2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 5
Figure 1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Figures

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
List of Figures
6

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 7
Table 1-1 MVME3100 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-2 MVME712-101 RTM Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 1-3 Default Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-4 MOTLoad’s Processor Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-5 System I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-6 System Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-7 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-8 System Indicator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-9 Flash Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-10 PCI Bus A Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-11 PCI Bus B Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-12 PCI Bus C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-13 Interrupt Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 1-14 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-15 PLD Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 1-16 PLD Data Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-17 Test Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-18 Test Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-19 Prescalar Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 1-20 Tick Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 1-21 Tick Timer Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 1-22 Tick Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 2-1 MPC8540 Power-on Reset Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-2 MPC8540 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 2-3 LBC Chip Select Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-4 I2C Bus Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 2-5 PHY Types and MII Management Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-6 Flash Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-7 IDSEL and Interrupt Mapping for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-8 Planar PCI Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 2-9 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-10 Clock Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table A-1 Emerson Network Power - Embedded Computing Publications . . . . . . . . . . . . . . . . . 45
Table A-2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table A-3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Tables

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
List of Tables
8

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 9
About this Manual
Overview of Contents
This manual is divided into the following chapters and appendices:
Chapter 1, Board Description and Memory Maps, provides a brief product description and a
block diagram. The remainder of the chapter provides information on memory maps and system
and configuration registers.
Chapter 2, Programming Details, provides additional programming information including IDSEL
mapping, interrupt assignments for the MPC8540 interrupt controller, Flash memory, two-wire
serial interface addressing, and other device and system considerations.
Appendix A, Related Documentation, provides a listing of related Emerson manuals, vendor
documentation, and industry specifications.

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
About this Manual
10
Abbreviations
Abbreviation Description
ATA Advanced Technology Attachment
CHRP Common Hardware Reference Platform
CMC Common Mezzanine Card
COM Communication
CPU Central Processing Unit
DDR Double Data Rate
DMA Direct Memory Access
DRAM Dynamic Random Access Memory
ECC Error Correction Code
FIFO First In First Out
GA General Availability
GMII Gigabit Media Independent Interface
GPCM General Purpose Chip select Machine
I/O Input/Output
IEEE Institute of Electrical and Electronics Engineers
KB Kilobytes
LBC Local Bus Controller
LED Light Emitting Diode
MB Megabyte
MHz Megahertz
MIIM MII Management
NVRAM Non Volatile RAM
PCI Peripheral Connect Interface
PCI-X Peripheral Component Interconnect -X
PHY Physical Layer
PIC Programmable Interrupt Controller
PIM PCI Mezzanine Card Input/Output Module
PLD Programmable Logic Device
PMC PCI Mezzanine Card (IEEE P1386.1)
POR Power-On Reset
PReP PowerPC Reference Platform
PrPMC Processor PMC
QUART Quad Universal Asynchronous Receiver/Transmitter
R/W Read/Write
RAM Random Access Memory

About this Manual
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 11
Conventions
The following table describes the conventions used throughout this manual.
ROM Read Only Memory
RTC Real Time Clock
RTM Rear Transition Module
RTOS Real Time Operating System
SATA Serial AT Attachment
SBC Single Board Computer
SDRAM Synchronous Dynamic Random Access Memory
SIG Special Interest Group
SMT Surface Mount Technology
SPD Serial Presence Detect
TSEC Triple Speed Ethernet Controllers
TSOP Thin Small Outline Package
UART Universal Asynchronous Receiver/Transmitter
UNIX UNIX operating system
USB Universal Serial Bus
VIO Input/Output Voltage
VITA VMEbus International Trade Association
VME VersaModule Eurocard
VMEbus VersaModule Eurocard bus
Abbreviation Description
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits
are 0 through F), for example used for addresses
and offsets
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word
Screen Used for on-screen output and code related
elements or commands in body text
Courier + Bold Used to characterize user input and to separate it
from system output
Reference Used for references and for table and figure
descriptions
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
About this Manual
12
Summary of Changes
This manual has been revised and replaces all prior editions.
[text] Notation for software buttons to click on the screen
and parameter description
... Repeated item for example node 1, node 2, ...,
node 12
.
.
.
Omission of information from example/command
that is not necessary at the time being
.. Ranges, for example: 0..4 means one of the
integers 0,1,2,3, and 4 (used in registers)
| Logical OR
Indicates a hazardous situation which, if not
avoided, could result in death or serious injury
Indicates a hazardous situation which, if not
avoided, may result in minor or moderate injury
Indicates a property damage message
No danger encountered. Pay attention to important
information
Notation Description
Part Number Publication Date Description
V3100A/PG1 First edition
6806800G37A April 2008 Updated to Emerson style.

About this Manual
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 13
Comments and Suggestions
We welcome and appreciate your comments on our documentation. We want to know what you
think about our manuals and how we can make them better.
Mail comments to us by filling out the following online form:
http://www.emersonnetworkpowerembeddedcomputing.com/ > Contact Us > Online Form
In “Area of Interest” select “Technical Documentation”. Be sure to include the title, part number,
and revision of the manual and tell us how you used it.

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
About this Manual
14

1
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 15
Board Description and Memory Maps
1.1 Introduction
This chapter briefly describes the board level hardware features of the MVME3100 single-board
computer, including a table of features and a block diagram. The remainder of the chapter
provides memory map information including a default memory map, MOTLoad’s processor
memory map, a default PCI memory map, MOTLoad’s PCI memory map, system I/O memory
map, and other configuration registers.
1.2 Overview
The MVME3100 is a single-slot, single-board computer based on the MPC8540 PowerQUICC
III™ integrated processor. The MVME3100 provides serial ATA (sATA), USB 2.0, 2eSST
VMEbus interfaces, dual 64-bit/100 MHz PMC sites, up to 256 MB of flash, dual 10/100/1000
Ethernet, one 10/100 Ethernet, and five serial ports. This board supports front and rear I/O and
a single SODIMM module for DDR memory. Access to rear I/O is available with a rear transition
module (RTM).
The MVME3100 Single-Board Computer Programmer’s Reference provides general
programming information, including memory maps, interrupts, and register data for the
MVME3100 family of boards. This document should be used by anyone who wants general, as
well as technical information about the MVME3100 products.
As of the printing date of this manual, the MVME3100 supports the models listed below.
Model Number Description
MVME3100-1152 677 MHz MPC8540 PowerQUICC III™integrated processor, 256MB DDR
SDRAM, 64MB flash, Gigabit Ethernet, SATA, IEEE handles
MVME3100-1263 833 MHz MPC8540 PowerQUICC III integrated processor, 512MB DDR
SDRAM, 128MB flash, Gigabit Ethernet, SATA, USB, PCI expansion
connector, IEEE handles
MVME721-101 Rear Transition Module, direct connect, 75mm, PIM socket for PMC-1 I/O,
four serial, 10/100/1000 Enet, 10/100 Enet

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Board Description and Memory Maps Overview
16
Figure 1-1 shows a block diagram of the MVME3100 and Table 1-1 lists the features of the
MVME3100.
Figure 1-1 Block Diagram
PMC 1 Front IO
U
S
BsATA
P2 P0 P1
GigE
RJ45
PHY
5461
COM1
RJ45
XCVR
RS232
DUART DDR MC
TSEC1
TSEC2
FEC LBC
I2C
PCIX
MPC8540
Processor
833 MHz
Serial Port 0
GigE 1
GigE 2
10/100
PHY
5461
PHY
5221
SODIMM - Up to
1GB DDR Memory
User
128KB
RTC
DS1375
VPD
8KB
VME
TSI148
XCVR
22501
XCVR
RS232
CPLD
Decode
Timers/Regs
RTC
DS1621
Quart
16C554
sATA
GD31244
USB
uPD720101
Flash
128MB
Clock
Distribution
Reset
Control
Power
Supplies
P2P
PCI6520
P2P
PCI6520
PMCSpan
Planar
Connector
Bus A
PCI-X 66MHz
PMC 1 PMC 2
sATA 1
VME Bus
I2C Bus USB 2PMC 1 Jn4 IOCOM2 - COM510/100 sATA 2
USB 2USB 1
GigE 2
Bus C
PCI 33 MHz
Bus B
PCI-X 66/100 MHz
PCI 33/66 MHz
Serial Ports 1-4
sATA 0
Device
Bus
166 MHz Memory Bus
RST/ABORT
PMC 2 Front IO
I2C Bus
Front Panel
Future Option
De-pop in -1152
Table 1-1 MVME3100 Features Summary
Feature Description
Processor/Host
Controller/Memory Controller
– Single 667/833 MHz MPC8540 PowerQUICC III™ integrated
processor (e500 core)
– Integrated 256KB L2 cache/SRAM
– Integrated four-channel DMA controller
– Integrated PCI/PCI-X controller
– Two integrated 10/100/1000 Ethernet controllers
– Integrated 10/100 Ethernet controller
– Integrated dual UART
– Integrated I2C controller
– Integrated programmable interrupt controller
– Integrated local bus controller
– Integrated DDR SDRAM controller

Overview Board Description and Memory Maps
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 17
System Memory – One SODIMM socket
– Up to DDR333, ECC
– 256MB or 512MB SODIMM
I2C Interface – One 8KB VPD serial EEPROM
– Two 64KB user configuration serial EEPROMs
– One real-time clock (RTC) with removable battery
– One temperature sensor
– Interface to SPD(s) on SODIMM and P2 for RTM VPD
Flash – 32MB to 256MB soldered Flash with two alternate 1MB boot sectors
selectable via a hardware switch
– Hardware switch or software bit write protection for entire logical
bank
PCI Interface Bus A:
– 66 MHz PCI-X (PCI-X 1.0b compliant)
– One TSi148 VMEbus controller
– One serial ATA (sATA) controller
– Two PCI6520 PCI-X-to-PCI-X bridges (primary side)
Bus B:
– 33/66/100 MHz PCI/PCI-X (PCI 2.2 and PCI-X 1.0b compliant)
– Two +3.3V/5V selectable VIO, 64-bit, single-wide PMC sites or one
double-wide PMC site (PrPMC ANSI/VITA 32-2003 and PCI-X
Auxiliary ANSI/VITA 39-2003 compliant)
– One PCI6520 PCI-X-to-PCI-X bridge (secondary side)
Bus C (-1263 version):
– 33 MHz PCI (PCI 2.2 compliant)
– One USB 2.0 controller
– One PCI expansion connector for interface to PMCspan
– One PCI6520 PCI-X-to-PCI-X bridge (secondary side)
I/O – One front panel RJ45 connector with integrated LEDs for front I/O:
one serial channel
– One front panel RJ45 connector with integrated LEDs for front I/O:
one 10/100/1000 Ethernet channel
– One front panel external sATA data connector for front I/O: one sATA
channel
– One front panel USB Type A upright receptacle for front I/O: one USB
2.0 channel (-1263 version)
– PMC site 1 front I/O and rear P2 I/O
– PMC site 2 front I/O
Serial ATA – One four-channel sATA controller: one channel for front-panel I/O,
one channel for planar I/O, one channel for future rear P0 I/O, and one
channel is not used
– One planar data connector and one planar power connector for an
interface to the sATA hard disk drive
USB (-1263 version) – One four-channel USB 2.0 controller: one channel for front panel I/O
and one channel for future rear P0 I/O. The other two channels are not
used.
Ethernet – Two 10/100/1000 MPC8540 Ethernet channels for front-panel I/O
and rear P2 I/O
– One 10/100 MPC8540 Ethernet channel for rear P2 I/O
Table 1-1 MVME3100 Features Summary (continued)
Feature Description

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Board Description and Memory Maps Overview
18
Serial Interface – One 16550-compatible, 9.6 to 115.2 KBAUD, MPC8540,
asynchronous serial channel for front-panel I/O
– One quad UART controller to provide four 16550-compatible, 9.6 to
115.2 KBAUD, asynchronous serial channels for rear P2 I/O
Timers – Four 32-bit MPC8540 timers
– Four 32-bit timers in a PLD
Watchdog Timer – One MPC8540 watchdog timer
VME Interface – VME64 (ANSI/VITA 1-1994) compliant
– VME64 Extensions (ANSI/VITA 1.1-1997) compliant
– 2eSST (ANSI/VITA 1.5-2003) compliant
– VITA 41.0, version 0.9 compliant
– Two five-row P1 and P2 backplane connectors
– One TSi148 VMEbus controller
Form Factor – Standard 6U VME
Miscellaneous – One front-panel reset/abort switch
– Four front-panel status indicators: 10/100/1000 Ethernet link/speed
and activity, board fail, and user software controlled LED
– Six planar status indicators: one power supply status LED, two user
software controlled LEDs, three sATA activity LEDs (one per channel)
– One standard 16-pin JTAG/COP header
– Boundary scan support
– Switches for VME geographical addressing in a three-row backplane
Software Support – VxWorks operating system
– Linux operating system
Table 1-2 MVME712-101 RTM Features Summary
Feature Description
I/O – One five-row P2 backplane connector for serial and Ethernet I/O
passed from the MVME3100
– Four RJ-45 connectors for rear-panel I/O: four asynchronous
serial channels
– Two RJ-45 connectors with integrated LEDs for rear panel I/O:
one 10/100/1000 Ethernet channel and one 10/100 Ethernet
channel
– One PIM site with rear-panel I/O
Miscellaneous – Four rear-panel status indicators: 10/100/1000 and 10/100
Ethernet link/speed and activity LEDs
Table 1-1 MVME3100 Features Summary (continued)
Feature Description

Memory Maps Board Description and Memory Maps
MVME3100 Single Board Computer Programmer’s Reference (6806800G37A) 19
1.3 Memory Maps
1.3.1 Default Processor Memory Map
The MPC8540 presents a default processor memory map following RESET negation. The
following table shows the default memory map from the point of view of the processor. The e500
core only provides one default TLB entry to access boot code and it allows for accesses within
the highest 4KB of memory. To access the full 8MB of default boot space (and the 1MB of CCSR
space), additional TLB entries must be set up within the e500 core for mapping these regions.
Refer to the MPC8540 Reference Manual listed in Appendix A, Related Documentation, for
details.
This is the default location for the CCSRs, but it is not mapped after reset.
Only FFFF F000 to FFFF FFFF is mapped after reset. The e500 core fetches the first instruction
from FFFF FFFC following a reset.
1.3.2 MOTLoad’s Processor Memory Map
MOTLoad’s processor memory map is given in the following table.
Table 1-3 Default Processor Address Map
Processor Address
Size Definition NotesStart End
0000 0000 FF6F FFFF 4087M Not mapped
FF70 0000 FF7F FFFF 1M MPC8540 CCS Registers 1
FF80 0000 FFFF FFFF 8M Flash 2
Table 1-4 MOTLoad’s Processor Address Map
Processor Address
Size Definition NotesStart End
0000 0000 top_dram-1 dram_size
(2GB max)
System Memory (on-board DRAM)
8000 0000 DFFF FFFF 1.5GB PCI Memory Space/VME
E000 0000 E0FF FFFF 16MB PCI I/O Space
E100 0000 E10F FFFF 1MB MPC8540 CCSR
E1100 0000 E1FF FFFF 15MB Not Used
E200 0000 E2FF FFFF 16MB Status/Control Registers/UARTs,
External Timers
E300 0000 EFFF FFFF 208MB Not Used
F000 0000 F7FF FFFF 128MB Reserved 1, 2

MVME3100 Single Board Computer Programmer’s Reference (6806800G37A)
Board Description and Memory Maps VME Memory Map
20
After RESET, the MPC8540 does not map any PCI memory space (inbound or outbound), and
does not respond to Config cycles.
1.3.3 VME Memory Map
The MVME3100 is fully capable of supporting both the PReP and the CHRP VME Memory Map
examples with RAM size limited to 2GB.
1.3.4 System I/O Memory Map
System resources including System Control and Status registers, external timers, and the
QUART are mapped into a 16MB address range from the MVME3100 via the MPC8540 local
bus controller (LBC). The memory map is defined in the following table, including the LBC bank
chip select used to decode the register:
bottom_flash FFFF FFFF flash_size
(128MB max)
Flash 2
1. Reserved for future larger flash devices.
2. The flash is ligically one back but may be physically implemented in two banks.
Table 1-4 MOTLoad’s Processor Address Map (continued)
Processor Address
Size Definition NotesStart End
Table 1-5 System I/O Memory Map
Address Definition
LBC Bank /
Chip Select Notes
E200 0000 System Status Register 2 3
E200 0001 System Control Register 2 3
E200 0002 Status Indicator Register 2 3
E200 0003 Flash Control/Status Register 2 3
E200 0004 PCI Bus A Status Register 2 3
E200 0005 PCI Bus B Status Register 2 3
E200 0006 PCI Bus C Status Register 2 3
E200 0007 Interrupt Detect Register 2 3
E200 0008 Presence Detect Register 2 3
E200 0009 PLD Revision 2 3
E200 000C PLD Date Code (32 bits) 2 3
E200 0010 Test Register 1 (32 bits) 2 3
E200 0014 Test Register 2 (32 bits) 2 3
E200 0018 -
E200 0FFF
Reserved 1