Epson S1C05251 User manual

MF1329-02
Technical Manual
CMOS CALLING NUMBER IDENTIFICATION RECEIVER IC
S1C05251 Technical Hardware
S1C05251

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© SEIKO EPSON CORPORATION 2001 All rights reserved.

The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C63 Family processors
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
S1 C63158 F0A01
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C63000 A1 1
Packing specification
Version (1: Version 1 ∗2)
Tool type (A1: Assembler Package ∗1)
Corresponding model number
(63000: common to S1C63 Family)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C63158
E0C63256
E0C63358
E0C63P366
E0C63404
E0C63406
E0C63408
E0C63F408
E0C63454
E0C63455
E0C63458
E0C63466
E0C63P466
New No.
S1C63158
S1C63256
S1C63358
S1C6P366
S1C63404
S1C63406
S1C63408
S1C6F408
S1C63454
S1C63455
S1C63458
S1C63466
S1C6P466
S1C63 Family peripheral products
Previous No.
E0C63467
E0C63557
E0C63558
E0C63567
E0C63F567
E0C63658
E0C63666
E0C63F666
E0C63A08
E0C63B07
E0C63B08
E0C63B58
New No.
S1C63467
S1C63557
S1C63558
S1C63567
S1C6F567
S1C63658
S1C63666
S1C6F666
S1C63A08
S1C63B07
S1C63B08
S1C63B58
Previous No.
E0C5250
E0C5251
New No.
S1C05250
S1C05251
Comparison table between new and previous number of development tools
Development tools for the S1C63 Family Development tools for the S1C63/88 Family
Previous No.
ADP63366
ADP63466
ASM63
GAM63001
ICE63
PRC63001
PRC63002
PRC63004
PRC63005
PRC63006
PRC63007
URS63366
New No.
S5U1C63366X
S5U1C63466X
S5U1C63000A
S5U1C63000G
S5U1C63000H1
S5U1C63001P
S5U1C63002P
S5U1C63004P
S5U1C63005P
S5U1C63006P
S5U1C63007P
S5U1C63366Y
Previous No.
ADS00002
GWH00002
URM00002
New No.
S5U1C88000X1
S5U1C88000W2
S5U1C88000W1
00
00

CONTENTS
S1C05251 TECHNICAL MANUAL EPSON i
CONTENTS
1 Overview.......................................................................................................................1
1.1 Features......................................................................................................................................................................1
1.2 Block Diagram...........................................................................................................................................................2
1.3 Pin Assignment.........................................................................................................................................................2
1.4 Pin Description..........................................................................................................................................................3
2 Power Supply Block and Initial Reset...........................................................................6
2.1 Power Supply............................................................................................................................................................6
2.2 Initial Reset.................................................................................................................................................................6
3 Functional Description..................................................................................................7
3.1 Register Description................................................................................................................................................7
3.2 Outputs from the #RDET, #IRQ and #DET Pins.......................................................................................12
3.3 Input Amp Circuit...................................................................................................................................................13
3.3.1 Differential Input..................................................................................................................................13
3.3.2 Single End Input.................................................................................................................................14
3.4 Ring/Line Reversal Signal Detection.............................................................................................................15
3.5 FSK Demodulation...............................................................................................................................................15
3.6 Dual-Tone Detection............................................................................................................................................16
3.7 Off-Hook Detection...............................................................................................................................................16
4 Precautions on Mounting............................................................................................17
5 Electrical Characteristics............................................................................................19
5.1 Absolute Maximum Ratings..............................................................................................................................19
5.2 Recommended Operating Conditions...........................................................................................................19
5.3 DC Characteristics................................................................................................................................................19
5.4 Current Consumption...........................................................................................................................................19
5.5 Crystal Oscillation Characteristics...................................................................................................................20
5.6 FSK Demodulation Circuit Characteristics...................................................................................................20
5.6.1 FSK AC Characteristics....................................................................................................................20
5.6.2 FSK Switching Characteristics.......................................................................................................20
5.6.3 FSK Energy Detection Mode AC Characteristics...................................................................21
5.6.4 FSK Energy Detection Mode Switching Characteristics......................................................21
5.7 Dual-Tone (CAS) Detection Circuit Characteristics.................................................................................22
5.7.1 CAS AC Characteristics...................................................................................................................22
5.7.2 CAS Switching Characteristics......................................................................................................22
5.8 Call Progress Mode (CPM) Detection Circuit Characteristics..............................................................23
5.8.1 CPM AC Characteristics...................................................................................................................23
5.8.2 CPM Switching Characteristics......................................................................................................23
5.9 Serial Interface Circuit Characteristics..........................................................................................................24
5.9.1 Serial Interface AC Characteristics..............................................................................................24
5.9.2 FSK Demodulated Data Read Mode..........................................................................................25
5.9.3 CAS Detection Circuit Control-Register Write Mode.............................................................25
5.10 S1C05251 Timing Chart...................................................................................................................................26
5.10.1 Bellcore On-Hook Data Transfer................................................................................................26
5.10.2 Bellcore Off-Hook Data Transfer................................................................................................26
5.10.3 BT Idle State CLI Service.............................................................................................................27
5.10.4 BT Loop State CLI Service..........................................................................................................27

CONTENTS
ii EPSON S1C05251 TECHNICAL MANUAL
5.11 External Wiring Diagram (Example)............................................................................................................28
5.11.1 Example of Bellcore-Compatible Telephone Circuit...........................................................28
5.11.2 Example of Bellcore-Compatible Auxiliary Circuit................................................................29
6 Package......................................................................................................................30
7 Pad Layout..................................................................................................................31
7.1 Pad Layout Diagram............................................................................................................................................31
7.2 Pad Coordinates...................................................................................................................................................31

1 OVERVIEW
S1C05251 TECHNICAL MANUAL EPSON 1
1 Overview
The S1C05251 (CAS + FSK IC), an upgraded version of the S1C05250, is a CMOS IC for calling number
identification with the Call Waiting function.
It provides an interface to various call information delivery services based on Bellcore GR-30-CORE, such asCND
(Calling Number Delivery), CNAM (Calling Name Delivery), and CIDCW (Calling Identity on Call Waiting), as
well as British Telecom’s CLIP (Calling Line Identification Service)andCableCommunications Association’sCDS
(Caller Display Service).
The S1C05251 incorporates power-down, ring detection, and carrier detection circuits, a synchronous receive data
output function, and a clock-synchronized serial interface. All these features makeitsuitableforvarious applications
such as those listed below.
• Calling number delivery service with a Call Waiting function
• Telephone sets and similar auxiliary equipment
• Telephone answering equipment
• Multifunction telephones
• Facsimiles
• Computer peripheral circuits
• Message waiting telephones
1.1 Features
• Conforms to Bellcore GR-30-CORE and SR-TSV-002476 (same as S1C05250)
• Conforms to British Telecom SIN227 and SIN242 (same as S1C05250)
• Can detect Bellcore CPE alert signal (CAS) and British Telecom idle-tone alert signal using a programmable
band-pass filter (same as S1C05250)
• FSK demodulation circuit based on ITU-T V.23 and BELL202 (same as S1C05250)
• Filter bypass mode to detect call progress mode (CPM) signal (same as S1C05250)
• Programmable alert-signal detection level (same as S1C05250)
• Carrier/ring detection output (same as S1C05250)
• FSK energy mode to detect FSK signal in power-down mode (new function for S1C05251)
• Supports CAS signal single-end input (new function for S1C05251)
• Off-hook detection (new function for S1C05251)
• Supports 3.57945 MHz crystal oscillator or external clock input (same as S1C05250)
• Serial-receive data output (same as S1C05250)
• Serial host interface (same as S1C05250)
• Power-down mode (same as S1C05250)
• Power supply voltage: 2.7 V to 5.5 V (same as S1C05250)
• Operating temperature range: -20°C to 70°C (same as S1C05250)
• Current consumption: 3 mA when operating (same as S1C05250)
1 µA in zero-power mode (same as S1C05250)
6 µA in FSK energy detection mode (new function for S1C05251)
• Shipping form: SOP2-28pin package (plastic), DIP-28pin package (ceramic) or chip (package for S1C05251)

1 OVERVIEW
2EPSON S1C05251 TECHNICAL MANUAL
1.2 Block Diagram
Band-pass
filter
CAS tone
filter
INN SDO
#DET
#PQUAL
Amp
–
+
INP
BPOUT
OSC3EXTCLK OSC4
EXTREF
–
+
HOOK
CASIN Amp
–
+
CASFB
FB
RDIN
V DD
V SS
#RDET V
DD
V REF V DD /2
(MODE0 ∗SEL)
(MODE1)
FSK
demodulator
Identification
circuit
CDIN
PDWN #RESET MODE1MODE0
Data/timing
recovery
circuit
Detection
circuit
Timing generator Control circuit
Interrupt
control circuit
#IRQ
SDI
#SCLK
#RDRC
To other blocks
Amp( )
Figure 1.2.1 Block diagram
1.3 Pin Assignment
SOP2-28pin DIP-28pin
1
14
28
15
S1C05251
28
15
1
14
S1C05251
No. Pin name No. Pin name No. Pin name No. Pin name
1 INP 8 HOOK 15 OSC3 22 #IRQ
2 INN 9 RDIN 16 OSC4 23 #SCLK
3 FB 10 #RDRC 17 EXTCLK 24 SDI
4 CASIN 11 #RDET 18 MODE0 25 SDO
5 CASFB 12 PDWN 19 MODE1 26 CDIN
6VREF 13 #RESET 20 #PQUAL 27 BPOUT
7 EXTREF 14 VSS 21 #DET 28 VDD
Figure 1.3.1 Pin assignment

1 OVERVIEW
S1C05251 TECHNICAL MANUAL EPSON 3
1.4 Pin Description
Note: The signal and pin names prefixed by # in this manual are those of active-low signals and pins.
Table 1.4.1 Pin description
Pin name Pin No. Type Power-down
status Description
INP 1 Input
Analog Off/ Active + Input: Non-inverting amplifier input. This pin is connected to the telephone wire through an input gain-setting resistor and a DC cut
capacitor. Under the power downmode, this pin is functionary
disconnected from the internal circuitry when the MODE1 pin is set to
low level. When the MODE1 pin is set to high level, this pin stays
active to detect FSK signal energy to send wake up signal to the host
through the #IRQ pin. Do not connect any external components to this
pin except gain setting resistors to this pin. Excess load may cause
improper operation of the circuit.
INN 2 Input
Analog Off/ Active - Input: Inverting amplifier input. This pin is connected to the telephone wire through an input gain-setting resistor and a DC cut
capacitor. Under the power downmode, this pin is functionary
disconnected from the internal circuitry when the MODE1 pin is set to
low level. When the MODE1 pin is set to high level, this pin stays
active to detect FSK signal energy to send wake up signal to the host
through the #IRQ pin. Do not connect any external components to this
pin except gain setting resistors to this pin. Excess load may cause
improper operation of the circuit.
FB 3 Output
Analog High-Z/ Active Amplifier Output: A feed back resistor is connected between this pin and the INN pin to set gain. Under the power down mode, this output
pin is set to high impedance when the MODE1 pin is set to low level.
When theMODE1 pin is set to high level in power down, this pinstays
active to detect FSK signal energy to send wake up signal to the host
through the #DET pin. Do not connect any external components to
this pin except a gain setting resistor to this pin. Excess load may
cause improper operation of the circuit.
CASIN 4 Input
Analog Off CAS Tone Input: CAS tone amplifier input. For the telephone application, this pin is connected to the output of telephone hybrid
circuit through input gain-setting resistor and a DC cut capacitor.
Under the power down mode,this pin is functionary disconnected
from the internal circuitry. Do not connect any external components to
this pin except gain setting resistors to this pin. Excess load may
cause improper operation of the circuit.
CASFB 5 Output
Analog High-Z CAS Amplifier Output: A feed back resistor is connected between this pin and the CASIN pin to set CAS gain. Under the power down
mode, this output pin is set to high impedance. Do not connect any
external components to this pin except a gain setting resistor to this
pin. Excess load may cause improper operation of the circuit.
VREF 6 Output
Analog High-Z/ VDD/2 level Reference Voltage Output: 1/2 VDD voltage output. This pin must be bypassed to ground through 0.1 µF capacitor. During power down
mode, this output pin is set to high impedance when the MODE1 pin
is low level. When theMODE1 pin is set to high level in power down,
this pin stays at VDD/2. Do not connect any external components to
this pin except a jumper to VREF pin or a bypass capacitor to ground.
Excess load may cause improper operation of the circuit.
EXTREF 7 Input
Analog Active External Reference Voltage Input: External DC reference voltage is connected to this pin. This voltage set the off-hook detectionthreshold
level.
HOOK 8 Input
Analog Active Off-Hook Detection Input: Diode bridge output from the TIP/RING lines is connected to this pin through external resistor divider todetect
off-hook/on-hook states.
RDIN 9 Schmitt
trigger input Active Ring Detect Input: The attenuated ring signal is connected to thispin for the ring detection. This circuit is always active even if the device is
in the power down mode.

1 OVERVIEW
4EPSON S1C05251 TECHNICAL MANUAL
Pin name Pin No. Type Power-down
status Description
#RDRC 10 Open-drain
output
Schmitt
trigger input
Active Ring Detect RC Terminal: RC network will be connected to this pin
to set time delays for the ring signal detection. This circuit is always
active even if the device is in the power down mode.
#RDET 11 Output Active Ring Detect Output: When theMODE1 pin is set to low level,thispin
is connected from output of a Schmitt trigger buffer which input is
connected to the#RDRC pin. Low level at this pin indicates that the
ring signal is detected. When the MODE1 pin bit is set to high level,
this pin is connected from output of a hook detect circuit which input is
connected from the HOOK pin. High level at this pinindicateson-hook
condition and low level at this pin indicates off-hook condition.
PDWN 12 Input Active Power Down Input: This pin must be kept at low level for the normal
operation. When it is set to high level, the device enters the power
down mode. During power down mode, the OSC4 pin is set to high
level, and the VREF, CASFB and FB pins are set to high impedance.
(The FB and VREF pins are set to high impedance only whenthe
MODE1 pin is at low level.)
#RESET 13 Input Active Reset Input: When this pin is set to low level, all internalhost
registers are reset to their default conditions.This pin must be set to
high level to write data to the internal registers.
VSS 14 Power
supply (-) Device Ground: This pin is connected to the system ground.
OSC3 15 Input Off Crystal Oscillator/External Clock Input: A crystal resonator is
connected between this pin and the OSC4 pin. This pin may be driven
from an external clock source. The proper value load capacitor must
be connected between this pin and ground. During power down, this
input pin is disconnected from internal circuits.
OSC4 16 Output High level Crystal Oscillator Output: A crystal or ceramic resonator is
connected betweenthis pin and OSC3 pin. Thispin must be kept
open when the OSC3 pin is driven from an external clock source. The
proper value load capacitor must be connected between this pin and
ground. During power down, this output pin is set to high level.
EXTCLK 17 Input Active External Clock Input: Typically 32.768 kHz clock signal is applied to
this pin from the host device to enable pre-qualification logic used in
FSK energy detection circuitry.
MODE0 18 Input Active Mode0 Select Input: This pin select CAS or FSK/CPM mode. When
this pin is set to high level, CAS mode is selected. In this mode, CAS
detection is enabled and the FSK function is disabled. The host
device also can write internal registers through the SDI and #SCLK
pin. Before writing data into registers, this pin must be set to low level
once to synchronize theserial interface circuit for data writing
sequence. When this pin is set to low level, FSK/CPM mode is
selected. In this mode, CAS detection is disabled and the FSK/CPM
function is enabled. The host device also can read the received data
from the SDO pin under this mode. Refer to Table 3.2.1 for more
details.
MODE1 19 Input Active Mode1 Select Input: This pin enables FSK energy and off-hook
detection mode. When this pin is set to high level, FSK energy and
off-hook detection mode is enabled. When this pin is set to low level,
FSK energy and off-hook detection mode is disabled. Refer to Table
3.2.1 for more details.
#PQUAL 20 Output High level Pre-qualification Output: Early qualification output will be monitored
at this pin. When no tones are detected, this pin stays at high level.