FastVision FastCamera13 User manual

FASTCAMERA SERIES
FASTCAMERA13
USER’S MANUAL
FVM-50013

2
COPYRIGHT NOTICE
Copyright © 2004 by FastVision, LLC.
All rights reserved. This document, in whole or in part, may not be copied, photocopied, reproduced,
translated, or reduced to any other electronic medium or machine-readable form without the express written
consent of FastVision, LLC.
FastVision makes no warranty for the use of its products, assumes no responsibility for any error, which
may appear in this document, and makes no commitment to update the information contained herein.
FastVision, LLC. retains the right to make changes to this manual at any time without notice.
Document Name: FastCamer13 User’s Manual
Document Number: 30002-50013
Revision History: 1.0 January 20,2003
1.1 March 26,2003
1.2 March 30,2003
1.3 April 9, 2003
2.0 August 10,2004
3.0 August 13, 2004
4.0 August 17, 2004
Trademarks:
FastVision®is a registered trademark of FastVision, LLC..
Channel Link™is a trademark of National Semiconductor.
3M™is a trademark of 3M Company
MS DOS®is a registered trademark of Microsoft Corporation
SelectRAM™is a trademark of Xilinx Inc.
Solaris™is a trademark of Sun Microsystems Inc.
Unix®is a registered trademark of Sun Microsystems Inc.
Virtex™is a trademark of Xilinx Inc.
Windows™, Windows 95™, Windows 98™, Windows 2000™, Windows NT™, and Windows
XP™are trademarks of Microsoft
All trademarks are the property of their respective holders.
FastVision, LLC.
131 Daniel Webster Highway, #529
Nashua, NH 03060
USA
Telephone: [phone]
Fax: [phone]
Web Site:
http://www.fast-vision.com/
Email:
[email protected], or [email protected]

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TABLE OF CONTENTS
1. INTRODUCTION _________________________________________________ 1-6
2. Features and Specifications_______________________________________ 2-6
2.1. CAMERA SPECIFICATIONS ____________________________________________2-7
2.2. IMAGE SENSOR SPECIFICATIONS:______________________________________2-7
2.3. Physical Specifications ________________________________________________2-7
2.4. Connectors __________________________________________________________2-9
2.4.1. Power Connector HR10A-10R-12PB__________________________________________ 2-9
2.4.2. Data Connector J2________________________________________________________ 2-9
2.4.3. Data Connector J3________________________________________________________ 2-9
3. Power Requirements ____________________________________________ 3-10
4. Timing ________________________________________________________ 4-10
5. Trigger Modes _________________________________________________ 5-10
6. Camera Data Flow ______________________________________________ 6-12
7. The Standard Camera Functionality _______________________________ 7-13
8. Pixel Gain and Offset____________________________________________ 8-13
9. Memory Option_________________________________________________ 9-13
9.1. FIFO memory mode __________________________________________________9-13
9.2. Circular buffer memory mode__________________________________________9-14
9.3. Image summing memory mode ________________________________________9-14
10. Lookup Table Option___________________________________________ 10-14
11. Data Format Funnel ____________________________________________ 11-14
12. Internal Camera Memory________________________________________ 12-14
13. Sensor Control________________________________________________ 13-14
13.1. Line Timing ______________________________________________________13-15
13.2. Frame Timing ____________________________________________________13-15
13.3. Exposure Modes__________________________________________________13-15
13.4. Trigger Modes____________________________________________________13-15
13.5. Trigger Options___________________________________________________13-16
13.6. Trigger Outputs___________________________________________________13-17
13.7. Reference Voltages________________________________________________13-17
13.8. Calibration_______________________________________________________13-17

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13.9. Power-on Initialization _____________________________________________13-17
14. Flash Memory_________________________________________________ 14-18
15. Camera State Storage __________________________________________ 15-19
16. Serial Control Interface _________________________________________ 16-20
16.1. Encoding ________________________________________________________16-21
17. Inter-FPGA Communication _____________________________________ 17-25
18. Embedded Soft Processor Core__________________________________ 18-26
19. Data FPGA ___________________________________________________ 19-31
19.1. Functional Description_____________________________________________19-31
19.2. Video Data path overview __________________________________________19-33
19.3. Operating mode control overview____________________________________19-33
19.4. Camera State_____________________________________________________19-33
19.5. DataFpga State controls____________________________________________19-34
19.5.1. Camera Link Readout Mode ______________________________________________ 19-34
19.5.2. Camera Link Clock Frequency setting_______________________________________ 19-37
19.5.3. Binning Control setting___________________________________________________ 19-37
19.5.4. Binning Multiplier setting _________________________________________________ 19-37
20. Frame Rates. _________________________________________________ 20-38
20.1. Memory Operation.________________________________________________20-38
20.2. DATA FPGA Technical Details. ______________________________________20-38
20.3. 1 Tap mode ______________________________________________________20-40
20.4. 2 Tap mode ______________________________________________________20-41
20.5. 4 Tap mode ______________________________________________________20-42
20.6. 8 Tap mode ______________________________________________________20-43
20.7. Sensor Interface __________________________________________________20-44
21. USB Camera Option____________________________________________ 21-45
22. Camera Control Program _______________________________________ 22-45
23. Application environments_______________________________________ 23-45
23.1. USB operation____________________________________________________23-45
23.2. The hardware connections are:______________________________________23-45
23.3. The software connections are: ______________________________________23-46
23.4. Using a FastVision supplied framegrabber ____________________________23-46
23.4.1. The hardware connections are:____________________________________________ 23-47
23.4.2. The software connections are:_____________________________________________ 23-47
23.5. Using a third-party framegrabber ____________________________________23-48
23.5.1. The hardware connections are:____________________________________________ 23-48
23.5.2. The software connections are:_____________________________________________ 23-49

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24. TROUBLESHOOTING __________________________________________ 24-50
25. FastVision TECHNICAL SUPPORT________________________________ 25-50
25.1. Contacting Technical Support_______________________________________25-50
25.2. Returning Products for Repair or Replacements _______________________25-50
25.3. Reporting Bugs___________________________________________________25-51

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1. INTRODUCTION
The FastCamera13 is a 1.3 megapixel CMOS camera with internal memory and FPGA’s that enable it to do
real-time processing. Thus it is what one would term a “smart” camera. The standard programming that is
supplied with the base camera forms the basis of the most used and demanded function for data
processing. It is expected that each customer may wish to customize this programming for its use. This
can be achieved by purchasing additional IP from FastVision or in-house development. Inquires or
discussions are always welcome.
2. FEATURES AND SPECIFICATIONS
The block diagram below shows the major subsystems in the camera. The camera is designed to support
many different applications by customization of the programmable logic in the camera. FastVision or the
customer can customize the size and content of the FPGAs and memory in the camera to contain many
different features, processing algorithms, and storage schemes. This manual discusses the ‘Standard’
version of the cameras. Customization of the FPGAs in the camera requires significant support from
FastVision. Please contact FastVision for a quote for the development tools and support.
1.3 MPixel
CMOS
Sensor
XC2VX000
FPGA
1-8 Million Gates
Camera
Control
LVDS
Link Receivers
(CC1-4)
(Async Serial)
66 MHz
Channel
Link Driver
66 MHz
Channel
Link Driver
(Optional)
128-1000MB
DDRAM
200 MHz
Three 85 MHz
Channel Link
Drivers
FPGA
Boot
Flash
Memory
Controller
FPGA
Power
Supply
2-4 MB
SRAM
CC1
CC2
CC3
CC4

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2.1.CAMERA SPECIFICATIONS
• The FastCamera13 uses a 1280H x 1024V (1.3 megapixel) CMOS digital image
sensor capable of 500 frames/second operation at full resolution
• 1280H x 1024V image resolution
• 12-micron-square active-pixel photodiodes
• 500+ frames per second, progressive-scan
• At full resolution, frame rate can go up to 500,000 fps at 1 x 1280pixels
• Monochrome or color (Bayer Pattern)
• Ten (10) parallel output ports
• Photobit® TrueColorTM Image Fidelity
• On-chip TrueBit® Noise Cancellation
• On-chip 10-bit analog-to-digital converters
• FPGA and memory-based configurable interface formats and onboard processing
• Supported by a full range of software tools
• Binning in order to achieve increased sensitivity at full frame rates
• Optional SRAM for ultra fast processing
• Optional additional DDRAM and increased FPGA size for additional processing
capability
• Trigger-able global electronic shutter (sync./async. modes)
• C holder mount (F with adaptor)
2.2.IMAGE SENSOR SPECIFICATIONS:
• Uses Micron Imaging’s MI-MV13 sensor
• 1280 x 1024 x 8 bits @ 500 fps (10 bits 400 fps)
• 15.36 mm x 12.29 mm active area
• 12-micron square active pixels
• 40% Fill Factor
• Monochrome or color (Bayer Pattern)
• On-chip Noise Cancellation
• Dynamic range 59 db
• Monochrome: 1000 bits per lux-second @ 550 nm
• Shutter 99.9% efficiency
• Noise 58 db (10 bit mode lowest sensor gain setting, nominal pixel of 512 counts)
2.3.Physical Specifications

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12.7mm
0 ref
39.5m
m
74.0mm
0 ref 7mm 132mm
12.7mm
7mm
0 ref
0 ref 39.5mm 79.0mm
J3 J2
P2
FastCamera13
Front View
FASTCAMERA13 CASE AND
MOUNTING DIMENSIONS
FastCamera13
Side View FastCamera13
Back Panel
FastCamera13
Bottom View

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2.4.Connectors
2.4.1. Power Connector HR10A-10R-12PB
Pin Function
1 Ground
2 +5 Volts
3 Ground
4 Reserved for application dependent I/O
5 Ground
6 +5 Volts
7 Reserved for application dependent I/O
8 Ground
9 +5 Volts
10 Reserved for application dependent I/O
11 +5 Volts
12 Reserved for application dependent I/O
2.4.2. Data Connector J2
Pin Signal Pin Signal
1 Ground 14 Ground
2 CL1_TXOUT0N 15 CL1_TXOUT0P
3 CL1_TXOUT1N 16 CL1_TXOUT1P
4 CL1_TXOUT2N 17 CL1_TXOUT2P
5 CL1_TXCLKOUTN 18 CL1_TXCLKOUTP
6 CL1_TXOUT3N 19 CL1_TXOUT3P
7 SERTCP 20 SERTCN
8 CC1N 21 SERTFGP
9 CC2P 22 CC1P
10 CC3N 23 CC2N
11 CC4P 24 CC3P
12 SERTFGN 25 CC4N
13 Ground 26 Ground
2.4.3. Data Connector J3
Pin Signal Pin Signal
1 Ground 14 Ground
2 CL2_TXOUT0N 15 CL2_TXOUT0P
3 CL2_TXOUT1N 16 CL2_TXOUT1P
4 CL2_TXOUT2N 17 CL2_TXOUT2P
5 CL2_TXCLKOUTN 18 CL2_TXCLKOUTP
6 CL2_TXOUT3N 19 CL2_TXOUT3P
7 Application Specific
I/O (P) 20 Application Specific I/O (N)
8 CL3_TXOUT0N 21 CL3_TXOUT0P
9 CL3_TXOUT1N 22 CL3_TXOUT1P
10 CL3_TXOUT2N 23 CL3_TXOUT2P
11 CL3_TXCLKOUTN 24 CL3_TXCLKOUTP
12 CL3_TXOUT3N 25 CL3_TXOUT3P
13 Ground 26 Ground

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3. POWER REQUIREMENTS
Power requirements are a strong function of the specific application; the camera is 15 Watts worst case, 5
to 10 Watts typical. Low noise +5 Volt input recommended. Internally the camera has high frequency
switching supplies that convert the 5 volt input to 3.3, 2.5 and 1.8 volts.
4. TIMING
 Camera Clock is configurable from 25 to 85 MHz depending on the application.
 Pixel data is valid when LVAL, FVAL and DVAL are true.
 Minimum two clocks LVAL and FVAL inactive between lines and frames.
 CC4 reserved for application specific needs.
5. TRIGGER MODES
Trigger modes are selected by serial commands.
Free Running, camera generates frames without triggers.
CC1 Positive edge triggered.
CC1 When active, expose, falling edge reads out the sensor.
Sensor readout can be in parallel with exposure.
The camera can be read out with 1,2, or 3 camera links, the serial port (for the really patient), or via the
USB port. Only image data from the selected ROI is sent. The camera can be configured to read out when
the image is taken, to read out from memory on serial command or the CC2 positive edge.
1.1.1.1 Data formats supported:
Mode Camera Link Format
MSB -------------------------------- LSB Read Out Mode
0 CL1_A[7:0] Single tap 8 bits
(Basic) (default)
1 CL1_B[1:0],CL1_A[7:0] Single tap 10 bits
(Basic)
2 CL1_A[7:0] even pixels (0,2,...)
CL1_B[7:0] odd pixels (1,3,...) Two Taps 8 bits (Basic)
3 CL1_B[1:0],CL1_A[7:0] even
CL1_B[5:4],CL1_C[7:0] odd Two Taps 10 bits (Basic)
4 CL1_A[7:0] Red, Y
CL1_B[7:0] Green, U
CL1_C[7:0] Blue, V
Three Taps 8 bits
(Color) (Basic)
5 CL1_B[1:0],CL1_A[7:0] Red, Y
CL1_B[5:4],CL1_C[7:0] Green, U
CL2_D[1:0],CL2_C[7:0] Blue, V
Three Taps 10 bits
(Color) (Medium)
6 CL1_B[7:0],CL1_A[7:0]
CL1_A[4:0] Red, U
CL1_B[2:0],CL1_A[7:5] Green, Y
CL1_B[7:3] Blue V
One tap 16 Bits
RGB565 (Basic)
7 CL1_A[7:0] pixels 4*n+0
CL1_B[7:0] pixels 4*n+1 Four Taps 8 bits (Medium)

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CL1_C[7:0] pixels 4*n+2
CL2_A[7:0] pixels 4*n+3
8 CL1_B[1:0],CL1_A[7:0] 4*n+0
CL1_B[5:4],CL1_C[7:0] 4*n+1
CL2_C[1:0],CL2_B[7:0] 4*n+2
CL2_C[4:5],CL2_A[7:0] 4*n+3
Four Taps 10 bits
(Medium)
9 CL1_A[7:0] pixels 5*n+0
CL1_B[7:0] pixels 5*n+1
CL1_C[7:0] pixels 5*n+2
CL2_A[7:0] pixels 5*n+3
CL2_B[7:0] pixels 5*n+4
Five Taps 8 bits
(Medium)
10 CL1_B[1:0],CL1_A[7:0] 5*n+0
CL1_B[5:4],CL1_C[7:0] 5*n+1
CL2_C[1:0],CL2_B[7:0] 5*n+2
CL2_C[4:5],CL2_A[7:0] 5*n+3
CL3_C[1:0],CL3_B[7:0] 5*n+4
Five Taps 10 bits
(Full)
11 CL1_A[7:0] R even
CL1_B[7:0] G even
CL1_C[7:0] B even
CL2_A[7:0] R odd
CL2_B[7:0] G odd
CL2_C[7:0] B odd
Six Taps 8 bits (Color)
(Medium)
12 CL1_B[1:0],CL1_A[7:0] R even
CL1_B[5:4],CL1_C[7:0] G even
CL2_C[1:0],CL2_B[7:0] B even
CL2_C[4:5],CL2_A[7:0] R odd
CL3_C[1:0],CL3_B[7:0] G odd
CL3_C[5:4],CL3_A[7:0] B odd
Six Taps 10 bits
(Color) (Full)
13 CL1_A[7:0] 8*n+0
CL1_B[7:0] 8*n+1
CL1_C[7:0] 8*n+2
CL2_A[7:0] 8*n+3
CL2_B[7:0] 8*n+4
CL2_C[7:0] 8*n+5
CL3_A[7:0] 8*n+6
CL3_B[7:0] 8*n+7
Eight Taps 8 bits (Full)
14 CL1_B[1:0],CL1_A[7:0] 8*n+0
CL1_B[5:4],CL1_C[7:0] 8*n+1
CL2_B[1:0],CL2_A[7:0] 8*n+2
CL2_B[5:4],CL2_C[7:0] 8*n+3
CL3_B[1:0],CL3_A[7:0] 8*n+4
CL3_B[5:4],CL3_C[7:0] 8*n+5
CL2_FVAL,CL2_LVAL,CL2_SP,CL1_SP,
CL1_B[7:6],CL1_B[3:2] 8*n+6
CL3_FVAL,CL3_LVAL,CL1_DVAL,CL3_SP,
CL2_B[7:6],CL2_B[3:2] 8*n+7
Eight Taps 10 bits
(Full)
254 NA Use Serial Port
255 NA Use USB

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Other modes are possible with custom FPGA configurations purchased from FastVision or developed in-
house.
6. CAMERA DATA FLOW
Sensor
128-1000MB
DDR
Memory
SRAM
LUT
By Pixel
Gain &
Offset
Data
Format
Funnel
Camera
Links
Mem LUT
Exposure
Control
CC1 CC2CC3 Read
Memory
Serial
Settings
DDR
Tables
Clear
Memory
Or
Stop Filling
Trigger
Frame
Capture
ROI
Serial
Settings
Frame
Rate
And
Exposure
Serial
Settings
DDR Memory can be organized as a FIFO or as a circular buffer. CC3 is used to clear the memory (FIFO)
or stop filling the memory (circular buffer). CC2 is used to read the top most images from memory (FIFO) or
to read the oldest non-read image from memory (Circular buffer).
The LUT converts the input pixels (10 Bits) to the output pixel size (8 or 10 Bits). These tables can also be
used to improve the linearity of the sensor, or to set the gamma of the camera.
DDR Memory can be used for image averaging. In this mode Images are summed into a 32 bit per pixel
buffers, which can be read out at any time (CC2) and/or cleared (CC3).
CC1,CC2, and CC3 can be replaced by Serial Commands, or can be always enabled or disabled, for free
running operation.

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7. THE STANDARD CAMERA FUNCTIONALITY
The ‘Standard’ Camera is a set of FPGAs designed to support most of the typical uses of the camera. It is a
good starting point for modifications. This design is copyrighted IP from FastVision and forms the reference
design, which is available from FastVision for use only with the FastCamera13.
8. PIXEL GAIN AND OFFSET
The offset and gain of each pixel can be calibrated by setting the pixel gain and offset arrays in the DDR
memory of the camera. It is a good idea to do this as the large number of converters, need to be calibrated
for best results. Note: only the pixels in the selected ROI are processed (see serial commands 0x02 and
0x03).
The offset table is set by taking several images with no light input, averaging them and uploading them to
the offset (or dark field) table. These values are subtracted from the sensor pixel values (clipped so less
than zero values are zero), before applying the gain table values. The gain table values are obtained by
taking a defocused image of a uniform object, with enough light to get to 75% of saturation at most on the
brightest point in the image. Using the resulting image gain values are computed (in the simplest case the
pixel values and the ratio with 75% of full scale (191 (8 bit) or 768 (10 bits)) determines the gain.)
Note: It is assumed that you are trying for a uniformly lit field of view (i.e. a Flat Field). It is important that
you have as nearly as is practical, a uniform field of light, as large or small gain values can introduce
significant artifacts in your images.
The gain table contains 8 bit values, which are formatted unsigned 1.7 format, that is one binary digit
followed by 7 fractional digits. This makes the range of gains 1.992 down to 0.00390625.
The equation for the pixel gain and offset is:
CP[i,j] = Saturate((2*Gain[i,j]/256)* Clip (P[i,j] – Offset[i,j]))
CP = Corrected Pixel
P = Raw sensor Pixel
Clip = 0 if P[i,j]-Offset[i,j] is negative, otherwise its P[i,j]-Offset[i,j].
Saturate = FullScale if its input is greater than or equal to FullScale, other wise it is it’s input alue.
FullScale = 255 for 8 bit pixels 1023 for 10 bit pixels.
9. MEMORY OPTION
The camera has 120 MB (or more) memory, which can be used to store images, and do averaging. Each
mode of operation is explained in the following sections. If the memory option is enabled, then sensor data
goes to memory instead of down stream.
9.1.FIFO memory mode
In this mode memory is used as a first in first out memory (FIFO). The memory fills with images, until it
is full, and then stops filling. At any time the user may request an image from the FIFO with CC2, or via
a serial command. This will make room for a new image, which will be filled as soon as one is collected.
This mode is typically used by systems that can accept images in bursts, but can not accept a
continuous stream of images. For example your system might take 8 images very fast and then read
them out at a slower rate (via a single camera link for example), your average frame rate is slow, but
your peak rate is high. If the host activates CC2 (or sends the serial command), it can cause the next
image to be read out when it comes in (pre-trigger the readout).

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9.2.Circular buffer memory mode
In this mode the memory is used as a circular buffer. Each time an image is presented to the memory it
is stored over-writing the oldest image in the buffer. When CC2 goes active (or via a serial command),
the filling operation stops, after a selected number of frames are added to the memory buffer (delayed
trigger). After the memory image collection stops, each time CC2 toggles (or by serial command) the
oldest remaining image is sent to the host. After the first CC2 is sent the host may send the next CC2 right
away it does not have to wait for the filling to finish. Each image will be sent to the host as it becomes
available. After the memory is full the camera will not accept any more images until it is read out or reset
via CC3 (or serial command). If the host is draining images as fast as they are coming in the image capture
will never stop. A reset (CC3) is required to re-arm the trigger and delay process.
9.3.Image summing memory mode
In this mode the memory is divided up into buffers the size of the selected ROI, but with 32 bit values.
Each time an image is added to memory, it is added to the current average buffer. When a
programmed count of images is exceeded, the system advances to the next buffer. When all the
buffers are full, the system stops until it is read out (CC2) or reset (CC3). Note: as each buffer is read
out (CC2) it is reset. If the host reads out the buffers faster than they are collected, image collection will
not stop. For example you can program the camera to total 10 images in each buffer, before passing it
to the host. The host triggers the readout via CC2 (or serial command).The CC2 trigger may be sent at
any time, the camera will provide a total buffer when it becomes available.
10. LOOKUP TABLE OPTION
If the lookup table option is enabled, the image data from up stream is passed through a lookup table. This
applies a point transformation to each pixel value, producing 10 bit results, from the 8 or 10 bit input. 32 Bit
totals bi-pass the block. (Or better you should not enable this block if you are doing image totaling, as it will
only operate on the lower 10 bits of the total.)
11. DATA FORMAT FUNNEL
The data format funnel takes the image data and parcels it out the camera links (or USB) as selected by the
Format Funnel mode. If 8 bit data is selected the upper 8 bits of each pixel is sent. (Note if you don’t like
that use the LUT to change this behavior).
32 Bit data total buffers are sent as 8 bit data in little endian (that is least significant byte first).
12. INTERNAL CAMERA MEMORY
The camera contains at least 128 MB of internal memory which can be expanded to 1000 MB, which can
be used to FIFO the input images, to allow burst exposure, and slow readout operation. Only the image
data in the selected ROI is stored. A serial command or the positive edge of CC3 can be used to clear FIFO
memory.
In addition the Camera contains LUTs for conversion from 8 to 10 bit data which can be uploaded via the
serial port.
13. SENSOR CONTROL

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13.1. Line Timing
Sensor line and frame rates are controlled by the Camera State settings. The minimum line period
depends on the sensor type and the ROI width. When the Line Period setting exceeds the minimum
period, extra clocks are inserted between lines. The Line Valid period only depends on the ROI width and
sensor type. The number of columns read from the sensor is always a multiple of 10 for the MV13 and 16
for the MV40 sensor. Since the Data FPGA also has access to the ROI settings it is possible for the actual
ROI width (as sent to the framegrabber) to start and end on any pixel, however this is not implemented.
The Control FPGA ensures that the starting and ending pixels of the ROI are read from the sensor. For the
MV13 this means that as many as 9 pixels before and 9 pixels after the ROI could be read from the sensor,
depending on the starting and stopping pixel values modulo 10. For the MV40 sensor as many as 15 pre-
and post-ROI pixels could be read from the sensor, depending on the starting and stopping pixel values
modulo 16. The software GUI is responsible for determining the actual number of pixels per line based on
the sensor and readout mode.
Camera-Link or USB readout rate can be the limiting factor for the line rate in non-memory modes. In this
case it is the GUI’s responsibility to maintain the Line Period setting large enough to prevent FIFO overrun
in the Data FPGA.
13.2. Frame Timing
In free-running mode the minimum frame period depends on the ROI height and the line period. When
either the frame period or exposure time setting exceeds the minimum period, extra clocks are inserted
between frames. A 32-bit frame time counter allows frame periods from the minimum up to 64 seconds in
increments of 15 nS.
In triggered modes the frame period is also affected by the exposure delay. In multiple trigger mode the
exposure delay only affects the time until the first readout of the trigger sequence and subsequent frames
run at the free-running rate as specified. In single-trigger mode with external exposure control, applying the
trigger faster than the maximum rate will cause the camera to skip triggers and run at a submultiple of the
trigger frequency. In multiple trigger mode and internal timed trigger mode, applying the trigger faster than
the maximum rate will result in the camera running at the specified free-run rate.
Trigger pipelining is provided so that a trigger event which occurs during exposure or readout (just during
readout in external exposure mode) will generate another frame.
13.3. Exposure Modes
The MV13 sensor is normally used in TrueSNAP shutter mode. The sensor has analog frame storage and
a transfer gate that allows exposure to overlap readout while exposing all lines together. The MV40 sensor
does not have analog storage and can only be exposed in a rolling shutter mode. Thus the individual lines
have different exposure windows which may or may not overlap depending on the line rate and exposure
time settings. This is the equivalent of using the MV13 sensor with the transfer gate on all the time.
When viewing high-speed motion, the MV13 works best if the lines are read out at the maximum possible
rate while additional time for exposure or frame period is inserted between frames. This maximizes the
overlap in the line exposure times. Unfortunately in the non-memory readout modes with reduced output
rates just the opposite must be done. Long interline delays in these modes causes excessive temporal
distortion in the moving image. This can appear as stretching or shrinking of vertically moving objects or
trapezoidal distortion of horizontally moving objects.
13.4. Trigger Modes

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There are four basic trigger modes:
• Free-running mode ignores trigger inputs and reads out the sensor continuously at a programmed
frame rate with programmed exposure timing.
• Multi-frame edge-triggered mode activates a programmed number of exposures after a programmed
delay at a programmed frame rate with programmed exposure timing.
• Single edge-triggered mode activates a programmed exposure after a programmed delay.
• External exposure mode exposes during the active trigger period.
Free-running mode allows continuous readout at rates ranging from about one frame per minute to the
maximum capability of the sensor. Exposure can be programmed in increments of 15 nS up to the frame
period. There are gaps in the allowable exposure times due to interaction between the readout circuitry
and pixel reset in the MV13 sensor. In the MV40 sensor the exposure time is even more restricted due to
the rolling shutter mode of operation. The Control FPGA will generate the exposure timing as close as
possible to the requested value.
Multi-frame edge-triggered mode effectively starts the camera into free-running mode for a programmed
number of frames after a delay of zero to about 64 seconds programmable in 15 nS increments. The active
edge of the trigger activates the time delay and the first exposure starts after this delay. The camera can
be re-triggered during active readout. If re-trigger event occurs too soon to start the subsequent exposure
after the programmed delay, the next exposure will start as soon as possible thereafter. This prevents the
effect of running at submultiples of the trigger rate when the trigger rate exceeds the capability of the
camera.
Single edge-triggered mode is the same as asynchronous multi-frame edge-triggered mode with the frame
count set to 1.
External exposure mode starts exposure as soon as possible after the active-going edge of the trigger and
stops exposure as soon as possible after the inactive-going edge of the trigger. For the MV13, this
provides accurate exposure timing based on the trigger pulse width. For the MV40, limitations of the rolling
shutter limit the exposure timing resolution to the line readout rate unless the exposure time exceeds the
readout time. Subsequent exposures can overlap readout of the current frame in this mode. This can
place further restrictions on the exposure timing resolution in both sensor types.
The MV13 camera has “synchronous” and “asynchronous” modes of exposure. These only apply to free-
running and multi-frame modes. Single-frame and external modes are always “asynchronous.” When the
synchronous trigger mode bit is set, the exposure timing is linked to the readout timing to avoid exposure
period jitter that can occur when the readout overlaps the exposure. In multi-frame triggered mode, the
synchronous mode also creates an additional delay of one readout time that must be added to the
programmed delay to find the actual delay to the first exposure.
13.5. Trigger Options

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There are four trigger sources - Camera Link CC1, TTL trigger input, Serial, and USB (via I2C).
• The CC1 and TTL sources can be enabled or disabled. They can also be active high (positive-going
edge for edge-triggering or high level for external exposure) or active low (negative-going edge for
edge-triggering or low level for external exposure).
• The Serial source uses the “O” command. This cannot be disabled in the Control FPGA. It must be
disabled by the GUI if desired.
• The USB source uses writes to subaddress TBD. In external exposure mode two writes are required.
Writes to subaddress TBD with bit 0 high start the exposure, and writes to subaddress TBD with bit 0
low end the exposure. This cannot be disabled in the Control FPGA. It must be disabled by the GUI if
desired.
13.6. Trigger Outputs
There are two trigger outputs, both TTL level on the P2 power connector. One output is high whenever the
sensor is exposing. The other is high during the programmed delay period in the two edge-triggered
modes.
13.7. Reference Voltages
All sensor reference voltages are programmable and generated by two LTC1660 octal D/A converters. At
power-up the DAC’s are loaded with default values hard-coded into the Control FPGA. After the Data
FPGA has been loaded the DAC’s are updated with the settings in the default camera state storage page of
flash memory.
Comparators in the Control FPGA check for changes in the DAC settings and re-load the DAC’s whenever
the values are changed. This can happen as a result of the host command to set camera state, or the host
command to restore state from flash.
13.8. Calibration
Both the MV13 and MV40 sensors have automated ADC calibration to reduce column-wise fixed-pattern
noise. This is initiated at sensor reset or by using the CAL_START_N input. The Control FPGA always
uses the sensor reset to initiate calibration. In addition, the MV40 sensor allows direct access to the
internal calibration values on a serial interface consisting of the DATA_CLK, DATA, RE_N, and WE_N pins.
This version of the Control FPGA does not use this interface.
Automatic calibration is initiated after power-up when the sensor is released from reset. Reset is released
before the Data FPGA is loaded to allow the sensor to stabilize during the load process. Reset is re-
asserted for two clock cycles at the end of the initialization sequence, about TBD milliseconds after the
reference voltage DAC’s are updated from flash. This causes the sensor to re-calibrate with the new
reference voltage settings.
After power-on initialization, the sensor is only calibrated on demand by the host using the Reset and
Calibrate Sensor command. It is not automatically calibrated after changing the reference voltages. Thus
the camera control GUI is responsible for periodic calibration as required.
13.9. Power-on Initialization

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The Control FPGA has a small embedded micro that runs through an initialization sequence at power-on.
This same micro also implements the host, USB, and Data FPGA communication protocols and deals with
flash memory and DAC’s.
1. Immediately after power-on, the voltage reference DAC’s are programmed with factory default values.
This allows the sensor to stabilize under conditions close to the actual operating environment.
2. Page zero is read from the flash memory. This page holds information necessary to locate actual
power-on data in the flash.
3. The sensor is released from reset and allowed to self calibrate and stabilize.
4. The Data FPGA is loaded from flash. If the offset or length stored in the header are not valid, the
embedded micro skips to step 10. This may take several seconds depending on the FPGA size.
5. Camera State is read from one of the 8 pages as selected by the pointer in the header. If the pointer is
not valid (1 - 8) or the selected page is uninitialized, the embedded micro skips to step 10.
6. Reference DAC’s are reprogrammed with the updated values from flash.
7. Camera State is forwarded to the Data FPGA.
8. If the Pointer to the Data FPGA initialization area is valid and the length is valid and non-zero, the Data
FPGA initialization is read from flash and forwarded to the Data FPGA.
9. The sensor is briefly reset to start another auto-calibration cycle.
10. The embedded micro enters the command service loop.
14. FLASH MEMORY
Table 2 shows the layout of flash memory. The first page is used only for main header information.
Following this are eight pages for storing up to 8 camera states. Fast-Vision should reserve one of these
for factory defaults. The Control FPGA will not write protect the defaults page so the Camera Control GUI
should prevent the user from overwriting the factory settings, or it should have the factory default settings
available in the software to restore them without using the flash. Any of these states can be chosen as the
power-up default.
Flash Page Layout
Page Offset Pages Description
0 1 Flash Memory Header Page
1 1 Camera State Storage 1
2 1 Camera State Storage 2
3 1 Camera State Storage 3
4 1 Camera State Storage 4
5 1 Camera State Storage 5
6 1 Camera State Storage 6
7 1 Camera State Storage 7
8 1 Camera State Storage 8
9 1370 FPGA bitstream (sized for 2V1000 + 2V250)
1379 2716 Available for Data FPGA Initialization and User Data
4095 1 Reserved by Atmel

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Table 2 - Flash Memory Layout
Table 3 shows the layout of the first page in flash memory. This contains enough descriptors for the
Camera Control GUI to determine the camera type and its options. This data should only be programmed
by Fast-Vision. The camera GUI software must enforce this, as there is no write protection built into the
Control FPGA firmware. Multibyte values are little endian.
Page Zero Flash Header
Byte Offset Bytes Description
0 1 Flash Memory Part Type: 0x16 or 0x32 for 16 or 32 Mb flash
1 1 Flash Memory Revision ID: 0x01 for this revision
2 2 Offset in bytes to Camera ID data from top of page 0: 0x79 0x01
4 4 Flash page offset to FPGA data: 0x09 0x00 0x00 0x00
8 4 FPGA bitstream length in bytes
12 4 Flash page offset of Data FPGA initialization data
16 4 Data FPGA initialization data length in bytes
20 1 Camera State to load at power on (1 to 8)
20 357 Reserved for additional header / ID info
377 11 Part Number, ASCII “800??-5????”
388 3 Part Revision, ASCII “010”
391 9 Serial Number, ASCII “XXX??????”
400 128 FPGA bitstream file header from mkbin, Null terminated string
Table 3 - Flash Memory Header Page
15. CAMERA STATE STORAGE
Internal to the Control FPGA all state is saved in a Block RAM. Copies of the current state can be saved to
the flash or uploaded to the host. The current state can also be retrieved from flash or changed by the
host. Only the host has random access to the camera state and this only when setting state. Reading back
the camera state always sends the entire state to the host. Table 4 shows the layout of the camera state
memory. Except for sensor reference voltages, multibyte values are little endian.
Byte Offset (decimal) Bytes Description
0 4 C3, 5A, F0, 69 for detecting uninitialized buffers
4 2 Vln2: 14 D9
6 2 Vref1: 14 D9
8 2 Vtest: 20 00
10 2 Vref2: 23 E0
12 2 Vbias1: 30 00
14 2 Vref3: 32 E8
16 2 Vbias2: 40 00
18 2 Vref4: 41 36
20 2 Vbias3: 50 00
22 2 Vln1: 54 D9
24 2 Vbias4: 60 00
26 2 Vlp: 64 D9
28 2 Vunused1: 70 00
30 2 Vclamp3: 70 00
32 2 Vunused2: 80 00
34 2 Vrstpix: 8D 17
36 2 ROI Start Pixel
38 2 ROI End Pixel

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40 2 ROI Start Line
42 2 ROI End Line
44 2 Line Period in Pixel Clocks
46 4 Exposure Time in Pixel Clocks
50 4 Frame Period in Pixel Clocks
54 4 Exposure Delay in Pixel Clocks
58 2 Serial Link Bit Period in Pixel Clocks
60 1 Camera Link Readout Mode
61 1 Camera Link Clock Frequency
62 1 Binning
63 1 Memory Options
64 1 Sensor Resolution - 8/10 bit
65 2 Trigger Mode (2nd Byte is Data FPGA dependent)
67 1 Frame count for Multi-Trigger mode
68 1 CC Mode: CC2, CC3, CC4 enable and edge select
69 59 Reserved for Control FPGA / base system extension
128 384 Available for Data FPGA functionality extensions
Table 4 - Camera State Memory Layout
Sensor reference voltages are presented to the DAC’s exactly as they are stored in the state. The order
listed above is the recommended order, but other orders may work. The format for these is MS byte first
with the most significant nibble indicating the command code to the DAC. Pairs of values are sent, one to
each DAC chip with the first going to U25 and the second to U26. Voltages are updated in the order sent.
Default values shown are for the FastCamera 13. For more information see the LTC1660 data sheet.
Whenever the state memory is updated from host or flash, the actual internal registers that implement the
camera state change, too. Some of these are located in the Control FPGA and some in the Data FPGA.
The Control FPGA forwards state data to the Data FPGA whenever it is updated.
The state memory holds all of the state variables currently defined for camera operational modes as well as
some additional storage that can be defined as required for more sophisticated Data FPGAs. The Data
FPGAs can count on this storage to be refreshed from flash after initial FPGA load and whenever the user
restores state from one of the saved sets in flash.
In addition to the camera state storage pages, some of the flash memory is available for Data FPGA
storage requirements such as pixel defect maps. The amount of flash available for this depends on the
size of the Data FPGA and the size of the flash device. A pointer in the flash header in page zero indicates
the starting page of the Data FPGA initialization area. Its length in pages (which may be zero) is stored in
the flash header as well. Data from this initialization area is read out and sent to the data FPGA after initial
FPGA load. Although the data in these pages has no predefined layout, the first page must start with the
sequence 3C, A5, 0F, 96. This prevents transmission of uninitialized flash pages and serves to identify the
following data as Data FPGA Initialization Data rather than Camera State.
16. SERIAL CONTROL INTERFACE