The signal names, nominal voltages, maximum load current, and designated targets
are the following:
Signal name V A Targets N tes
VCC1 1.010FPGA Core voltage
VCC1V8 1.810DDR2 RA ain supply
. . LDO Feed for DDR2 Ref.
. . FPGA I/O Bank 11,13,15,17,(19,21)
. . FLASH Internal voltage
VCC2V5 2.510LDO Feed For GT LDOs
. . FPGA Auxiliary voltage
. . XFP/XAUI Auxiliary voltage
VCC3V3 3.310XFPs .
. . FPGA I/O Bank 20,1,3,0,2,4,(12,5,23,18,6,25)
. . Feature Conn.for I/O std. only
. . FLASH/JTAG I/O voltage
. . DDR2 Supply SPD RO
VCC0V9 0.93 DDR2 Reference voltage
AVCC1 1.03 FPGA GT GT's core voltage
AVCPLL1V2 1.23 FPGA GT GT's PLL supply
VCC5 5 . XFP aux. XPF aux. power
VCC1V2 1.222XFP/XAUI XFP/XAUI converter ain supply
2.2 Cl ck s urces
There are three clock sources available on SGA10GD for the FPGA cores. The
following tables shows their name, nominal frequencies, designated FPGA pins, and
their application.
Signal f [MHz]FPGA# Applicati n
GCLKN 200.00 L18 System/Global Clock, and
GCLKP (XO) K17 DDR2 reference clock
REF2CKN *156.25 H3 XFP Gigabit Ethernet App.
REF2CKP (XO) H4
GT3RCKN *100.00 Y3 PCI Express Hosts reference
GT3RCKP - Y4 .
* These clock references are routed to GT clock pins.
XO designates LVPECL Crystal Oscillators.
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