Freescale Semiconductor MPC8358E Owner's manual

© 2011 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
This document provides an overview ofthe MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing therequirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,
Rev. 3.
To locate any updates for this document, refer to the
MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.
Document Number: MPC8360EEC
Rev. 4, 01/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . 13
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 17
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 20
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 28
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 62
19. HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
21. Package and Pin Listings . . . . . . . . . . . . . . . . . 68
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
24. System Design Information . . . . . . . . . . . . . . 102
25. Ordering Information . . . . . . . . . . . . . . . . . . . 106
26. Document Revision History . . . . . . . . . . . . . 107
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
2Freescale Semiconductor
Overview
1Overview
This section describes a high-level overview including features and general operation of the
MPC8360E/58E PowerQUICC II Pro processor. A major component of this device is the e300 core, which
includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™
603e instruction set. The new QUICC Engine module provides termination, interworking, and switching
between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine
module’s enhanced interworking eases the transition and reduces investment costs from ATM to IP based
systems. The other major features include adual DDR SDRAM memory controller for the MPC8360E,
which allows equipment providers to partition system parameters and data in an extremely efficient way,
such as using one 32-bit DDR memory controller for control plane processing and the other for data plane
processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also
offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.
Figure 1 shows the MPC8360Eblock diagram.
Figure 1. MPC8360E Block Diagram
Memory Controllers
GPCM/UPM/SDRAM
32/64 DDR Interface Unit
PCI Bridge
Local Bus
Bus Arbitration
DUART
Dual I2C
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Clock Synthesizer
System Interface Unit
(SIU)
Local
Baud Rate
Generators
Multi-User
RAM
UCC8
Parallel I/O
Accelerators
Dual 32-Bit RISC CP
Serial DMA
&
2 Virtual
DMAs
2 GMII/
RGMII/TBI/RTBI
8 MII/
RMII
8 TDM Ports 2 UTOPIA/POS
(124 MPHY)
Serial Interface
QUICC Engine Module
JTAG/COP
Power
Management
Timers
FPU
Classic G2 MMUs
32KB
D-Cache
32KB
I-Cache
Security Engine
e300 Core
PCI
DDRC1
UCC7 UCC6 UCC5 UCC4 UCC3 UCC2 UCC1
MCC
USB
SPI2
Time Slot Assigner
DDRC2
SPI1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 3
Overview
Figure 2 shows the MPC8358E block diagram.
Figure 2. MPC8358E Block Diagram
Major features of the MPC8360E/58E are as follows:
• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the Freescale processor families implementing the Power
Architecture™ technology
• QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each
operating up to 500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
Memory Controllers
GPCM/UPM/SDRAM
32/64 DDR Interface Unit
PCI Bridge
Local Bus
Bus Arbitration
DUART
Dual I2C
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Clock Synthesizer
System Interface Unit
(SIU)
Local
Baud Rate
Generators
Multi-User
RAM
UCC8
Parallel I/O
Accelerators
Dual 32-Bit RISC CP
Serial DMA
&
2 Virtual
DMAs
2 GMII/
RGMII/TBI/RTBI
6 MII/
RMII
4 TDM Ports 1 UTOPIA/POS
(31/124 MPHY)
Serial Interface
QUICC Engine Module
JTAG/COP
Power
Management
Timers
FPU
Classic G2 MMUs
32KB
D-Cache
32KB
I-Cache
Security Engine
e300 Core
PCI
DDRC
UCC5 UCC4 UCC3 UCC2 UCC1
USB
SPI2
Time Slot Assigner
SPI1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
4Freescale Semiconductor
Overview
— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)
— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the
MPC8358E supporting the following protocols and interfaces (not all of them simultaneously):
– IEEE 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a
media-independent interface (MII, RMII, RGMII)1
– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent
interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
– 9.6-Kbyte jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in
accordance ITU-T I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex
(with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM
forum TM4.1 for up to 64-Kbyte simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance
with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in
accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001
(Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686, and 3153
– IP support for IPv4 packets including TOS, TTL, and header checksum processing
– Ethernet over first mile IEEE 802.3ah
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including
bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
1.SMII or SGMII media-independent interface is not currently supported.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 5
Overview
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels
— One multichannel communication controller (MCC) only on the MPC8360E supporting the
following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces
— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional
2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E
supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with
1-bit mode for E3/T3 rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC
and MCC serial channels (MCC is only available on the MPC8360E)
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
–DES,3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
6Freescale Semiconductor
Overview
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
• Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory
controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus;
on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the
MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers,
both support ECC)
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open
pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 7
Overview
• PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
8Freescale Semiconductor
Electrical Characteristics
• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer
embedded hardware
• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3].
There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with
other QE functions.
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
• IEEE Std. 1149.1™-compliant, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are
independent of theI/O cell, but are included for amore completereference. These are not purely I/Obuffer
design specifications.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 9
Electrical Characteristics
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic Symbol Max Value Unit Notes
Core supply voltage
For QUICC Engine module frequencies <500 MHz and e300
frequencies <667 MHz
For a QUICC Engine module frequency of 500 MHz or an e300
frequency of 667 MHz
VDD
–0.3 to 1.32
–0.3 to 1.37
V—
PLL supply voltage
For QUICC Engine module frequencies <500 MHz and e300
frequencies <667 MHz
For a QUICC Engine module frequency of 500 MHz or an e300
frequency of 667 MHz
AVDD
–0.3 to 1.32
–0.3 to 1.37
V—
DDR and DDR2 DRAM I/O voltage
DDR
DDR2
GVDD
–0.3 to 2.75
–0.3 to 1.89
V—
Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63 V —
PCI, local bus, DUART, system control and power management, I2C,
SPI, and JTAG I/O voltage
OVDD –0.3 to 3.63 V —
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5
Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5
Local bus, DUART, CLKIN, system control
and power management, I2C, SPI, and
JTAG signals
OVIN – 0.3 to (OVDD + 0.3) V 3, 5
PCI OVIN –0.3 to (OVDD + 0.3) V 6
Storage temperature range TSTG –55 to 150 °C—
Notes:
1. Functional and tested operating conditions are given in Ta bl e 2 . Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: LV IN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 4.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
10 Freescale Semiconductor
Electrical Characteristics
2.1.2 Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit Notes
Core supply voltage
For QUICC Engine module frequencies <500 MHz and e300
frequencies <667 MHz
For a QUICC Engine module frequency of 500 MHz or an e300
frequency of 667 MHz
VDD
1.2 V ± 60 mV
1.3 V ± 50 mV
V1
PLL supply voltage
For QUICC Engine module frequencies <500 MHz and e300
frequencies <667 MHz
For a QUICC Engine module frequency of 500 MHz or an e300
frequency of 667 MHz
AVDD
1.2 V ± 60 mV
1.3 V ± 50 mV
V1
DDR and DDR2 DRAM I/O supply voltage
DDR
DDR2
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Three-speed Ethernet I/O supply voltage LVDD0 3.3 V ± 330 mV
2.5 V ± 125 mV
V—
Three-speed Ethernet I/O supply voltage LVDD1 3.3 V ± 330 mV
2.5 V ± 125 mV
V—
Three-speed Ethernet I/O supply voltage LVDD2 3.3 V ± 330 mV
2.5 V ± 125 mV
V—
PCI, local bus, DUART, system control and power management, I2C, SPI,
and JTAG I/O voltage
OVDD 3.3 V ± 330 mV V —
Junction temperature TJ0 to 105
–40 to 105
°C2
Notes:
1. GVDD
, LVDD , OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
2. The operating conditions for junction temperature, TJ, on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is
0°to 70 °C. Refer to Errata General9 in
Chip Errata for the MPC8360E, Rev. 1 .

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 11
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltages at the interfaces of the device.
Figure 3. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Figure 4 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V
signals, respectively.
Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/OVDD + 20%
G/L/OVDD
G/L/OVDD + 5%
of tinterface1
1. Note that tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
Undervoltage
Waveform
Overvoltage
Waveform
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
4 ns
(Max)
–3.5 V
7.1 V p-to-p
(Min)
62.5 ns
+3.6 V
0 V
4 ns
(Max)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
12 Freescale Semiconductor
Electrical Characteristics
2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2 Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
2.2.1 Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages
(GVDD, LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the
power suppliesare stable and if the I/Ovoltages are supplied before the corevoltage, there maybe a period
of time that all input and output pins will actively be driven and cause contention and excessive current.
In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core
voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 5.
Table 3. Output Drive Capability
Driver Type Output Impedance (Ω) Supply Voltage
Local bus interface utilities signals 42 OVDD = 3.3 V
PCI signals 25
PCI output clocks (including PCI_SYNC_OUT) 42
DDR signal 20
36 (half-strength mode)1
1DDR output impedance values for half strength mode are verified by design and not tested.
GVDD = 2.5 V
DDR2 signal 18
36 (half-strength mode)1
GVDD = 1.8 V
10/100/1000 Ethernet signals 42 LVDD = 2.5/3.3 V
DUART, system control, I2C, SPI, JTAG 42 OVDD = 3.3 V
GPIO signals 42 OVDD = 3.3 V
LVDD = 2.5/3.3 V

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 13
Power Characteristics
Figure 5. Power Sequencing Example
I/O voltage supplies (GVDD,LVDD, andOVDD) do not have any ordering requirements with respect to one
another.
2.2.2 Power-Down Sequencing
The MPC8360E/58E does notrequire the core supplyvoltage andI/O supply voltagestobe powered down
in any particular order.
3 Power Characteristics
The estimated typical power dissipation values are shown in Table 4 and Table 5.
Table 4. MPC8360E TBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz) Typical Maximum Unit Notes
266 266 500 5.0 5.6 W 2, 3, 5
400 266 400 4.5 5.0 W 2, 3, 4
533 266 400 4.8 5.3 W 2, 3, 4
667 333 400 5.8 6.3 W 3, 6, 7, 8
500 333 500 5.9 6.4 W 3, 6, 7, 8
I/O Voltage (GVDD, LVDD, OVDD)
Core Voltage (VDD, AVDD)
90%
0.7 V
Time
Voltage

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
14 Freescale Semiconductor
Power Characteristics
667 333 500 6.1 6.8 W 2, 3, 5, 9
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD
. For I/O power values, see Ta b le 6 .
2. Typical power is based on a voltage of VDD = 1.2 V or 1.3 V, a junction temperature of TJ= 105°C, and a Dhrystone benchmark
application.
3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TAtarget, and I/O
power.
4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ= 105°C, and an artificial smoke test.
5. Maximum power is based on a voltage of VDD = 1.3 V for applications that use 667 MHz (CPU)/500 (QE) with WC process,
a junction TJ= 105°C, and an artificial smoke test.
6. Typical power is based on a voltage of VDD = 1.3 V, a junction temperature of TJ= 70°C, and a Dhrystone benchmark
application.
7. Maximum power is based on a voltage of VDD = 1.3 V for applications that use 667 MHz (CPU) or 500 (QE) with WC process,
a junction TJ= 70°C, and an artificial smoke test.
8. This frequency combination is only available for rev. 2.0 silicon.
9. This frequency combination is not available for rev. 2.0 silicon.
Table 5. MPC8358E TBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz) Typical Maximum Unit Notes
266 266 300 4.1 4.5 W 2, 3, 4
400 266 400 4.5 5.0 W 2, 3, 4
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD
. For I/O power values, see Ta b le 6 .
2. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ= 105°C, and a Dhrystone benchmark
application.
3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TAtarget, and I/O
power.
4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ= 105°C, and an artificial smoke test.
Table 4. MPC8360E TBGA Core Power Dissipation1(continued)
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz) Typical Maximum Unit Notes

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 15
Clock Input Timing
Table 6 shows the estimated typical I/O power dissipation for the device.
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.
NOTE
The rise/fall time on QUICC Engine block input pins should not exceed 5
ns. This should be enforced especially on clock signals. Rise time refers to
signal transitions from 10% to 90% of VDD; fall time refers to transitions
from 90% to 10% of VDD.
Table 6. Estimated Typical I/O Power Dissipation
Interface Parameter GVDD
(1.8 V)
GVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V) Unit Comments
DDR I/O
65% utilization
Rs= 20 Ω
Rt= 50 Ω
2 pairs of clocks
200 MHz, 1 ×32 bits 0.3 0.46 — — — W —
200 MHz, 1 ×64 bits 0.4 0.58 — — — W —
200 MHz, 2 ×32 bits 0.6 0.92 — — — W —
266 MHz, 1 ×32 bits 0.35 0.56 — — — W —
266 MHz, 1 ×64 bits 0.46 0.7 — — — W —
266 MHz, 2 ×32 bits 0.7 1.11 — — — W —
333 MHz, 1 ×32 bits 0.4 0.65 — — — W —
333 MHz, 1 ×64 bits 0.53 0.82 — — — W —
333 MHz, 2 ×32 bits 0.81 1.3 — — — W —
Local Bus I/O
Load = 25 pf
3 pairs of clocks
133 MHz, 32 bits — — 0.22 — — W —
83 MHz, 32 bits — — 0.14 — — W —
66 MHz, 32 bits — — 0.12 — — W —
50 MHz, 32 bits — — 0.09 — — W —
PCI I/O
Load = 30 pF
33 MHz, 32 bits — — 0.05 — — W —
66 MHz, 32 bits — — 0.07 — — W —
10/100/1000
Ethernet I/O
Load = 20 pF
MII or RMII — — — 0.01 — W Multiply by
number of
interfaces used.
GMII or TBI — — — 0.04 — W
RGMIIorRTBI ————0.04W
Other I/O — — — 0.1 — — W —

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
16 Freescale Semiconductor
Clock Input Timing
4.1 DC Electrical Characteristics
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
4.2 AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.7 OVDD + 0.3 V
Input low voltage — VIL –0.3 0.4 V
CLKIN input current 0 V ≤ VIN ≤ OVDD IIN —±10μA
PCI_SYNC_IN input current 0 V ≤ VIN ≤ 0.5V or
OVDD – 0.5V ≤ VIN ≤ OVDD
IIN —±10μA
PCI_SYNC_IN input current 0.5 V ≤ VIN ≤ OVDD – 0.5 V IIN —±100μA
Table 8. CLKIN AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
CLKIN/PCI_CLK frequency fCLKIN — — 66.67 MHz 1
CLKIN/PCI_CLK cycle time tCLKIN 15 — — ns —
CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2
CLKIN/PCI_CLK duty cycle tKHK/tCLKIN 40 — 60 % 3
CLKIN/PCI_CLK jitter — — — ±150 ps 4, 5
Notes:
1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or minimum
operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 17
RESET Initialization
4.3 Gigabit Reference Clock Input Timing
Table 9 provides the Gigabit reference clocks (GTX_CLK125) AC timing specifications.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8360E/58E.
5.1 RESET DC Electrical Characteristics
Table 10 provides the DC electrical characteristics for the RESET pins of the device.
Table 9. GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter/Condition Symbol Min Typical Max Unit Notes
GTX_CLK125 frequency tG125 — 125 — MHz —
GTX_CLK125 cycle time tG125 —8—ns—
GTX_CLK rise and fall time
LV DD = 2.5 V
LV DD = 3.3 V
tG125R/tG125F ——
0.75
1.0
ns 1
GTX_CLK125 duty cycle
GMII & TBI
1000Base-T for RGMII & RTBI
tG125H/tG125
45
47
—
55
53
%2
GTX_CLK125 jitter — — — ±150 ps 2
Notes:
1. Rise and fall times for GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3V.
2. GTX_CLK125 is used to generate the GTX clock for the UCC Ethernet transmitter with 2% degradation. The GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by GTX_CLK.
See Section 8.2.2, “MII AC Timing Specifications,” Section 8.2.3, “RMII AC Timing Specifications,” and Section 8.2.5, “RGMII
and RTBI AC Timing Specifications” for the duty cycle for 10Base-T and 100Base-T reference clock.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Input high voltage VIH —2.0OV
DD + 0.3 V
Input low voltage VIL — –0.3 0.8 V
Input current IIN ——±10μA
Output high voltage VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
18 Freescale Semiconductor
RESET Initialization
5.2 RESET AC Electrical Characteristics
This section describes the AC electrical specifications for the reset initialization timing requirements of
the device. Table 11 provides the reset initialization AC timing specifications for the DDR SDRAM
component(s).
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Notes:
1. This table applies for pins PORESET
, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow 32 — tPCI_SYNC_IN 1
Required assertion time of PORESET with stable clock applied to CLKIN
when the device is in PCI host mode
32 — tCLKIN 2
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the device is in PCI agent mode
32 — tPCI_SYNC_IN 1
HRESET/SRESET assertion (output) 512 — tPCI_SYNC_IN 1
HRESET negation to SRESET negation (output) 16 — tPCI_SYNC_IN 1
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI host mode
4—t
CLKIN 2
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device is
in PCI agent mode
4—t
PCI_SYNC_IN 1
Input hold time for POR config signals with respect to negation of HRESET 0— ns
Time for the device to turn off POR config signals with respect to the
assertion of HRESET
—4 ns 3
Time for the device to turn on POR config signals with respect to the negation
of HRESET
1—t
PCI_SYNC_IN 1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10. RESET Pins DC Electrical Characteristics (continued)
Characteristic Symbol Condition Min Max Unit

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor 19
RESET Initialization
Table 12 provides the PLL and DLL lock times.
5.3 QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine
block’s communication interfaces.
NOTE
The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting theperformance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.
Table 13 lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block
core frequency for each interface.
Table 12. PLL and DLL Lock Times
Parameter/Condition Min Max Unit Notes
PLL lock times — 100 μs—
DLL lock times 7680 122,880 csb_clk cycles 1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.
Table 13. QUICC Engine Block Operating Frequency Limitations
Interface Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1(MHz)
Notes
Ethernet Management: MDC/MDIO 10 (max) 10 20 —
MII 25 (typ) 100 50 —
RMII 50 (typ) 100 50 —
GMII/RGMII/TBI/RTBI 125 (typ) 1000 250 —
SPI (master/slave) 10 (max) 10 20 —
UCC through TDM 50 (max) 70 8 ×F2
MCC 25 (max) 16.67 16 ×F 2, 4
UTOPIA L2 50 (max) 800 2 ×F2
POS-PHY L2 50 (max) 800 2 ×F2
HDLC bus 10 (max) 10 20 —
HDLC/transparent 50 (max) 50 8/3 ×F2,3

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
20 Freescale Semiconductor
DDR and DDR2 SDRAM
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8360E/58E.
6.1 DDR and DDR2 SDRAM DC Electrical Characteristics
Table 14 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
UART/async HDLC 3.68 (max internal ref
clock)
115 (Kbps) 20 —
BISYNC 2 (max) 2 20 —
USB 48 (ref clock) 12 96 —
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 1.71 1.89 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.125 GVDD + 0.3 V —
Input low voltage VIL –0.3 MVREF – 0.125 V —
Output leakage current IOZ —±10μA4
Output high current (VOUT = 1.420 V) IOH –13.4 — mA —
Output low current (VOUT = 0.280 V) IOL 13.4 — mA —
MVREF input leakage current IVREF —±10μA—
Table 13. QUICC Engine Block Operating Frequency Limitations (continued)
Interface Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1(MHz)
Notes