Freescale Semiconductor MPC8313E PowerQUICC II Pro User manual

MPC8313E PowerQUICC™ II Pro
Integrated Processor
Family Reference Manual
Supports
MPC8313E
MPC8313
MPC8313ERM
Rev. 2
12/2008

Document Number: MPC8313ERM
Rev. 2, 12/2008
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number Title
Page
Number
Co nt en ts
About This Book
Audience.......................................................................................................................lxxiii
Organization..................................................................................................................lxxiii
Suggested Reading......................................................................................................... lxxv
General Information................................................................................................... lxxv
Related Documentation............................................................................................. lxxvi
Conventions .................................................................................................................. lxxvi
Signal Conventions...................................................................................................... lxxvii
Acronyms and Abbreviations ...................................................................................... lxxvii
Chapter 1
Overview
1.1 MPC8313E PowerQUICC II Pro Processor Overview ...................................................1-1
1.2 MPC8313E Architecture Overview................................................................................. 1-7
1.2.1 Power Architecture Core ............................................................................................. 1-7
1.2.2 Security Engine......................................................................................................... 1-10
1.2.3 DDR Memory Controller........................................................................................... 1-10
1.2.4 Dual Enhanced Three-Speed Ethernet Controllers.................................................... 1-11
1.2.5 PCI Controller............................................................................................................1-12
1.2.5.1 PCI Bus Arbitration Unit....................................................................................... 1-13
1.2.6 Universal Serial Bus (USB) 2.0................................................................................. 1-13
1.2.6.1 USB Dual-Role Controller .................................................................................... 1-14
1.2.7 Enhanced Local Bus Controller (eLBC).................................................................... 1-14
1.2.8 Integrated Programmable Interrupt Controller (IPIC)...............................................1-16
1.2.9 Dual I2C Interfaces .................................................................................................... 1-16
1.2.10 DMA Controller......................................................................................................... 1-17
1.2.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)...............................1-17
1.2.12 Serial Peripheral Interface (SPI)................................................................................1-18
1.2.13 System Timers ........................................................................................................... 1-18
1.3 Application Examples.................................................................................................... 1-18
1.3.1 Low-End Printer CPU and Interface ASIC................................................................ 1-19
1.3.2 High-End Printer I/O Processor................................................................................. 1-20
1.3.3 IEEE Std. 1588 in Test and Measurement and Industrial Automation...................... 1-21
1.3.4 IEEE Std. 802.11n WLAN Access Point................................................................... 1-23
1.3.5 Media Server.............................................................................................................. 1-24

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Contents
Paragraph
Number Title
Page
Number
Chapter 2
Memory Map
2.1 Internal Memory Mapped Registers ................................................................................ 2-1
2.2 Accessing IMMR Memory From the Local Processor.................................................... 2-1
2.3 Complete IMMR Map ..................................................................................................... 2-1
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-12
3.3 Output Signal States During Reset ................................................................................ 3-13
3.4 External Signal Description........................................................................................... 3-14
Chapter 4
Reset, Clocking, and Initialization
4.1 External Signals ...............................................................................................................4-1
4.1.1 Reset Signals................................................................................................................4-1
4.1.2 Clock Signals............................................................................................................... 4-3
4.2 Functional Description..................................................................................................... 4-4
4.2.1 Reset Operations.......................................................................................................... 4-4
4.2.1.1 Reset Causes............................................................................................................ 4-5
4.2.1.2 Reset Actions........................................................................................................... 4-5
4.2.2 Power-On Reset Flow.................................................................................................. 4-6
4.2.3 Hard Reset Flow .......................................................................................................... 4-8
4.2.4 Soft Reset Flow............................................................................................................4-9
4.3 Reset Configuration......................................................................................................... 4-9
4.3.1 Reset Configuration Signals ........................................................................................ 4-9
4.3.1.1 Reset Configuration Word Source ......................................................................... 4-10
4.3.1.2 SYS_CLK_IN Division......................................................................................... 4-11
4.3.1.3 Selecting Reset Configuration Input Signals......................................................... 4-11
4.3.2 Reset Configuration Words........................................................................................ 4-12
4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-13
4.3.2.1.1 System PLL Configuration................................................................................ 4-13
4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................4-14
4.3.2.2.1 PCI Host/Agent Configuration .......................................................................... 4-16
4.3.2.2.2 Boot Memory Space (BMS).............................................................................. 4-17
4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-17
4.3.2.2.4 Boot ROM Location.......................................................................................... 4-18

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4.3.2.2.5 eTSEC1 Mode ................................................................................................... 4-19
4.3.2.2.6 eTSEC2 Mode ................................................................................................... 4-20
4.3.2.2.7 e300 Core True Little-Endian............................................................................ 4-20
4.3.2.2.8 LALE Configuration.......................................................................................... 4-21
4.3.3 Loading the Reset Configuration Words ................................................................... 4-21
4.3.3.1 Loading from Local Bus........................................................................................ 4-21
4.3.3.1.1 Local Bus Controller Setting............................................................................. 4-22
4.3.3.2 Loading from I2C EEPROM................................................................................. 4-23
4.3.3.2.1 Using the Boot Sequencer Reset Configuration................................................4-23
4.3.3.2.2 EEPROM Calling Address................................................................................ 4-23
4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode...................................... 4-23
4.3.3.2.4 Reset Configuration Load Fail .......................................................................... 4-25
4.3.3.3 Default Reset Configuration Words....................................................................... 4-26
4.3.3.3.1 Examples for Hard-Coded Reset Configuration Words Usage .........................4-27
4.4 Clocking ........................................................................................................................4-28
4.4.1 Clocking in PCI Host Mode....................................................................................... 4-30
4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:2])...........................................................4-30
4.4.2 Clocking In PCI Agent Mode.................................................................................... 4-30
4.4.3 System Clock Domains.............................................................................................. 4-30
4.4.4 USB Clocking............................................................................................................ 4-31
4.4.5 Ethernet Clocking...................................................................................................... 4-32
4.4.6 Real-Time Clock (RTC)............................................................................................. 4-32
4.5 Memory Map/Register Definitions................................................................................ 4-32
4.5.1 Reset Configuration Register Descriptions................................................................ 4-32
4.5.1.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-33
4.5.1.2 Reset Configuration Word High Register (RCWHR)............................................4-33
4.5.1.3 Reset Status Register (RSR) .................................................................................. 4-33
4.5.1.4 Reset Mode Register (RMR) ................................................................................. 4-35
4.5.1.5 Reset Protection Register (RPR) ........................................................................... 4-35
4.5.1.6 Reset Control Register (RCR) ............................................................................... 4-36
4.5.1.7 Reset Control Enable Register (RCER)................................................................. 4-37
4.5.2 Clock Configuration Registers................................................................................... 4-37
4.5.2.1 System PLL Mode Register (SPMR) .................................................................... 4-37
4.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-39
4.5.2.3 System Clock Control Register (SCCR)................................................................ 4-40
Chapter 5
System Configuration
5.1 Introduction...................................................................................................................... 5-1
5.2 Local Memory Map Overview and Example .................................................................. 5-1

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Contents
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5.2.1 Address Translation and Mapping............................................................................... 5-3
5.2.2 Window into Configuration Space............................................................................... 5-4
5.2.3 Local Access Windows................................................................................................ 5-4
5.2.3.1 Local Access Register Memory Map ...................................................................... 5-4
5.2.4 Local Access Register Descriptions ............................................................................ 5-6
5.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-6
5.2.4.1.1 Updating IMMRBAR.......................................................................................... 5-6
5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)................................5-7
5.2.4.3 LBC Local Access Window nBase Address Registers
(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-8
5.2.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value.......................................................5-8
5.2.4.4 LBC Local Access Window nAttributes Registers (LBLAWAR0–
LBLAWAR3)....................................................................................................... 5-9
5.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value .................................... 5-9
5.2.4.5 PCI Local Access Window nBase Address Register
(PCILAWBAR0–PCILAWBAR1).................................................................... 5-10
5.2.4.5.1 PCILAWBAR0[BASE_ADDR] Reset Value....................................................5-10
5.2.4.6 PCI Local Access Window nAttributes Registers
(PCILAWAR0–PCILAWAR1) .......................................................................... 5-11
5.2.4.6.1 PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value................................ 5-11
5.2.4.7 DDR Local Access Window nBase Address Registers
(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-12
5.2.4.7.1 DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-12
5.2.4.8 DDR Local Access Window nAttributes Registers (DDRLAWAR0–
DDRLAWAR1).................................................................................................. 5-13
5.2.4.8.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................ 5-13
5.2.5 Precedence of Local Access Windows ...................................................................... 5-14
5.2.6 Configuring Local Access Windows ......................................................................... 5-14
5.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 5-14
5.2.8 Outbound Address Translation and Mapping Windows............................................ 5-15
5.2.9 Inbound Address Translation and Mapping Windows .............................................. 5-15
5.2.9.1 PCI Inbound Windows........................................................................................... 5-15
5.2.10 Internal Memory Map................................................................................................ 5-15
5.2.11 Accessing Internal Memory from External Masters.................................................. 5-16
5.3 System Configuration .................................................................................................... 5-16
5.3.1 System Configuration Register Memory Map........................................................... 5-16
5.3.2 System Configuration Registers ................................................................................ 5-17
5.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-17
5.3.2.2 System General Purpose Register High (SGPRH)................................................ 5-17
5.3.2.3 System Part and Revision ID Register (SPRIDR).................................................5-18
5.3.2.3.1 SPRIDR[PARTID] Coding................................................................................ 5-18

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5.3.2.4 System Priority and Configuration Register (SPCR) ............................................ 5-18
5.3.2.5 System I/O Configuration Register Low (SICRL)................................................5-20
5.3.2.6 System I/O Configuration Register High (SICRH)............................................... 5-23
5.3.2.7 Debug Configuration ............................................................................................. 5-26
5.3.2.7.1 DDR Debug Configuration................................................................................ 5-26
5.3.2.7.2 Local Bus Debug Configuration........................................................................ 5-27
5.3.2.8 DDR Control Driver Register (DDRCDR)............................................................ 5-27
5.3.2.9 DDR Debug Status Register (DDRDSR) .............................................................. 5-28
5.4 Software Watchdog Timer (WDT)................................................................................. 5-29
5.4.1 WDT Overview.......................................................................................................... 5-29
5.4.2 WDT Features............................................................................................................ 5-29
5.4.3 WDT Modes of Operation......................................................................................... 5-30
5.4.4 WDT Memory Map/Register Definition ................................................................... 5-30
5.4.4.1 System Watchdog Control Register (SWCRR).....................................................5-31
5.4.4.2 System Watchdog Count Register (SWCNR) .......................................................5-32
5.4.4.3 System Watchdog Service Register (SWSRR)......................................................5-32
5.4.5 Functional Description............................................................................................... 5-33
5.4.5.1 Software Watchdog Timer Unit............................................................................. 5-33
5.4.5.2 Modes of Operation............................................................................................... 5-34
5.4.6 Initialization/Application Information....................................................................... 5-35
5.4.6.1 WDT Programming Guidelines............................................................................. 5-35
5.5 Real Time Clock Module (RTC).................................................................................... 5-35
5.5.1 RTC Overview ........................................................................................................... 5-35
5.5.2 RTC Features ............................................................................................................. 5-36
5.5.3 RTC Modes of Operation........................................................................................... 5-36
5.5.4 RTC External Signal Description .............................................................................. 5-36
5.5.5 RTC Memory Map/Register Definition..................................................................... 5-37
5.5.5.1 Real Time Counter Control Register (RTCNR) .................................................... 5-37
5.5.5.2 Real Time Counter Load Register (RTLDR).........................................................5-38
5.5.5.3 Real Time Counter Prescale Register (RTPSR) .................................................... 5-39
5.5.5.4 Real Time Counter Register (RTCTR).................................................................. 5-39
5.5.5.5 Real Time Counter Event Register (RTEVR)........................................................ 5-40
5.5.5.6 Real Time Counter Alarm Register (RTALR).......................................................5-40
5.5.6 Functional Description............................................................................................... 5-41
5.5.6.1 Real Time Counter Unit......................................................................................... 5-41
5.5.6.2 RTC Operational Modes........................................................................................ 5-41
5.5.7 RTC Programming Guidelines................................................................................... 5-42
5.6 Periodic Interval Timer (PIT) ........................................................................................ 5-42
5.6.1 PIT Overview............................................................................................................. 5-42
5.6.2 PIT Features...............................................................................................................5-43
5.6.3 PIT Modes of Operation............................................................................................ 5-43

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5.6.4 PIT External Signal Description................................................................................ 5-43
5.6.5 PIT Memory Map/Register Definition ...................................................................... 5-44
5.6.5.1 Periodic Interval Timer Control Register (PTCNR)..............................................5-44
5.6.5.2 Periodic Interval Timer Load Register (PTLDR)..................................................5-45
5.6.5.3 Periodic Interval Timer Prescale Register (PTPSR).............................................. 5-46
5.6.5.4 Periodic Interval Timer Counter Register (PTCTR).............................................. 5-46
5.6.5.5 Periodic Interval Timer Event Register (PTEVR) ................................................. 5-46
5.6.6 Functional Description............................................................................................... 5-47
5.6.6.1 Periodic Interval Timer Unit.................................................................................. 5-47
5.6.6.2 PIT Operational Modes.......................................................................................... 5-48
5.6.7 PIT Programming Guidelines.................................................................................... 5-48
5.7 General-Purpose Timers (GTMs)................................................................................... 5-48
5.7.1 GTM Overview.......................................................................................................... 5-48
5.7.2 GTM Features ............................................................................................................5-49
5.7.3 GTM Modes of Operation.......................................................................................... 5-50
5.7.3.1 Cascaded Modes.................................................................................................... 5-50
5.7.3.2 Clock Source Modes.............................................................................................. 5-50
5.7.3.3 Reference Modes ................................................................................................... 5-50
5.7.3.4 Capture Modes....................................................................................................... 5-51
5.7.4 GTM External Signal Description ............................................................................. 5-51
5.7.5 GTM Memory Map/Register Definition.................................................................... 5-52
5.7.5.1 Global Timers Configuration Registers (GTCFRn)...............................................5-54
5.7.5.2 Global Timers Mode Registers (GTMDR1–GTMDR4)........................................ 5-57
5.7.5.3 Global Timers Reference Registers (GTRFR1–GTRFR4) .................................... 5-58
5.7.5.4 Global Timers Capture Registers (GTCPR1–GTCPR4)........................................ 5-58
5.7.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4) ...................................... 5-59
5.7.5.6 Global Timers Event Registers (GTEVR1–GTEVR4) .......................................... 5-59
5.7.5.7 Global Timers Prescale Registers (GTPSR1–GTPSR4) ........................................ 5-60
5.7.6 Functional Description............................................................................................... 5-61
5.7.6.1 General-Purpose Timer Units................................................................................ 5-61
5.7.6.2 Reference Modes ................................................................................................... 5-61
5.7.6.3 Capture Modes....................................................................................................... 5-61
5.7.6.4 Cascaded Modes.................................................................................................... 5-62
5.7.7 Initialization/Application Information....................................................................... 5-64
5.7.7.1 Programming Guidelines....................................................................................... 5-64
5.7.7.1.1 GTM Registers................................................................................................... 5-64
5.8 Power Management Control (PMC).............................................................................. 5-64
5.8.1 External Signal Description....................................................................................... 5-65
5.8.2 PMC Memory Map/Register Definition.................................................................... 5-65
5.8.2.1 Power Management Controller Configuration Register (PMCCR).......................5-66
5.8.2.2 Power Management Controller Event Register (PMCER)....................................5-67

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5.8.2.3 Power Management Controller Mask Register (PMCMR) ................................... 5-69
5.8.2.4 Power Management Controller Configuration Register 1 (PMCCR1)..................5-69
5.8.2.5 Power Management Controller Configuration Register 2 (PMCCR2)..................5-71
5.8.3 Functional Description............................................................................................... 5-72
5.8.3.1 Dynamic Power Management................................................................................ 5-72
5.8.3.2 Shutting Down Unused Blocks.............................................................................. 5-73
5.8.3.3 Software-Controlled Power-Down States.............................................................. 5-73
5.8.3.4 Software-Controlled Power Supply Switching...................................................... 5-73
5.8.3.5 Support of PCI Power Management Interface Specification.................................5-74
5.8.3.5.1 Entering Low Power States—Core-Only Mode................................................ 5-77
5.8.3.5.2 Entering Low Power States—Core and System Mode...................................... 5-77
5.8.3.6 Exiting Core and System Low Power States.........................................................5-78
5.8.3.6.1 Exiting Low Power States—Core-Only Mode.................................................. 5-78
5.8.3.6.2 Exiting Low Power States—Core and System Mode........................................ 5-78
5.8.3.7 MPC8313E-Specific PMC Low Power States ...................................................... 5-79
5.8.3.7.1 Power State Transitions from an ACPI Perspective..........................................5-79
5.8.3.7.2 MPC8313E Low Power Sequencing................................................................. 5-83
5.8.3.7.3 PMC External Power Supply Control ............................................................... 5-88
5.8.3.7.4 Low-Power Considerations ............................................................................... 5-90
5.8.4 Initialization/Application Information....................................................................... 5-91
5.8.4.1 Core Disable in Low Power Mode ........................................................................ 5-91
Chapter 6
Arbiter and Bus Monitor
6.1 Overview..........................................................................................................................6-1
6.1.1 Coherent System Bus Overview.................................................................................. 6-1
6.2 Arbiter Memory Map/Register Definition....................................................................... 6-2
6.2.1 Arbiter Configuration Register (ACR)........................................................................ 6-2
6.2.2 Arbiter Timers Register (ATR).................................................................................... 6-4
6.2.3 Arbiter Event Register (AER)...................................................................................... 6-5
6.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-6
6.2.5 Arbiter Mask Register (AMR)..................................................................................... 6-7
6.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 6-7
6.2.7 Arbiter Event Address Register (AEADR).................................................................. 6-9
6.2.8 Arbiter Event Response Register (AERR)................................................................. 6-10
6.3 Functional Description................................................................................................... 6-10
6.3.1 Arbitration Policy ...................................................................................................... 6-10
6.3.1.1 Address Bus Arbitration with PRIORITY[0:1]..................................................... 6-11
6.3.1.2 Address Bus Arbitration with REPEAT ................................................................ 6-12
6.3.1.3 Address Bus Arbitration after ARTRY.................................................................. 6-13

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6.3.1.4 Address Bus Parking.............................................................................................. 6-13
6.3.1.5 Data Bus Arbitration.............................................................................................. 6-13
6.3.2 Bus Error Detection ................................................................................................... 6-13
6.3.2.1 Address Time Out.................................................................................................. 6-13
6.3.2.2 Data Time Out ....................................................................................................... 6-14
6.3.2.3 Transfer Error ........................................................................................................ 6-14
6.3.2.4 Address Only Transaction Type............................................................................. 6-14
6.3.2.5 Reserved Transaction Type.................................................................................... 6-15
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type................................................................ 6-15
6.4 Initialization/Applications Information ......................................................................... 6-16
6.4.1 Initialization Sequence............................................................................................... 6-16
6.4.2 Error Handling Sequence........................................................................................... 6-16
Chapter 7
e300 Processor Core Overview
7.1 Overview..........................................................................................................................7-1
7.1.1 Features........................................................................................................................ 7-3
7.1.2 Instruction Unit............................................................................................................ 7-6
7.1.2.1 Instruction Queue and Dispatch Unit ...................................................................... 7-6
7.1.2.2 Branch Processing Unit (BPU)................................................................................ 7-7
7.1.3 Independent Execution Units....................................................................................... 7-7
7.1.3.1 Integer Unit (IU)...................................................................................................... 7-7
7.1.3.2 Floating-Point Unit (FPU)....................................................................................... 7-7
7.1.3.3 Load/Store Unit (LSU) ............................................................................................ 7-8
7.1.3.4 System Register Unit (SRU).................................................................................... 7-8
7.1.4 Completion Unit .......................................................................................................... 7-8
7.1.5 Memory Subsystem Support........................................................................................7-8
7.1.5.1 Memory Management Units (MMUs)..................................................................... 7-9
7.1.5.2 Cache Units............................................................................................................ 7-10
7.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-10
7.1.7 System Support Functions......................................................................................... 7-11
7.1.7.1 Power Management ............................................................................................... 7-11
7.1.7.2 Time Base/Decrementer ........................................................................................ 7-11
7.1.7.3 JTAG Test and Debug Interface............................................................................. 7-12
7.1.7.4 Clock Multiplier.................................................................................................... 7-12
7.1.7.5 Core Performance Monitor.................................................................................... 7-12
7.2 PowerPC Architecture Implementation......................................................................... 7-13
7.3 Implementation-Specific Information............................................................................ 7-13
7.3.1 Register Model........................................................................................................... 7-14
7.3.1.1 UISA Registers...................................................................................................... 7-16