Fujitsu MB15C02 User manual

1
FUJITSU MICROELECTRONICS
DATA SHEET DS04–21348–3Ea
Copyright©1999-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
1999.2
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C02
■DESCRIPTION
The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a
prescaler. A 64/65 division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C02 is suitable for mobile communications, such as paging systems.
■FEATURES
• High frequency operation: 220 MHz max @VDD = 1.0 V to 1.5 V
330 MHz max @VDD = 1.2 V to 1.5 V
450 MHz max @VDD = 1.3 V to 1.5 V
• Single power supply : VDD = 1.0 to 1.5 V
• Power saving function
• Pulse swallow function: 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to 60°C
■PACKAGES
16-pin, Plastic SSOP
(FPT-16P-M05)
20-pin, Plastic SSOP
(FPT-20P-M03)

2
MB15C02
■PIN ASSIGNMENTS
Top
1
2
3
4
5
6
16
15
14
13
12
11
7
8
10
9
View
VDD VSS
Data
LE
Clock
fin
OSCIN
OSCOUT
TEST
FC
LD
Do
φP
Vp
PS
NC
NC
17
18
19
20
φR
NC
NC
(FPT-20P-M03)
Top
1
2
3
4
5
6
16
15
14
13
12
11
7
8
10
9
View
VDD VSS
Data
LE
Clock
fin
OSCIN
OSCOUT
TEST
FC
LD
Do
φP
Vp
PS
φR
(FPT-16P-M05)
SSOP-16 pin
SSOP-20 pin

3
MB15C02
■PIN DESCRIPTIONS
(Continued)
Pin no. Pin
name I/O Descriptions
SSOP
16 SSOP 20
1 1 VDD –Power supply voltage
2 2 Clock IClock input for the shift register.(Schmitt trigger input)
Data is shifted into the shift register on the rising edge of the clock.
– 3 NC –No connection
3 4 Data ISerial data input using binary code.(Schmitt trigger input)
4 5 LE ILoad enable signal input (Schmitt trigger input)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
5 6 fin I Prescaler input.
A bias circuit and amplifier are at input port. Connection with an external
VCO should be done by AC coupling.
6 7 PS IPower saving mode control. This pin must be set at “L” at Power-ON. PS = “H” ; Normal mode
PS = “L” ; Power saving mode
– 8 NC –No connection
7 9 LD OLock detector signal output.
When a PLL is locking, LD outputs “H”.
When a PLL is not locking, LD outputs “L”.
810 Do O
Charge pump output.
Phase of the charge pump can be reversed by FC input. The Do output
may be inverted by FC input. The relationships between the programmable
reference divider output (fr) and the programmable divider output (fp) are
shown below;
fr > fp :“H” level (FC = “L”), “L” level (FC = “H”)
fr = fp : High impedance
fr < fp :“L” level (FC = “L”), “H” level (FC = “H”)
911 Vp –Power supply for the charge pump.
10 12 φR O
Phase comparator output pin (for external charge pump). Relation between
the programmable reference divider output (fr) and the programmable divider
output (fp) are shown below;
When FC = “L”
fr > fp : φR = “L” level, φP = “L” level
fr = fp : φR = “L” level, φP = High impedance
fr < fp : φR = “H” level, φP = High impedance
When FC = “H”
fr > fp : φR = “H” level, φP = High impedance
fr = fp : φR = “L” level, φP = High impedance
fr < fp : φR = “L” level, φP = “L” level
–13 NC –No connection
11 14 φP O Phase comparator output pin (for external charge pump). Refer to Pin
description for φR. φP pin is a Nch open drain output.
12 15 FC IPhase comparator input select pin.
13 16 TEST ITest mode select pin. (Pull down resistor)
Please set this pin to ground or open usually.

4
MB15C02
(Continued)
Pin no. Pin
name I/O Descriptions
SSOP
16 SSOP 20
14 17 OSCOUT OOscillator output.
Connection for an external crystal.
–18 NC –No connection
15 19 OSCIN IProgrammable reference divider input.
Oscillator input.
Clock can be input to OSCIN from outside. In the case, please leave OSCOUT
pin open and make connection with OSCIN as AC coupling.
16 20 VSS –Ground pin.

5
MB15C02
■BLOCK DIAGRAM
Control
register
Phase
comparator
OSCIN
OSCOUT
VP
Do
14-bit latch
Programmable
reference divider
Binary 14-bit
reference counter
Data 18-bit shift register
18-bit latch
Binary 6-bit
swallow
counter
Binary 12-bit
programma-
ble counter
LD
fin
Clock
LE
TEST
VSS
Prescaler Charge
pump
fp
fr
Intermittent
mode control
circuit
PS
FC
Control circuit
Lock detector
φP
φR
14
14
18
612
VDD
Output
control
circuit
Output
control
circuit
Crystal
oscillator
circuit

6
MB15C02
■ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Rating Unit Remark
Min. Max.
Power supply voltage VDD, VPGND–0.5 +2.0 V
Input voltage VIN GND–0.5 VDD +0.5 V
Output voltage VOUT GND–0.5 VDD +0.5 V
Output current IOUT –10 +10 mA
Storage temperature Tstg –40 +125 °C
Parameter Symbol Value Unit Remark
Min. Typ. Max.
Power supply voltage VDD, VP
1.0 – 1.5
V
For 220 MHz
VDD = VP1.2 – 1.5 For 330 MHz
1.3 – 1.5 For 450 MHz
Input voltage VIN GND – VDD V
Operating temperature Ta –20 – +60 °C

7
MB15C02
■ELECTRICAL CHARACTERISTICS (For 220 MHz :VDD = Vp = 1.0 to 1.5 V, Ta = –20 to +60°C)
(For 330 MHz :VDD = Vp = 1.2 to 1.5 V, Ta = –20 to +60°C)
(For 450 MHz :VDD = Vp = 1.3 to 1.5 V, Ta = –20 to +60°C)
*1: Conditions; Inputs except for fin, OSCIN and TEST are grounded, Outputs are opened.
Specifying the current flowing in VDD and Vp at operating state under conditions of VDD = Vp, fin =
220 MHz, or 330 MHz, and OSCIN = 12.8 MHz.
The current at locking state shows IDD Supply current (P.20).
*2: Conditions; PS = Low, Inputs except for fin, OSCIN and TEST are grounded, Outputs are opened.
*3: Condition; Ta = 25°C
*4: Condition; Ta = –20 to +60°C
Parameter Symbol Condition Value Unit
Min. Typ.*3 Max.*4
Power supply current Active Mode IDD *1 (VDD=1.0V/220MHz)
(VDD=1.2V/330MHz)
(VDD=1.3V/450MHz)
–
–
–
0.6
1.0
1.3
1.2
1.8
2.2 mA
Power saving current Power sav-
ing mode IDDS *2 (VDD=1.0V)
(VDD=1.2V)
(VDD=1.3V)
–
–
–
50
70
80
250
300
350 µA
Operating frequency fin fin Programmable divider
(VDD=1.0 to 1.5V)
(VDD=1.2 to 1.5V)
(VDD=1.3 to 1.5V)
10
10
10
–
–
–
220
330
450
MHz
OSCIN fOSC Programmable
reference divider 5–20MHz
Input sensitivity fin Vfin AC coupling –2.0 – – dBm
OSCin VOSC AC coupling –2.0 – – dBm
Input voltage Except for fin and
OSCin
H level VIH –VDD –
0.2 ––
V
L level VIL –––0.2
Input current Except for fin, OSCin
and TEST
H level IIH VIN=VDD ––+1.0
µA
L level IIL VIN=GND –1.0 – –
Output voltage
Except for
OSCOUT
and φP
H level VOH IOH = –0.2 mA VDD –
0.2 ––
V
L level VOL IOL = 0.2 mA – – 0.2
φPLlevelV
OL IOL = 0.2 mA – – 0.2 V
High impedance
cutoff current Do IOFF1 VOUT = GND to VP–100 – 100 nA
φPI
OFF2 VOUT = VDD ––100nA

8
MB15C02
■FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M ×N) + A] ×fOSC ÷R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095)
A : Preset divide ratio of binary 6-bit swallow counter (0 to 63)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M : Preset modulus of dual modulus prescaler (64)
2. Circuit Description
(1) Intermittent operation
The intermittent operation of the MB15C02 refers to the process of activating and deactivating its internal circuit
thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power
saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency
(fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may
causethephasecomparatortogenerateanexcessivelylargeerrorsignal,resultinginanout-of-synthlockfrequency
To preclude the occurrence of this problem, the MB15C02 has an intermittent mode control circuit which forces the
frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and resultant
lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting pin PS high
providesthenormaloperationmodeandsettingthepinlowprovidesthepowersavingmode.TheMB15C02behavior
in the active and power saving modes is summarized below.
Active mode (PS = “H”)
All MB15C02 circuits are active and provide the normal operation.
Power saving mode (PS = “L”)
TheMB15C02stopsanycircuitsthatconsumepowerheavilyaswellascauselittleinconveniencewhendeactivated
and enters the low-power dissipation state. Do,φR, φP, and LD pins take the same state as when the PLL is locked.
Do pin becomes a high-impedance state and the input voltage to the voltage control oscillator (VCO) is maintained
at the same level as in active mode(that is, locked state) according to a time constant of a low pass filter (LPF).
Consequently , the output frequency from the VCO (fvco) is maintained at approximately the lock frequency.
Applying the intermittent operation by alternating the active and power saving modes, and also forcing the phases
of fr and fp to synchronize when it switches from stand by to active modes, the MB15C02 can keep the power
dissipation of its entire circuitry to the minimum.
(2) Programmable divider
The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as
fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter,
and a controller which controls the divide ratio of the prescaler

9
MB15C02
Divide ratio range:
Prescaler : M = 64, M+1=65
Swallow counter : A = 0 to 63
Programmable counter : N = 5 to 4095
The MB15C02 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable
counters must satisfy the relationship N>A.
The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio = (M + 1) ×A + M ×(N – A) = M ×N + A = 64 ×N + A
When N is set within 5<N<63, the possible divide ratio A of the swallow counter can take values 0<A<N-1 because
N must be greater than A. For example, 0<A<19 is allowed when N=20 but 20<A<63 is not allowed in that case.
Consequently, N>64 must be satisfied for the total divider to be set within 0<A<63.
The fp and fin have the following relation:
fp = fin / (64 ×N + A)
(3) Programmable reference divider
The programmable reference divider divides the reference oscillation frequency(fosc) from the crystal oscillator
connected between OSCin and OSCout pins or from the external oscillator input taken in directly through OSCin,
pin and then, sends the resultant fr to the phase comparator. It consists of a 14-bit binary programmable reference
counter. When the output from the external oscillator is to be input directly to OSCin, pin the connection must be
AC coupled and OSCout pin is left open. Also, to prevent OSCout from malfunctioning, its traces on the printed
circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form of load.
The following divider is used:
Programmable reference counter : R = 5 to 16383
The fr and fosc have the following relation:
fr = fosc / R
(4) Phase comparator
The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates
an error signal that is proportional to phase difference. The outputs from the phase comparator include 1) Do which
takes on one of the three states, namely, “L” (low), “H” (high), and “Z” (high impedance), and is sent to the LPF,
2)φR, 3)φP, 4)LD which indicates the PLL lock or unlock states.
(a) Phase comparator
The phase comparator detects the phase error between fr and fp, then generates an error signal that is
proportional to the phase error. The roles of the fr and fp supplied to the phase comparator may be reversed
by switching the logical input level of pin FC. This inverts the logical level of the Do output. The logical level of
Dooutputmay beselectedaccordingtothecharacteristicsoftheexternalLPFandtheVCO.(RefertoTable1.)
Table. 1 Phase comparator inputs/output relationships
FC = “L” FC = “H”
Do φRφPDoφRφP
fr > fp H L L L H Z
fr = fp Z L Z Z L Z
fr < fp L H Z H L L
Output
Phase
relation

10
MB15C02
(b) Charge pump
The charge pump is available in two forms: internal external.
Internal charge pump output (Do)
External charge pump outputs (φR, φP)
(c) Phase comparator input/output waveforms
The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr
and fp. Note that φP is an Nch open drain output. The pulse width ofthe phase comparatoroutputs are identical
and equal to the phase error between fr and fp as shown in Figure 1.
Figure 1. Phase comparator input/output waveform
fp
fr
When FC = “L”
When FC = “H”
Do
Do
High Z
High Z
φR
φP
φR
φP
High Z
High Z
High Z: High impedance state
fp : Nch open output

11
MB15C02
(d) Lock detector
The lock detector detects the lock and unlock states of the PLL. The lock detector outputs “H” when the PLL
enters the lock state and outputs “L” when the PLL enters the unlock state as shown in Figure 2. When PS =
“L”, the lock detector outputs “H” compulsorily.
Figure 2. Phase comparator input/output waveforms (Lock detector)
fr
fp
LD

12
MB15C02
4. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of a control bit and divide ratio
setting data. The control bit selects the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits(6 bits for the swallow counter and 12 bits for the
programmable counter) and 1 control bit as shown in Figure 3.1. In case of the programmable reference divider,
the serial data consists of 14 divider bits and 1 control bit as shown in Figure 3.2.
The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data
for the programmable reference divider.
CA
0A 1A 2A 3A 4A 5N 0N 1N 2N 3N 4N 5N 6N 7N 8N 9N
10 N 11
Direction of data input
Figure 3. Serial data format
CR
0R 1R 2R 3R 4R 5R 6R 7R 8R 9R
10 R 11 R 12 R 13
Direction of data input
Figure 3.1. Divide ratio for the programmable divider
Figure 3.2. Divide ratio for the programmable reference divider
LSB MSB
Swallow counter Programmable counter
control bit
LSB MSB
control bit
Programmable reference counter

13
MB15C02
(2) The flow of serial data
Serialdataisreceivedviadatapininsynchronizationwiththeclockinputandloadedintoshiftregisterwhichcontains
the divide ratio setting data and into the control register which contains the control bit. The logical product (through
the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the
latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is enabled and the
divide ratio data from the shift register is loaded into the selected counter (s).
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table 2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table2.2
represent the divide ratio of programmable counter.
Table. 2 Divide ratio for the programmable divider
Table.2.1 Swallow counter divider A Table2.2 Programmable counter divider N
Note: Less than 5 is prohibited.
Divide
ratio
(A) A
0A 1A 2A 3A 4A 5Divide
ratio
(N) N
0N 1N 2N 3N 4N 5N 6N 7N 8N 9N 10 N 11
0 0 0 0 0 0 0 5 101000000000
1 1 0 0 0 0 0 6 011000000000
⋅ ⋅⋅⋅⋅⋅⋅ ⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
63 1 1 1 1 1 1 4095 111111111111
Figure 4. The flow of serial data
14-bit binary programmable reference counter
Programmable
referencedivider
14-bit latch
18-bit shift register
18-bit latch
AND
C*
AND
Data
Clock
LE
Prescaler 6-bit binary swallow counter 12-bitbinary programmable
counter Programmable
divider
* : Control register
612
18
14
14

14
MB15C02
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set
to 1. Table.3 Divide ratio for the programmable reference divider
(5) Setting data input timing
The MB15C02 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data
bits are effective.
To set the divide ratio for the MB15C02 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1(>1 µs): Data setup time t2(>1 µs): Data hold time t3(> µs): Clock pulse width
t4(>1 µs): LE setup time to the rising edge of last clock t5(>1 µs): LE pulse width
Divide
ratio
(R) R
0R 1R 2R 3R 4R 5R 6R 7R 8R 9R 10 R 11 R 12 R 13
5 10100000000000
6 01100000000000
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
16383 11111111111111
Data
Clock
LE
t1 t4t5
t3
t2
Figure 5. Serial data input timing

15
MB15C02
Since the divide rations are unpredictable when the MB15C02 is turned on, it is necessary to initialize the divide
ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers
(e.g., programmable reference divider), set LE to “H” level before setting the divide ratio for the other dividers (e.g.,
programmable divider). To change the divide ratio of one of the divider after initialization, input the serial data only
for that divider (the divide ratio for the other divider is preserved).
Figure 6. Inputting serial data(Setting divisors)
Data
Clock
LE
Serial data for program-
mable reference divider 1* 0*
Serial data for program-
mable divider
15 clocks 19 clocks
* : Control bit

16
MB15C02
■TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
2. OSCIN Input Sensitivity
Input sensitivity (dBm)
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
−60.0 0 100 200 300 400 500 600 700 800 900 1000
fin input frequency vs. Input sensitivity
fin input frequency (MHz)
Ta = +25°C
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.3 V
VDD = 1.5 V
Input sensitivity (dBm)
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
−60.0 0 50 100 150 200 250 300 350 400 450 500
OSCIN input frequency vs. Input sensitivity
OSCIN input frequency (MHz)
Ta = +25°C
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.3 V
VDD = 1.5 V

17
MB15C02
3. fin Power Supply Voltage
4. OSCIN Power Supply Voltage
Input frequency (MHz)
(MHz)
1000
900
800
700
600
500
400
300
200
100
00.9 1.0 1.1 1.2 1.3 1.4 1.6 1.7 1.8
Power supply voltage vs. fin input frequency
Power supply voltage (V)
Ta = +25°C
Vfin = −2.0 (dBm)
1.5
Input frequency (MHz)
500
450
400
350
300
250
200
150
100
50
00.9 1.0 1.1 1.2 1.3 1.4 1.6 1.7 1.8
Power supply voltage vs. OSCIN input frequency
Power supply voltage (V)
Ta = +25°C
Vfin = −2.0 (dBm)
1.5

18
MB15C02
5. IDD Power Supply Current
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
IDD (mA)
Input frequency vs. power supply current
Ta = +25°C
0 100 200 300 400 500 600 700 800 900 1000
Input frequency (MHz)
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.3 V
VDD = 1.5 V

19
MB15C02
6. Do (Charge Pump) Power Supply Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.00.8 0.9 1.0 1.1 1.2 1.3 1.5 1.6 1.7 1.8
VDD (Vp) vs. IOL
(at VOL = 0.2 V)
VDD (V)
Ta = +25°C
1.4
IOL (mA)
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.00.8 0.9 1.0 1.1 1.2 1.3 1.5 1.6 1.7 1.8
VDD (Vp) vs. IOH
(at VOH = VDD – 0.2 V)
VDD (V)
Ta = +25°C
1.4
IOH (mA)

20
MB15C02
7. Spectrum Wave Form
ATTEN 10 dB
RL 0 dBm UAUG 16 10dB/ ∆MKR −85.50 dB 25.0 kHz
CENTER 286.0000 MHz
*RBW 1.0 kHz VBW 1.0 kHz SPAN 200.0 kHz *SWP 1.00 s
D
S
∆MKR
25.0 kHz
−85.50 dB
• LOCK Frequency : 286.0 MHz
(fr = 25 kHz)
• VDD = 1.2 V, Vp = 1.2 V
Ta = +25°C
ATTEN 10 dB
RL 0 dBm UAUG 50 10dB/ ∆MKR −53.84 dB 800 Hz
CENTER 286.00000 MHz
*RBW 100 Hz VBW 100 kHz SPAN 20.00 kHz *SWP 3.00 s
D
S
∆MKR
800 Hz
−53.84 dB
• LOCK Frequency : 286.0 MHz
( fr = 25 kHz)
• VDD = 1.2 V, Vp = 1.2 V
Ta = +25°C
DO VT (to VCO)
6800 pF 68000 pF 4700 pF
15 kΩ
4.3 kΩ
* VCO : KV = 6 MHz/v
• Test circuit