Fujitsu MB86R02 User manual

MB86R02 ‘Jade-D’ Hardware Manual V1.64
MB86R02 ‘Jade-D’
Graphics Controller
Hardware Manual
Fujitsu Semiconductor Europe GmbH
Release 1.64 (amended)
(17.09.2013 13:11)
This document is subject to changes
and corrections without prior warning

MB86R02 ‘Jade-D’ Hardware Manual V1.64
Preface
Intention and Target Audience of this Document
This document describes and gives you detailed insight to the stated Fujitsu semiconductor product.
The MB86R02 ‘Jade-D’ device is the successor of Fujitsu’s MB86R01 ‘Jade’ and contains both
improvements and many new features.
This target audience of this document is engineers developing products which will use the MB86R02
‘Jade-D’ device. It describes the function and operation of the device. Please read this document
carefully.
Trademarks
APIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671
Munich, Germany.
ARM is a registered trademark of ARM Limited in UK, USA and Taiwan.
ARM is a trademark of ARM Limited in Japan and Korea.
ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.
ARM Powered logo is a trademark of ARM Limited in Korea.
ARM926EJ-S and ETM9 are trademarks of ARM Limited.
System names and the product names which appear in this document are the trademarks of the
respective company or organization.
Licenses
Under the conditions of Philips corporation I2C patent, the license is valid where the device is used in
an I2C system which conforms to the I2C standard specification by Philips Corporation.
The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.

MB86R02 ‘Jade-D’ Hardware Manual V1.64
The contents of this document are subject to change without notice. Customers are advised to
consult with FUJITSU sales representatives before ordering.
Any information in this document, including functional descriptions and schematic diagrams, shall not
be construed as license of the use or the exercising of any intellectual property rights, such as patent
rights or copyright or any other right of FUJITSU or any third party or does FUJITSU warrant non-
infringement of any third-party's intellectual property right or other right by using such information.
FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of
third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured for general use,
including unrestricted ordinary industrial use, general office use, personal use, and household use but
are not designed, developed and manufactured for use accompanying fatal risks or dangers that,
unless extremely high safety levels are ensured, could have a serious effect to the public and could
lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction
control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon systems), or (2) for use requiring extremely high
reliability (i.e., submarine or satellite technology). Please note that FUJITSU will not be liable against
you and/or any third party for any claims or damages arising in connection with above-mentioned
uses of the products.
If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by the Japanese government will be required for export of those products from Japan.
All rights reserved and Copyright © FUJITSU SEMICONDUCTOR EUROPE 2010

MB86R02 ‘Jade-D’ Hardware Manual V1.64
Document Change History
Version
Date
Editor
Comment
V1.64 (amended)
17.09.2013
RvReitzenstein
Table ‘Pin Functional Description’ rectified.
Amended row are marked with a change bar on the right side.
Amended entries are marked bold.
V1.64
30.01.2013
von Treuberg
Extended section 17.2.1.3 '
Jade-D Restrictions'.
Removed reference to Application note on APIX jitter (no
longer applies). Added hint on using Demand Mode for
DMA/UART transfers.
V1.63
30.01.2012
von Treuberg
Changed RSDS electrical characteristics.
V1.62
07.11.2011
von Treuberg
Changed Channel Mapping table (26.6).
V1.61 21.09.2011 von Treuberg Corrected pin names in chapters 1, 7, 17:
APIX_n_SB > APIXn_SB_
APIX_SB0 > APIX0_SB
APIX_SB1 > APIX1_SB
APIX_SB5-0 > APIX0_SB
APIX1_SB5-0 > APIX1_SB
Modified section 5.1.13 (Only ES2 > Not available in ES1)
Extended Driving capability 2: list in 34.4.1, 3.3V Standard
CMOS I/O.
RLD: Changed statement 'little endian' to 'big endian'.
Removed 'Uplink' in description of CH0CFG/CH1CFG bits 6:3.
The swing setting has an effect regardless of RX/TX usage.
Corrected GPIO listings (number of GPIOs effected) with
concern to CMPX_MODE_10 descriptions in mulitplex
overview and register description.
Added an additional note concerning multiplex mode #3 if the
pins are unused (check the table for multiplex mode #3).
Corrected 9.6.1: address of instruction vector table to
0000_0080H.
Corrected IRQ connections diagram in chapter 9. IRQ5 is
connected to IRC2.
Added information about unused case for TRACEDATA_X
pins in pinmultiplex mode #3.
Replaced MediaLB Signal Timings chapter.
V1.60
29.10.2010
von Treuberg
Added new section in Electrical Characteristics: 'Transmitter
Serial Data Signal Characteristics'
V1.50
25.03.2010
von Treuberg
SSCG: Modified modulation peak values (e.g. 3% > 2x 1.56%),
added SSCG settings table for recommended value of 20 kHz.
CRG: Modified table 5-1 Clock Overview List
Electrical Characteristics: Added important requirement for
APIX PLL stability (power-on procedure)
EXTBUS: 11.6.1 corrected typo in description for NOR flash
page access mode.
CNT: Corrected reset values of register CAXI_PS and
CMUX_MD.
EXTBUS: modified diagram in section 11.8 (Word write access
to 16 bit width SRAM/NOR Flash)
I2S: corrected FIFO size from previously documented 18/36

MB86R02 ‘Jade-D’ Hardware Manual V1.64
Words, to the implemented size of 66/132 Words.
CCNT: Modified CCID register fields.
Electrical Characteristics: changes:
(1) Table 34-1 Maximum Ratings
(2) Table 34-3 3.3V Standard CMOS I/O Recommended
Operating Conditions, added driving capabilities.
(3) New section: APIX Characteristics
(4) Added RSDS characteristics
GDC: 18.6.3.3 Direct Color (24 bits/pixel) – corrected RGBA
table (A field is only 1 bit)
GDC: Extended all LxEC descriptions for RGBA (e.g. L1EC,
L2EC etc.)
RLD: byte alignment information added to StrideCfg1 register.
Limitations information added to AHBMTransferWidth Setup
section.
V1.40
19.10.2009
von Treuberg
Overview: Unused pins - changed handling of OSC_FILTER,
changed handling of XTRST pin.
GPIO: re-inserted block diagram (mistakenly removed)
IRC: removed IRQs as only required for debugging
DMAC: Corrected line to MPX_MODE_1[1:0] = "HL" in section
'Related Pins'. Corrected DMA configuration A register
(DMACAx), BC[3:0] and TC[15:0] function descriptions.
RLD: added more detail to DestAddress register description
Electrical characteristics, almost all tables modified
CRG: corrected initial value of CRAM register.
TCON: exchanged Figure 22-4 Block diagram of TSIG.
SSCG: updated register description
UART: changed table 28-2:
(external input condition: CLK = 25.0MHz, CRIPM[3:0] = 0001)
Addendum (differences ES1/ES2): added note about APIX TX
initialization
V1.30
24.07.2009
von Treuberg
CCNT: Corrected typo in description of register CAXI_PS
ADDENDUM: Added note about JTAGSEL polarity
DMAC: changed hex value in second diagram of section
'15.8.1 DMA start in Single channel'
GPIO: corrected base address in table 24-1
DDR2: several small corrections concerning DRIMRx and
OCD adjustment
CCNT: Added note that only 32 bit access to DDR is poss.
when in big endian mode. Extended description of multiplex
mode/function selection register CMUX_MD. Corrected ChipID
register displayed values.
Overview + Addendum: modified MUX tables for better
understanding. Added cell types to pin overview.
Memory map: changed RHlite to APIX, added SSCG area.
Modified Register Access description.
I2C: added 'Example of a slave address transmission'
GPIO: new block diagram and note about configuration of
differential pair configuration in MUX mode 4, function 4
SIG: added limitation for cyclic monitoring mode.
SSCG: added base address to register description.

MB86R02 ‘Jade-D’ Hardware Manual V1.64
CRG: modified description of DPERI register
V1.20
22.06.2009
von Treuberg
CCNT: Page 9-12: corrected typo ADC7 > ADC2
GDC: VCCR register – changed reset value. Corrected table of
DCKD clock delay values and DCM3 description.
APIX: Changed names OscMode, OscBias, OscFilter to
OSC_MODE, OSC_BIAS and OSC_FILTER for consistancy. -
Added upstream channel bandwith limitation
IRC: Added info to IRQ7,8,19,20 ... 23: Unused, corresponding
correction to IRQ table (9.6)
EXTBUS: changed footnote of MCFMODE0/2/4
TCON: Removed superflous section concerning Indigo.
Exchanged block diagram of TSIG (22-4). Modified diagram
'Basic structure of a sync mixer (22-7).
DDR2: corrected flowchart and tables 13-4, 13-6, corrected
13.6.2.2 flow chart and added new explanation text. Added
limitation about read/write when in self-refresh mode.
Corrected 13.7.2.2 OCD Adjustment Procedure, changed
bitfield ODTBIAS in register DROABA.
SSCG: numerous small corrections. Removed references to
1.6 GHz operation (not for Jade-D implementation)
Addendum: added difference in SSCG functional scope
ES1/ES2
DMAC/I2S: added restriction for I2S transfer modes
SIG: Added new example control flow diagram to 21.6.1
Added new chapter 'Electrical Characteristics'
V1.10
18.05.2009
von Treuberg
Overview: corrected bus connection information, added
improved overview of multiplex pin groups, corrected I2S unit
count, added section concerning PU/PD differences ES1/ES2,
updated pin listings/unused pins info
SPI: Added second channel
GDC: corrected display timing table values, added 1280 x 480
GDC: correcrected address offsets of L2WY, L2WW, L2WH
GDC: Modified DCM3 register
GDC: Added DCM1.LCS register description
GDC: Corrected RSDS bitfield initial value (DCM0 register)
CCNT: Renamed register CDEBUG0 > CBSC
CCNT: Renamed register CDEBUG1 > CDCRC
CCNT: Added new register CMSR2
CCNT: Corrected numbers of CMBUS register bitfields
CRG: Minimal register description changes
ADC: Corrected ADC channel mapping table, updated register
description
Added Addendum for differences ES1/ES2
IRC: Added missing registers for IRC2 to overview, corrected
TBR addresses in tables
CLUT: updated diagrams
DITH: updated diagrams
SIG: updated diagrams
TCON: updated diagrams
RLD: updated diagrams
V1.00
12.03.2009
von Treuberg
Overview: Unused pins: changed handling of I2S_ECLK, VPD,

MB86R02 ‘Jade-D’ Hardware Manual V1.64
TDI, added information about internal pull-up/down resistors
for numerous pins, corrected number of IRC channels to 3.
GDC: corrected blending registers description
IRC: Removed IRC overview diagram (covered by tables)
Pin multiplex tables, changes to CMPX_MODE_2[1:0] and
CMPX_MODE_3[1:0] and CMPX_MODE_2[1:0].
V0.05
18.12.2008
von Treuberg
Updated pins lists, package layouts
GDC: initial values of DCM3 register changed
ADC: completely new register description
SSCG: extended and updated register description
PWM: corrected all offset addresses of registers
TCON: updated register description
RBC: added limitation when using VINITHI/REMAP
IRC: replaced TBDs with latest information
DDR2: made changes to 'SDRAM initialization procedure' and
'ODT Setting Procedure'
CCNT: corrected typo in register CIST, added new register
information to CMBUS.
APIX: added application note for PCB designers
V0.04
17.10.2008
von Treuberg
General changes: English improvements
Overview: Added unused pins list
Memory Map (updated figure)
CRG (Table 5-3 timings updated, register descriptions updated
for CRPR, CRHR, CRHB, CSEL, new registers CRDP0.
CRPD1 added)
CCNT (register MBUS2AXU added, changed registers CIST,
CEX_PIN_ST, CMSR1, CMSR2)
APIX (complete register update)
PWM (register update)
V0.03
12.08.2008
von Treuberg
Major changes:
Preface: new block diagram
Overview (preliminary pinning information, multiplexing)
System Configuration (example configuration)
Memory Map (updated figure)
CRG (corrected 42.5 MHz > 41.625 MHz, MLB has 2 clocks,
SELXCLK changed, SSCG register start changed, Hint for
disabling non-active module clocks, predivider reminder
added, added predivider PLL info)
IRC (added IRC2 for 16 new interrupts)
DMAC (added DMA trigger from RH DREQ Rx + Tx)
CCNT (removed USB set and related registers, added soft
reset registers/bitfields, removed IDE related registers,
removed I2S endian bits)
HOSTIFC (content added)
APIX (added content and register description)
PWM (updated register description)
I2S (updated register description)
ADC (extended for 4 channels)
I2C (updated register description)
TCON (Added flow control, revised feature list, added clock
position pin mapping tables, added software reset description,

MB86R02 ‘Jade-D’ Hardware Manual V1.64
app note for RSDS channel order inversion, AC TTL spec
change to 42 MHz)
V0.02 25.05.2007 von Treuberg Reorganization, new chapters, major alterations of
content
V0.01
08.03.2007
von Treuberg
First version

MB86R02 ‘Jade-D’ Hardware Manual V1.64
Table of Contents
1Overview .......................................................................................................................................1-1
1.1 Features .............................................................................................................................1-1
1.2 Block Diagram....................................................................................................................1-3
1.2.1 Outline of each functional block......................................................................................1-4
Function Summary of the Blocks......................................................................................................1-6
1.3 Package Dimensions..........................................................................................................1-9
1.4 Pinning..............................................................................................................................1-10
1.5 Pin Assignment.................................................................................................................1-10
1.5.1 Pin Assignment Table...................................................................................................1-12
1.5.2 Pin Multiplexing.............................................................................................................1-22
1.6 Pin Functional Description................................................................................................1-31
2System Configuration....................................................................................................................2-1
2.1 Typical Application .............................................................................................................2-1
3Memory Map .................................................................................................................................3-1
3.1 Memory Map of LSI............................................................................................................3-1
3.2 Register Access..................................................................................................................3-4
4CPU (ARM926EJ-S core) .............................................................................................................4-1
4.1 Outline of ARM926EJ-S core.............................................................................................4-1
4.2 Features of ARM926EJ-S core ..........................................................................................4-1
4.3 Block diagram of ARM926EJ-S core..................................................................................4-1
4.4 Configuration of ARM926EJ-S and ETM ...........................................................................4-2
5Clock Reset Generator (CRG) ......................................................................................................5-1
5.1 Outline ................................................................................................................................5-1
5.2 Features .............................................................................................................................5-1
5.3 Overview.............................................................................................................................5-2
5.4 Location in the device.........................................................................................................5-3
5.5 Operation............................................................................................................................5-3
5.5.1 Reset Generation............................................................................................................5-3
5.5.2 Clock Generation............................................................................................................5-7
5.6 Registers ..........................................................................................................................5-16
5.1.1. Register list...................................................................................................................5-16
5.1.2. PLL control register (CRPR).........................................................................................5-18
5.1.3. Watchdog timer control register (CRWR).....................................................................5-21
5.1.4. Reset/Standby control register (CRSR)........................................................................5-23
5.1.5. Clock divider control register A (CRDA) .......................................................................5-25
5.1.6. Clock divider control register B (CRDB) .......................................................................5-27
5.1.7. AHB (A) bus clock gate control register (CRHA)..........................................................5-28
5.1.8. APB (A) bus clock gate control register (CRPA) ..........................................................5-29
5.1.9. Reserved control register (CRPB)................................................................................5-30
5.1.10. AHB (B) bus clock gate control register (CRHB) ......................................................5-31
5.1.11. ARM core clock gate control register (CRAM)..........................................................5-32
5.1.12. DPERI clock gate control register (CRDP0, CRDP1) ...............................................5-32
5.1.13. Clock Selector control register (CSEL) .....................................................................5-33
6Spread Spectrum Clock Generator (SSCG) .................................................................................6-1
6.1 Position of Block in whole LSI............................................................................................6-1
6.2 Features .............................................................................................................................6-1
6.2.1 Functional .......................................................................................................................6-1
6.2.2 Limitations.......................................................................................................................6-1

MB86R02 ‘Jade-D’ Hardware Manual V1.64
6.3 Software Interface ..............................................................................................................6-3
6.3.1 Format of Register Description.......................................................................................6-3
6.3.2 Global Address ...............................................................................................................6-4
6.3.3 Register Summary..........................................................................................................6-4
Register Description..........................................................................................................................6-4
6.4 Processing Mode................................................................................................................6-8
6.4.1 Parameter setting for 666MHz PLL clock.......................................................................6-8
6.4.1.1 Parameter setting for SSCG-speed of 15KHz.........................................................6-8
6.4.1.2 Parameter setting for SSCG-speed of 20KHz.........................................................6-9
6.4.1.3 Parameter setting for SSCG-speed of 35KHz.......................................................6-10
6.4.1.4 Parameter setting for SSCG-speed of 50KHz.......................................................6-10
6.5 Control Flow .....................................................................................................................6-11
6.5.1 Operation ......................................................................................................................6-11
7CCNT (Chip Control).....................................................................................................................7-1
7.1 Overview.............................................................................................................................7-1
7.2 Features .............................................................................................................................7-2
7.3 Supply clock .......................................................................................................................7-2
7.4 Registers ............................................................................................................................7-3
7.4.1 Register list.....................................................................................................................7-3
7.4.2 CHIP ID register (CCID) .................................................................................................7-5
7.4.3 Soft reset register (CSRST)............................................................................................7-6
7.4.4 Interrupt status register (CIST).......................................................................................7-7
7.4.5 Interrupt status mask register (CISTM) ..........................................................................7-9
7.4.6 GPIO interrupt status register (CGPIO_IST)................................................................7-11
7.4.7 GPIO interrupt status mask register (CGPIO_ISTM)....................................................7-11
7.4.8 GPIO interrupt polarity setting register (CGPIO_IP).....................................................7-13
7.4.9 GPIO interrupt mode setting register (CGPIO_IM).......................................................7-13
7.4.10 AXI bus wait cycle set register (CAXI_BW)..................................................................7-15
7.4.11 AXI priority setting register (CAXI_PS).........................................................................7-17
7.4.12 Multiplex mode setting register (CMUX_MD) ...............................................................7-19
7.4.13 External pin status register (CEX_PIN_ST)..................................................................7-21
7.4.14 MediaLB set register (CMLB) .......................................................................................7-22
7.4.15 MBUS2AXU set register (CMBUS)...............................................................................7-24
7.4.16 Mode switch register like endian etc. (CBSC) ..............................................................7-25
7.4.17 DDR2 Interface reset control register (CDCRC)...........................................................7-27
7.4.18 Soft reset register 0 for macro (CMSR0)......................................................................7-28
7.4.19 Soft reset register 1 for macro (CMSR1)......................................................................7-30
7.4.20 Soft reset register 2 for macro (CMSR2)......................................................................7-33
8Remap Boot Controller (RBC).......................................................................................................8-1
8.1 Outline ................................................................................................................................8-1
8.2 Features .............................................................................................................................8-1
8.3 Block Diagram....................................................................................................................8-1
8.4 Supply clock .......................................................................................................................8-2
8.5 Register ..............................................................................................................................8-2
8.5.1 Register list.....................................................................................................................8-2
8.5.2 Remap control register (RBREMAP)..............................................................................8-4
8.5.3 VINITHI control register A (RBVIHA)..............................................................................8-5
8.5.4 INITRAM control register A (RBITRA)............................................................................8-6
8.6 Operation............................................................................................................................8-7
8.6.1 RBC reset .......................................................................................................................8-7
8.6.2 Remap control.................................................................................................................8-7
8.6.3 VINITHI control ...............................................................................................................8-7