Future Technology UMFT60 Series User manual

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.:FT_001191 Clearance No.: FTDI#457
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its
documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or
implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of u se or
failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical
appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This
document provides preliminary information that may be subject to change without notice. No freedom to use patents or other
intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2
Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640
Copyright © Future Technology Devices International Limited
Future
Technology
Devices
International Ltd
UMFT60x
(FIFO TO USB 3.0
Bridge Evaluation
Board)
The UMFT60xx is an evaluation/development
module with either FMC(LPC)/HSMC connectors
for interfacing FTDI’s FT60x USB 3.0 Superspeed
IC with external hardware. The UMFT60xx allows
for bridging a FIFO bus to a USB3.0 host and
evaluating the functionality of the FT60x.
As a daughter card, the UMFT60xx must work
with a FIFO master board which has either a FMC
or HSMC connector. There are 4 models which
provide different FIFO bus interfaces and data bit
widths.
The modules are designed such that they can
plug into most FPGA development platforms
supplied by vendors such as Xilinx or Altera.
Refer to Ordering Information for module
options.
The UMFT60xx supports 2 parallel slave FIFO bus
protocols (Multi-Channel FIFO / 245 Synchronous
FIFO) with a data “burst” rate of up to 400MB/s.
For a full list of the FT60x’s features refer to the
FT60x datasheet.
The UMFT60xx module has the following features:
Supports USB 3.0 Super Speed (5Gbps)/USB
2.0 High Speed (480Mbps)/USB 2.0 Full Speed
(12Mbps) transfer
4 IN channels and 4 OUT channels on FIFO bus
connectivity
Supports multi voltage I/O: 1.8V, 2.5V and 3.3V
High speed connector for FIFO bus : FMC(Field
Programmable Mezzanine Card) or HSMC (High
Speed Mezzanine Card)
FMC connector is compatible with most Xilinx
FPGA reference design boards
HSMC is compatible with most Altera FPGA
reference design boards
Multi powered options: external DC powered,
BUS powered, FMC/HSMC powered
Hardware Reset and Remote Wake Up
Micro-USB3.0 receptacle

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 1
1Ordering Information
Part No.
Description
UMFT600A-B
16 Bit FIFO bus, HSMC connector with B version chip
UMFT601A-B
32 Bit FIFO bus, HSMC connector with B version chip
UMFT600X-B
16 Bit FIFO bus, FMC (Low Pin Count)connector with B version chip
UMFT601X-B
32 Bit FIFO bus, FMC(Low Pin Count) connector with B version chip
Table 1.1 UMFT60xx Ordering Information

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 2
Table of Contents
1Ordering Information ................................................ 1
2Hardware Description................................................ 3
2.1 Physical Description ............................................................5
2.1.1 Dimensions ........................................................................................ 5
2.2 Connectors, Jumpers and Push Buttons ..............................7
2.2.1 CN1 - Micro USB3.0 Receptacle ............................................................ 7
2.2.2 CN2 –POWER JACK 2.1MM .................................................................. 7
2.2.3 JP1 –External/VBUS Powered Selection................................................. 7
2.2.4 JP2 –VCC33 Selection......................................................................... 8
2.2.5 JP3, JP6–VCCIO Selection ................................................................... 8
2.2.6 JP4, JP5 –FIFO mode selection and GPIO pin out .................................... 8
2.2.7 SW1, SW2 –Push Buttons for Reset and Remote Wake Up ...................... 8
2.2.8 CN4 –FMC / HSMC FIFO bus interface connector .................................... 9
3Board Schematics .................................................... 13
4Hardware Setup Guide............................................. 18
4.1 Power Configuration..........................................................18
4.2 Jumpers Default Position ..................................................18
4.3 Power Consumption ..........................................................19
5Contact Information ................................................ 20
Appendix A –References ............................................. 21
Document References ...............................................................21
Acronyms and Abbreviations.....................................................21
Appendix B –List of Tables & Figures .......................... 22
List of Tables.............................................................................22
List of Figures ...........................................................................22
Appendix C –Revision History ..................................... 23

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 3
2Hardware Description
Figure 2-1 UMFT600A Module Top and Bottom View
Figure 2-2 UMFT601A Module Top and Bottom View
Figure 2-3 UMFT600X Module Top and Bottom View

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 4
Figure 2-4 UMFT601X Module Top and Bottom View
The main functions of the UMFT60xx module are as follows:
Provides Multi-channel FIFO mode and 245 Synchronous FIFO mode Protocols, configured
by GPIOs.
Configurable FIFO clock: 66.67MHz and 100MHz (100MHz only for 2.5V or 3.3V VCCIO),
default clock is 100MHz.
High speed FIFO bus interface: FMC (Low Pin Count) and HSMC optional. See Ordering
Information.
Jumpers selection allowing powered options: VBUS-powered, External DC-powered, FIFO
master board-powered.
Multi voltage VCCIO option:1.8V, 2.5V, 3.3V.
Configurable GPIOs.
Hardware reset and remote wake up support.
Available with 16bit and 32bit wide FIFO bus.

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 5
11.2
11.2
1.6
1.6
4.5
11.2
1.6
71.12
3.81
5.715
60.0
50.485
3.78
78.7
2.1 Physical Description
The UMFT600A/UMFT601A and UMFT600X/UMFT601X modules dimensions are illustrated in Figure
2.5 to Figure 2.8.
2.1.1 Dimensions
Figure 2-5 UMFT600A/UMFT601A Dimensions (Top view)
Figure 2-6 UMFT600A/UMFT601A Dimensions (Side view)
±0.10mm Tolerance
All dimensions are in mm

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 6
63.56
60.0
70.0
11.33
3.515
11.2
1.6
6.3
Figure 2-7 UMFT600X/UMFT601X Dimensions (Top view)
Figure 2-8 UMFT600X/UMFT601X Dimensions (Side view)
±0.10mm Tolerance
All dimensions are in mm

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 7
2.2 Connectors, Jumpers and Push Buttons
Connectors, jumpers and push buttons are described in the following sections.
2.2.1 CN1 - Micro USB3.0 Receptacle
Pin No.
Name
Type
Description
1
VBUS
P
5V DC power supply
2
D-
IO
USB D- line
3
D+
IO
USB D+ line
4
ID
IO
OTG identification(N.C.)
5
GND
P
Ground
6
SSTX-
O
Super Speed USB transmitter differential pair (-)
7
SSTX+
O
Super Speed USB transmitter differential pair(+)
8
GND
P
Ground
9
SSRX-
I
Super Speed USB receiver differential pair (-)
10
SSRX+
I
Super Speed USB receiver differential pair (+)
Table 2.1 CN1 - Micro USB3.0 Pin-out
2.2.2 CN2 –POWER JACK 2.1MM
Optional external DC 5V input.
Pin No.
Name
Type
Description
1
5V
P
5V power supply
2
GND
P
Ground
3
GND
P
Ground
Table 2.2 CN2 –POWER JACK 2.1MM
2.2.3 JP1 –External/VBUS Powered Selection
Select whether the module power is supplied by an external DC 5V or VBUS. Note this setting
must be chosen in conjunction with the JP2 setting. Default is open. [Note]
Jumper position
Description
Short pin 1-2
Select VBUS Power
Short pin 2-3
Select external DV 5V
Table 2.3 JP1 –5V input Options

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 8
2.2.4 JP2 –VCC33 Selection
Select whether the module main power is supplied by DC5V or the FIFO master board DC3.3V.[Note]
Jumper position
Description
Short pin 1-2
Select powered by external DV5V or VBUS
Short pin 2-3
Select powered by FIFO master Board(default)
Table 2.4 JP3 –VCC33 Option
2.2.5 JP3, JP6–VCCIO Selection
Select the IO voltage level. [Note]
Jumper position
Description
JP3
JP6
Short pin 1-2
Open
VCCIO=2.5V(default)
Short pin 2-3
Open
VCCIO=1.8V
Open
Short
VCCIO=3.3V
Table 2.5 JP3 –VCCIO Option
2.2.6 JP4, JP5 –FIFO mode selection and GPIO pin out
Select Multi-channel FIFO mode or 245 Synchronous FIFO mode.
JP4 pin2 is GPIO_0 pin out and JP5 pin2 is GPIO_1 pin out.
Jumper position
FIFO Mode
Channel
No.
GPIO valid
JP4
JP5
GPIO_0
(JP4 pin2)
GPIO_1
(JP5 pin2)
1-2(or open)
1-2(or open)
Multi-Channel FIFO
4
Yes
Yes
1-2(or open)
2-3
Multi-Channel FIFO
2
Yes
No
2-3
1-2(or open)
Multi-Channel FIFO
1
No
Yes
2-3
2-3
245 Synchronous FIFO
1
No
No
Table 2.6 JP4, JP5 –Configurations
Note: Please refer to section 4 Hardware setup guide for more details power configuration options
and jumpers positions.
2.2.7 SW1, SW2 –Push Buttons for Reset and Remote Wake Up
SW1 –Reset, module hardware reset, mapped to FMC/HSMC connector, can be used for FIFO
master reset. Drive low when press down.

UMFT60x FIFO TO USB 3.0 Bridge Evaluation Board
Version 1.1
Document Reference No.: FT_001191 Clearance No.: FTDI#457
Copyright © Future Technology Devices International Limited 9
SW2 –Remote Wake Up, drive low when press down.
2.2.8 CN4 –FMC / HSMC FIFO bus interface connector
2.2.8.1 FMC connector configurations-UMFT600X/UMFT601X Module
FMC Pin#/Name
UMFT600X
U1: FT600 Pin#/Name
UMFT601X
U1: FT601 Pin#/Name
C14/LA10_P
11 /Wake up_N (Optional, default: OPEN)
16 /Wake up_N (Optional, default: OPEN)
C15/LA10_N
10 /RESET_N
15 /RESET_N
C18/LA14_P
12 /GPIO_0(Optional, default: OPEN)
17 /GPIO_0(Optional, default: OPEN)
C19/LA14_N
13 /GPIO_1(Optional, default: OPEN)
18 /GPIO_1(Optional, default: OPEN)
C22/LA18_P_CC
43 /D_CLK (FIFO bus clock,FT600 output)
68 /D_CLK (FIFO bus clock,FT601 output)
C26/LA27_P
N.C.
62 /DATA18
C27_LA27_N
N.C.
60 /DATA16
D14/LA09_P
N.C.
8 /BE_N_3
D15/LA09_N
N.C.
7 /BE_N_2
D20/LA17_P_CC
N.C.
76 /DATA31
D21/LA17_N_CC
N.C.
75 /DATA30
D23/LA23_P
N.C.
70 /DATA25
D24/LA23_N
N.C.
69 /DATA24
D26/LA26_P
N.C.
63 /DATA19
D27/LA26_N
N.C.
61 /DATA17
G6/LA00_P_CC
N.C.
13 /OE_N
G7/LA00_N_CC
N.C.
12 /RD_N
G12/LA08_P
N.C.
11 /WR_N
G13/LA08_N
N.C.
10 /SIWU_N
G21/LA20_P
9 /OE_N
74 /DATA29
G22/LA20_N
8 /RD_N
73 /DATA28
G24/LA22_P
7 /WR_N
67 /DATA23
G25/_LA22_N
6 /SIWU_N
65 /DATA21
G27/LA25_P
56 /DATA15
57 /DATA15
G28/LA25_N
54 /DATA13
55 /DATA13