GÄN GS66508B-EVBDB1 User manual

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 1
Please refer to the Evaluation Board/Kit Important Notice on page 30
GS66508B-EVBDB1
GaN E-HEMT Daughter Board and GS665MB-EVB
Evaluation Platform
User’s Guide
Visit www.gansystems.com for the latest version of this user’s guide.
DANGER!
This evaluation kit is designed for engineering evaluation in a controlled
lab environment and should be handled by qualified personnel ONLY.
High voltage will be exposed on the board during the test and even brief
contact during operation may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized,
always wait until all capacitors are discharged before touching the board.
CAUTION
This product contains parts that are susceptible to damage by electrostatic
discharge (ESD). Always follow ESD prevention procedures when
handling the product.

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 2
Please refer to the Evaluation Board/Kit Important Notice on page 30
Overview
The GS66508B-EVBDB1 daughter board style evaluation kit consists of two GaN Systems 650V GaN
Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers,
isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows
users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the
universal mother board (P/N: GS665MB-EVB) or for quick prototyping of a users’ own system design.
Features
•Serves as a reference design and evaluation tool as well as deployment-ready solution for easy in-
system evaluation.
•Vertical mount style with height of 35mm, which fits in majority of 1U design and allows
evaluation of GaN E-HEMT in traditional through-hole type power supply board.
•Current shunt position for switching characterization testing
•Universal form factor and footprint for all products
The daughter board and universal mother board ordering part numbers are below:
Table 1 Ordering part numbers
Part Number GaN E-HEMT
P/N:
Description
GS66508B-EVBDB1 GS66508B GaN E-HEMT bottom side cooled 650V/30A, 50mΩ
Analog Devices isolated driver ADUM4121ARZ
GS665MB-EVB
Universal 650V Mother Board
Control and Power I/Os
The daughter board GS6650B8-EVBDB1 circuit diagram is shown in Figure 1. The control logic inputs on
2x3 pin header J1 are listed below:
Table 2 Control pins
Pin
Descriptipon
ENA
Enable input. It is internally pulled up to VCC, a low logic disables all the PWM gate
drive outputs.
VCC +5V auxillary power supply input for logic circuit and gate driver. On the daughter
board there are 2 isolated 5V to 9V DC/DC power supplies for top and bottom switches.
VDRV
Optional 9V gate drive power input. This pin allows users to supply separate gate drive
power supply. By default VDRV is connected to VCC on the daughter board via a 0 ohm
jumper FB1. If bootstrap mode is used for high side gate drive, connect VDRV to 9V
PWMH
High side PWM logic input for top switch Q1. It is compatible wth 3.3V and 5V
PWML
Low side PWM logic input for bottom switch Q2. It is compatible wth 3.3V and 5V
0V
Logic inputs and gate drive power supply ground return.

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 3
Please refer to the Evaluation Board/Kit Important Notice on page 30
Power pins
The 3 power pins are
•VDC+: Input DC Bus voltage
•VSW: Switching node output
•VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-.
Figure 1 - GS66508B-EVBDB1 Evaluation Board Block Diagram
GS66508B-EVBDB1 half bridge daughter board
Figure 2- GS66508B-EVBDB top side

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 4
Please refer to the Evaluation Board/Kit Important Notice on page 30
Figure 3- GS66508B-EVBDB bottom side
A. 2x GaN Systems 650V E-HEMT GS66508B, 30A/50mΩ
B. Decoupling capacitors C4-C11
C. 2 x Analog Devices ADuM4121ARZ Isolated gate driver
D. Optional current shunt position JP1.
E. Test points for bottom Q2 VGS.
F. Recommended probing positions for Q2 VDS.
G. Optional bootstrap circuit D1/R1 (unpopulated).
H. 5V-9V isolated DC/DC gate drive power supply
GaN E-HEMTs
This daughter board includes two GaN Systems GS66508B (650V/30A, 50mΩ) E-HEMTs in a GaNPX®
bottom cooled package. The large S pad serves as the Source connection and thermal pad. Pin 4 is the
Kelvin source connection for the gate drive return.
Figure 4- Package outline of GS66508B

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 5
Please refer to the Evaluation Board/Kit Important Notice on page 30
Gate driver circuit
•The half bridge evalualtion boards use two Analog Devices high voltage, isolated gate drivers
(ADuM4121ARZ) to drive the GaN transistors directly. The ADuM4121ARZ gate driver is used
to isolate and drive the GaN transistor, operating at high DC bus voltage. It has a rail-to-rail
output with maximum output current of 2A to turn the GaN device on and off efficiently and
reliably. An external 20Ω gate resistor is used to limit the current for sourcing and sinking.
•The ADuM4121ARZ has a propagation delay of less than 53 ns and typical rise and fall times of
approximately 18 ns. The very high Common-mode transient immunity (CMTI) of 150 kV/us
(min) isolates high transient noise during the high frequency operation and prevents erroneous
outputs.
•The GaN E-HEMT switching speed and slew rate can be directly controlled by the gate resistors.
By default the turn-on/turn-off gate resistors, R6/R12, are 20Ω. The user can adjust the values of
gate resistors to fine tune the turn-on and turn-off speed.
•FB2/FB3 are footprints for optional ferrite bead. By default they are populated with 0Ω jumpers.
If gate oscillation is observed, it is recommended to replace them with ferrite bead with Z=10-
20Ω@100MHz.
Figure 5- Gate driver circuit
Gate drive power supply
•5V-9V isolated DC/DC converters are used for the gate drive. The 9V output is regulated down to
6V for the gate driver.
•By default gate drive supply input VDRV is tied to VCC +5V via 0Ω jumper (FB1). Remove FB1 if
separate gate drive input voltage is to be used.
Bootstrap mode
•The board has the option for users to experiment with non-isolated bootstrap circuit with
following circuit changes:

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 6
Please refer to the Evaluation Board/Kit Important Notice on page 30
oRemove PS2 and short circuit pin 2 to 5 and pin 1 to 4.
oPopulate D1/ R1 (not supplied): D1 is the high voltage bootstrap diode (for example ES1J)
and use 1-2Ω 0805 SMD resistor on R1. Depopulate PS1, LED1 and replace C2 with 1uF
capacitor.
oRemove 0Ω jumper at FB1 and supply +9V at VDRV.
Figure 6 - Gate drive power supply with optional bootstrap mode
Current shunt JP1
•The board provides an optional current shunt position JP1 between the source of Q2 and power
ground return. This allows drain current measurement for switching characterization test such as
Eon/Eoff measurement.
•The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt
(recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω)
•If current shunt is not used JP1 must be shorted. JP1 affects the power loop inductance and its
inductance should be kept as low as possible. Use a copper foil or jumper with low inductance.
CAUTION
Check the JP1 before the first time use. To complete the circuit JP1 needs to
be either shorted or a current shunt must be inserted before powering up.

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 7
Please refer to the Evaluation Board/Kit Important Notice on page 30
Figure 7 - Current shunt position JP1
Measurement with current shunt
1. When measuring VSW with current shunt, ensure all channel probe grounds and current shunt
BNC output case are all referenced to the source end of Q2 before the current shunt. The
recommended setup of probes is shown as below.
2. The output of coaxial current shunt can be connected to oscilloscope via 50Ωtermination
impedance to reduce the ringing.
3. The measured current is inverted and can be scaled by using: Id=Vid/Rsense.
Figure 8- Recommended probe connection with current shunt
VGL
VSL
VSW
BNC case
To oscilloscope
probe input (use
50Ω termination)
BNC tip
V
DS
V
GS
I
D

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 8
Please refer to the Evaluation Board/Kit Important Notice on page 30
Thermal design
1. GS66508B has a thermal pad at the bottom side for heat dissipation. The heat is transferred to the
bottom side of PCB using thermal vias and copper plane.
2. A heatsink (35x35mm size) can be attached to the bottom side of board for optimum cooling.
Thermal Interface Material (TIM) is needed to provide electrical insulation and conformance to
the PCB surface. The daughter board evaluation kit includes a sample 35x35mm fin heatsink (not
installed), although other heatsinks can also be used to fit users’ system design.
3. A thermal tape type TIM (Berguist®Bond-Ply 100) is chosen for its easy assembly. The supplied
heatsink has the thermal tape pre-applied so simply peel off the protective film and attach the
heatsink to the back of board as marked in Figure 3.
4. Two optional mounting holes as shown in Figure 9 are provided for mounting customized
heatsink using screws.
5. Using the supplied heatsink and TIM, the overall junction to ambient thermal resistance RthJ-A is
~9°C/W with 500LFM airflow.
6. Forced air cooling is recommended for power testing.
Figure 9 The daughter board with heatsink attached
CAUTION:
There is no on-board over-temperature protection. Device temperature must be closely monitored
during the test. Never operate the board with device temperature exceeding TJ_MAX (150°C)

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 9
Please refer to the Evaluation Board/Kit Important Notice on page 30
Using GS66508B-EVBDB1 with universal mother board GS665MB-
EVB
Figure 10 - 650V universal mother board GS665MB-EVB
GaN Systems offers a universal 650V mother board (ordering part number: GS665MB-EVB, sold
separately) that can be used as the basic evaluation platform for all the daughter boards.
The universal 650V mother board evaluation kit includes following items:
1. Mother board GS665MB-EVB
2. 12VDC Fan
12V input
The board can be powered by 9-12V on J1. On-board voltage regulator creates to 5V for daughter board
and control logic circuits. J3 is used for external 12VDC fan.
12V INPUT
(+)
5V Power Supply
CIN
VSW
PWM control & dead
time circuit
Daughter Board
Probing point for VSW
For Ext.
12VDC Fan
Airflow direction
Optional Cout
VDC- VOUT
VDC-
VDC+

GS66508B-EVBDB1
650V GaN E-HEMT Evaluation Board User’s Guide
___________________________________________________________________________________________________________________
GS66508B-EVBDB1 UG rev. 190605 © 2019 GaN Systems Inc. www.gansystems.com 10
Please refer to the Evaluation Board/Kit Important Notice on page 30
PWM control circuit
Figure 11 - PWM control input and dead time circuit
Figure 12 - On board dead time generatrion circuit
The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users
can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted,
controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’ own control
board).
An on-board dead time generation circuit is included on the mother board. Dead time is controlled by
two RC delay circuits, R6/C12 and R5/C11. The default dead time is set to about 100ns. Additionally two
potentiometers locations are provided (TR1/TR2, not included) to allow fine adjustment of the dead time
if needed.
0V
D1 PMEG2005EB
SOD523
R6
1K00
TR12K C11
100pF
0V
R5
1K00
C10
1uF
C9
0.1uF
+5V
J7
112538 1
2
3 4 5
R4
100R
R1206
R2
100R
R1206
U2A
74VHC132
3
1
2
147
0V
R1
49R9
0V
D2 PMEG2005EB
SOD523
TR22K
C12
100pF
0V
U2B
74VHC132
4
5
6
U2C
74VHC132
9
10
8
U2D
74VHC132
12
13
11
TP7
TP8
DNP
DNP
PWM
OUTPUT
INVERTED
PWM OUTPUT
R3
49R9
DNP
DNP
R7
49R9