HiTech Global HTG-ZRF8 User manual

HTG-ZRF8 Platform User Manual
www.HiTechGlobal.com
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HiTech Global ZYNQ UltraScale+™ RFSoC Development Platform
HTG-ZRF8 User Manual
Version 1.0 August 2018
Copyright © HiTech Global 2004-2018

HTG-ZRF8 Platform User Manual
www.HiTechGlobal.com
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Disclaimer
HiTech Global does not assume any liability arising out of the application or use of any product described or
shown herein; nor does it convey any license under its patents, copyrights, or mask work rights or any rights of
others. HiTech Global reserves the right to make changes, at any time, in order to improve reliability and
functionality of this product. HiTech Global will not assume responsibility for the use of any circuitry described
herein other than circuitry entirely embodied in its products. HiTech Global provides any design, code, or
information shown or described herein "as is." By providing the design, code, or information as one possible
implementation of a feature, application, or standard, HiTech Global makes no representation that such
implementation is free from any claims of infringement. End users are responsible for obtaining any rights they
may require for their implementation. HiTech Global expressly disclaims any warranty whatsoever with respect
to the adequacy of any such implementation, including but not limited to any warranties or representations that
the implementation is free from claims of infringement, as well as any implied warranties of merchantability or
fitness for a particular purpose.
HiTech Global will not assume any liability for the accuracy or correctness of any engineering or software
support or assistance provided to a user. HiTech Global products are not intended for use in life support
appliances, devices, or systems. Use of a HiTech Global product in such applications without the written
consent of the appropriate HiTech Global officer is prohibited.
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Revision History
Date
Version
Notes
8/15/2017
1.0

HTG-ZRF8 Platform User Manual
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Table Of Contents
1.0) Overview
5
2.0) Features
6
3.0) Banks Assignment, Block Diagram, & Clocks
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4.0) Main Clocks
11
5.0) PCI Express
14
6.0) DDR 4 Memory
17
7.0) FPGA Mezzanine Card (FMC+)
24
8.0) ADC / DAC Ports
30
9.0) USB To UART Bridges
32
10.0) ARM Trace Port
33
11.0) SDIO Interface
34
12.0)10/100/1000 Ethernet
35
13.0) Display Port
36
14.0) USB2.0/3/0
36
15.0) SATA
37
16.0) 1-PPS
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17.0) LEDs, XDAC, User I/O Headers & Pushbutton
38
18.0) IP Protection
39
19.0) I2C Bus Switch
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20.0) Configuration
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Tables & Figures
Table (1) FPGA Features
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Table (2): Main Clocks
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Table (3): Summary of the Si5341 (U46) Clock Outputs
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Table (4): PCI Express FPGA Pin Assignments
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Table (5): PCI Express Clock Circuit
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Table (6): DDR4 FPGA Pin Assignment (SODIMM-PL Side)
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Table (7) DDR4 FPGA Pin Assignment (Components-PS Side)
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Table (8): Vita57.4 FMC+ Pin Assignment
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Table (9): FPGA Mezzanine Connector (FMC+) Pin Assignment
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Table (10): RFB Resistor Table vs Various Output Voltages
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Table (11): ADC Interface Pin Assignment
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Table (12): DAC Interface Pin Assignment
31
Table (13): USB To UART FPGA Pin Assignment
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Table (14): Trace/Debug Port’s FPGA Pin Assignment
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HTG-ZRF8 Platform User Manual
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Table (15): SDIO Port’s FPGA Pin Assignment
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Table (16): Ethernet Port’s FPGA Pin Assignment
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Table (17): Display Port’s FPGA Pin Assignment
36
Table (18): USB Port’s FPGA Pin Assignment
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Table (19): SATA Port’s FPGA Pin Assignment
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Table (20): 1-PPS Port’s FPGA Pin Assignment
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Table (21): User Interface FPGA Pin Assignment
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Figure (1): FPGA Bank Assignment
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Figure (2): System Block Diagram
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Figure (3): Clock Block Diagram
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Figure (4): Mechanical Drawing
10
Figure (5): Si5341 Block Diagram
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Figure (6): LMX2482 Block Diagram
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Figure (7): PCI Express Clock Circuit
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Figure (8): PCI Express Clock Enable Circuit
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Figure (9): HSPC (Vita57.4) Carrier Card Connector Grid Labeling
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Figure (10): FMC+/FMC VADJ Configurations
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Figure (11): ADC/DAC Clock Diagram
32
Figure (12): I2C Bus Switch
40
Figure (13): Configuration Option
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HTG-ZRF8 Platform User Manual
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◙1.0) Overview
Populated with one Xilinx ZYNQ UltraScale+ RFSoC ZU25DR, ZU27DR, or ZU28DR, the HTG-ZRF8
provides access to large FPGA gate densities, multiple ADC/DAC ports, expandable I/Os ports and DDR4
memory for variety of different programmable applications.
The HTG-ZRF8 is supported by eight 12-bit ADC (4GSPS) and eight 14-bit DAC (6.4GSPS) ports. The ADC
and DAC ports are supported through high-performance front panel micro Rf connectors.
The HTG-ZRF8 architecture allows easy and versatile functional expansion through one Vita 57.4 compliant
(FMC+) port. The HTG-ZRF8 can host wide range of Vita57.1 /Vita57.4 compliant daughter cards.
The HTG-ZRF8 is supported by one 72-bit ECC DDR4 SODIMM socket providing access to up to 16 GB of
SDRAM memory. The processor’s side is supported by up to 2GB of DDR4 memory.
The HTG-ZRF8 can be used in PCI Express and Standalone mode and powered through its 6-pin Molex PCIe
connector.
Table (1) illustrates key features of the supported FPGAs by the HTG-ZRF8 platform.
Table (1): Summary of supported ZYNQ RFSoc UltraScale+ FPGA Features