Holtek BC45B4523 User manual

Rev. 1.20 1 October 28, 2020 Rev. 1.00 PB October 28, 2020
BC45B4523
13.56MHz Multi-Standard NFC Reader
Features
• Operating Voltage:
♦Receiver A_VDD: 2.7V~3.6V
♦Transmitter T_VDD: 2.7V~5.5V
♦Digital I/O IO_VDD: 2.7V~5.5V
• Operating Temperature: -40°C~85°C
• Power Saving Modes:
♦Hard Power Down: 0.5μA
♦Soft Power Down: 4.7μA
♦Standby: 1.0mA
♦Support Card Detection mode:
10.4μA @ wakeup period=500ms
• Up to 10Mbps SPI interface speed
• 64-byte send and receive FIFO-buer
• 64-byte addressing user-congurable registers
• Interrupt pin IRQ
• Programmable timer
• Low jitter on-chip oscillator buer
• Ultra Low Power On-Chip 3.3V Regulator
• Low Power Card Detection
• External RF Field Detection
• Supported Protocols:
♦ISO14443A/B, all bit rates
– 106, 212, 424 and 848kbps
♦ISO15693, all modes
– Downlink: 1 of 4 and 1 of 256
– Uplink: 6.6/13/26/53kbps with 1 sub-carrier
– Uplink: 6.6/13/26kbps with 2 sub-carrier
– Package: 24-pin QFN
Transmitter
• Modulation index adjustable by software
• Output current up to 250mA @ T_VDD=5.0V
• Output impedance 3Ω @ T_VDD=5.0V
• Arbitrary modulation by external signal
• Wide operating voltage for TX from 2.7V to 5.5V
• On-chip framing coder for supported standards
Receiver
• RX sensitivity down to 2mVp
• On-chip Framing decoder for supported standards
• Automatic Gain Control (AGC)
Applications
• Secure access control/door locks
• Toys
• Handheld NFC readers
• Contactless payment system
Abbreviation
AGC: Automatic gain control
CRC: Cyclic redundancy check
DPLL: Digital Phase locked Loop
EGT: Extra guard time in ISO14443B
EOF: End of Frame
ETU: Elementary Time Unit
fc: Carrier frequency
FIFO: First In, First Out Memory
SOF: Start of Frame
UID: Unique Identier
RF: Radio Frequency
General Description
The BC45B4523 is a single-chip reader ASIC for
13.56MHz NFC/contactless standard protocols,
which provides the best solution for near field
wireless communication applications such as access
control locks, label readers, payment machines.
The device supports and compatibles with all major
global secured baseband ISO standards including
ISO14443 Type A, Type B, Crypto_M cards and
Smart label ISO15693. The device provides a high-
speed SPI controller/host interface with an integrated
64-byte FIFO for smooth data transfer. Furthermore,
the embedded codec is capable of handling all bit-
level coding/decoding, encrypting/decrypting as well
as frame-level manipulation for transmission and
reception. The device is well suited for mobile devices
due to its low power consumption and low operating
voltage from 2.7V to 3.6V. The ultra-low power on-
chip 3.3V regulator is provided to stabilize the device
power, and simultaneously supply power of up to
150mA to the external companion microcontroller.
The BC45B4523 receiver circuit has integrated a full
AGC loop allowing a wide dynamic range of RF input
signal levels. The excellent sensitivity performance of
the device enables detection of the input signals with

Rev. 1.20 2 October 28, 2020
BC45B4523
amplitudes as low as 1mVpp without distorting the data
integrity. The receiver lters can be selected optionally
either to a predefined band in accordance with the
generic required standard setup, or to an arbitrarily
dened combination which gives exibility to cope with
various antenna variations/parameters. The baseband
circuits permit the inbound/outbound configuration to
accept various forms of customized protocols, incoming
to the chip and outgoing to the external RF circuitry in
the application specic-design system.
The transmitter is capable of accepting a wide range of
operating supply voltages to serve various applications,
e.g., 5V for base stations or desktop readers, and 3.3V
for handheld devices. The transmission controller
is entirely used to support all operation status and
requests, including FIFO status full/high/low and
transmission complete flag. The transmitter drivers
support a wide range of power supply voltages from
2.7V to 5.5V. A high drive current up to 250mA is
guaranteed for demanding item-level mid-range reader
designs. The dual high-powered transmitters can be
flexibly configured in various configurations, e.g.
dierential driving, single-ended driving and a mode
to drive an external Class-E amplifier for improving
the drive strength in the gate antenna setup.
The BC45B4523 contains efficient power saving
modes: Hard Power Down, Soft Power Down,
Standby and low-power Card Detection modes. The
low-power Card Detection mode allows the device
to not operate at full power continuously. The device
periodically detects external card. If an external card
is detected, interrupt signal will be sent to MCU to
wake up the system.
To facilitate operation of the companion microcontroller,
the BC45B4523 is fully equipped with on-chip
peripheral support devices such as an RF-trig timer,
a host interrupt generator and a clock divider. The
BC45B4523 is oered in a QFN package with excellent
heat dissipation when self-mounted on PCB.
Block Diagram
Bit Level CODEC
Encryption
Engine
Frame CODEC
State Machine /
Wake Up Controller /
Flow Control
CRC
Generator
WkUp
Timer Program Timer
Power Mode
Control
Interface
Control ( SPI )
Registers
IRQ Controller
POR MISO
MOSI
NCS
SCLK
IRQ
RSTPD
TD
DIG
I/O
FIFO
Transmitter
TX1
TX2
T_VSS
T_VDD
Data
Evaluator
AmpENV
RF
Amplitude
Detector
Voltage
Reference
IO_VDD
D_VDDVREG_OUTVREG_INXTAL1 XTAL2
Regulator
1V6
Regulator
3V3
RX
VMID
TA CLK13M
A_VDD A_VSS
Receiver Digital
D_VSS
Low Freq.
OSC
CLK16k
Functional Block Diagram

Rev. 1.20 3 October 28, 2020
BC45B4523
Pin Assignment
BC45B4523
24 QFN-A
1
2
3
4
5
6
7 8 9 10 11 12
13
14
15
16
17
18
192021222324
RX
TA
MISO
MOSI
SCK
NCS
VREG_IN
T_VSS
TX2
T_VDD
TX1
T_VSS
VREG_OUT
A_VDD
A_VSS
XTAL1 XTAL2
VMID
TD IRQ RSTPD D_VDD D_VSS IO_VDD
Pin Description
Pin No. Pin Name Type Description
1 RX Analog Input Receiver input
2TA Analog Output Analog Test pin
3 MISO Digital Output SPI: Master In Slave Out
4 MOSI Digital Input SPI: Master Out Slave In
5 SCK Digital Input SPI: Clock input
6 NCS Digital Input SPI: Chip Select (Active Low)
7 IO_VDD Power Digital I/O power supply
8 D_VSS Power Digital and digital I/O ground
9 D_VDD Power Digital core power supply (need an external 100nF decoupling
capacitor)
10 RSTPD Digital Input Master Reset (Active High)
11 IRQ Digital Output Interrupt Request output
12 TD Digital I/O Digital Test pin
13 T_VSS Power Transmitter ground
14 TX1 Output Transmitter output # 1
15 T_VDD Power Transmitter power supply
16 TX2 Output Transmitter output # 2
17 T_VSS Power Transmitter ground
18 VREG_IN Power On-chip Regulator input (5.0V)
19 VREG_OUT Power On-chip Regulator output (3.3V)
20 A_VDD Power Analog power supply (3.3V)
21 A_VSS Power Analog ground
22 XTAL1 Analog Input Crystal oscillator input
23 XTAL2 Analog Output Crystal oscillator output
24 VMID Analog Output Mid rail reference voltage

Rev. 1.20 4 October 28, 2020
BC45B4523
Electrical Characteristics
Absolute Maximum Rating
Stresses exceeding those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Exposure to the absolute maximum rating conditions for an extended period of time may affect the device
reliability. Only one absolute maximum rating can be applied at a time.
Parameter Rating
Analog Supply Voltage (A_VDD to A_VSS) -0.5V to 3.6V
Digital I/O Supply Voltage (IO_VDD to D_VSS) -0.5V to 5.5V
Transmitter Supply Voltage (T_VDD to T_VSS) -0.5V to 5.5V
Digital Core Output Supply Voltage (D_VDD to D_VSS) -0.5V to 2.4V
Analog Input Voltage) -0.5V to A_VDD+0.3V
Analog output Voltage -0.5V to A_VDD+0.3V
Digital Input Voltage -0.5V to IO_VDD+0.3V
Digital Output Voltage -0.5V to IO_VDD+0.3V
Transmitter Output Voltage -0.5V to T_VDD+0.3V
Regulator Input Voltage (VREG_IN to D_VSS) -0.5V to 5.5V
Regulator Output Voltage (VREG_OUT to D_VSS) -0.5V to 5.5V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -65°C to +150°C
Junction Temperature 125°C
Thermal Impedance (θJA)Note – QFN 4×4 34.04°C/W
Note: θJA is determined by JEDEC 2S2P (4L), PCB size 76.2×114.3mm with 2×2 vias, following JEDEC51-5, -7.
Operating Condition
Symbol Parameter Conditions Min. Typ. Max. Unit
A_VDD Analog Power Supply Voltage — 2.7 3.3 3.6 V
IO_VDD Digital I/O Power Supply Voltage — 2.7 3.3 5.5 V
D_VDD Digital Core Power Supply Voltage Regulated from internal 1.54 1.65 2.20 V
T_VDD Transmitter Power Supply Voltage — 2.7 5.0 5.5 V
ESD Electrostatic Discharge Tolerance HBM model — 1.5 — kV
VPOR Reset Trigger Voltage IO_VDD & A_VDD 2.3 2.4 2.6 V
Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
I_A_VDD
Analog Power Supply Current
A_VDD=3.3 V
Active state (receiver on) — 5.5 6.4 mA
Idle state (receiver o󰀨) — 0.8 1.0 mA
Hard Power Down (pin RSTPD=1) — — 0.2 μA
Soft Power Down (bit PowerDown=1),
25°C — 1.7 2.4 μA
Soft Power Down (bit PowerDown=1),
-40°C to 85°C — — 3.5 μA
Standby (bit StandBy=1) — 0.7 0.9 mA
Wake Up Card Detection Mode
(Bit WkUpCD=1) – Sleep phaseNote,
25°C
— 1.7 2.4 μA
Wake Up Card Detection Mode
(Bit WkUpCD=1) – Detect phaseNote — 3.0 3.3 mA

Rev. 1.20 5 October 28, 2020
BC45B4523
Symbol Parameter Conditions Min. Typ. Max. Unit
I_IO_VDD
Digital I/O Power Supply Current
(Also Include Digital Core Current)
IO_VDD=3.3 V
Active state (CODEC on) — 1.0 1.2 mA
Idle state (CODEC o󰀨) — 0.9 1.1 mA
Hard Power Down (pin RSTPD=1) — — 0.2 μA
Soft Power Down (bit PowerDown=1),
25°C — 3.0 4.2 μA
Soft Power Down (bit PowerDown=1),
-40°C to 85°C — — 7.0 μA
Standby (bit StandBy=1) — 0.3 0.5 mA
Wake Up Card Detection Mode
(bit WkUpCD=1) – Sleep phaseNote — 3.0 4.2 μA
Wake Up Card Detection Mode
(bit WkUpCD=1) – Detect phaseNote — 0.9 1.1 mA
Itotal
Total Power Supply Current
I_IO_VDD + I_A_VDD + I_T_VDD
IO_VDD=A_VDD=T_VDD=3.3V,
I_TX=100mA
(Not Apply On-Chip 3.3V Regulator,
VREG_IN and VREG_OUT are Not
Connected)
Active state
(receiver on, transmitter o󰀨) — 6.6 7.6 mA
Idle state (receiver o󰀨, transmitter o󰀨) — 1.7 2.1 mA
Hard Power Down (pin RSTPD=1) — — 0.8 μA
Soft Power Down (bit PowerDown=1),
25°C — — 11.0 μA
Standby (bit StandBy=1) — 1.0 1.4 mA
Average at Wake Up Card Detection
Mode
@ TwkUp=500ms, transmitter on
periodically (calculated)
— 10.4 — μA
Average at Wake Up Card Detection
Mode
@ TwkUp=1000ms, transmitter on
periodically (calculated)
— 7.5 — μA
Note: Average power in Wake Up Card Detection Mode depends on duty cycle between Sleep and Detect period.
Pin Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
CRx RX Input Capacitance — — 4 — pF
IRx RX Input Leakage Current VRx=1.65V, 25°C — — 0.4 μA
Cin, io Digital Pin Input Capacitance — — 5 — pF
VINL Digital Logic Input Low Voltage — — — 0.8 V
VINH Digital Logic Input High Voltage — IO_VDD
- 0.8 — — V
VOL Digital Logic Output Low Voltage IO_VDD=3.3V, Isink=3mA — — 0.5 V
VOH Digital Logic Output High Voltage IO_VDD=3.3V, Isource=3mA 2.8 — — V
TrRise Time IO_VDD=3.3V, CL=15pF — 4 10 ns
TfFall Time IO_VDD=3.3V, CL=15pF — 4 10 ns
Iin,logic1 Logic 1 Input Current VINH=IO_VDD, 25°C — — 0.4 μA
Iin,logic0 Logic 0 Input Current VINL=0, 25°C — — 0.4 μA
Iout,logic1 Logic 1 Output Source Current IO_VDD=3.3V, 25°C 3 — — mA
Iout,logic0 Logic 0 Output Sink Current IO_VDD=3.3V, 25°C 3 — — mA

Rev. 1.20 6 October 28, 2020
BC45B4523
Transmitter Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
I_TX Transmitter Current, Continuous
Wave T_VDD=5V, 25°C, Average Current — — 250 mA
Z_TX,min Minimum Equivalent TX Output
Impedance (TxCfgCW=0x3F) T_VDD=5V, 25°C — 3 5 Ω
I_T_VDD,static Transmitter Static Power Supply
Current
Pin TX1 & TX2 are unconnected
TX1RFEn=1, TX2RFEn=1
T_VDD=5V
— 7 — mA
M Adjustable Modulation Index T_VDD=5V, 100ASK=0 0 — 60 %
T_VDD=5V, 100ASK=1 — — 100
Receiver Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VSEN Receiver Input Sensitivity A_VDD=3.3V — 2 — mVp
PSRR Power Supply Rejection Ratio A_VDD=3.3V + 0.2×sin(1MHz) — 40 — dB
VRx RX Input Voltage Range A_VDD=3.3V, ByPassENV=0 0.0 — 3.3 V
A_VDD=3.3V, ByPassENV=1 0.5 — 2.8
VCar,Min Minimum Carrier for Envelope Detector — — 0.25 — Vp
VVMID VMID Voltage A_VDD=3.3V 1.63 1.65 1.67 V
ZVMID
VMID Output Impedance
@ 13.56MHz CL=100nF, A_VDD=3.3V — — 0.5 Ω
Gain Gain (Measured from RX to the output
of the internal last amplier)
Gain[1:0]=11, Gain_ST3[2:0]=000 — — 48 dB
Gain[1:0]=00, Gain_ST3[2:0]=000 12 — —
Gstep Gain Step
AGCEn=1 — 3 —
dB
AGCEn=0
Dened by Gain[1:0] — 12 —
RxNoise Intrinsic Input Referred Noise in RX — — TBD — mVrms
FD, min Minimum RF Amplitude at RX Pin for
External RF Field Detection RF input at RX pin is in phase with
internal clock. When the phase is
di󰀨erent this value will be more.
— 10 — mVp
CD, min Minimum RF Amplitude Changing at
RX pin for Card Detection — 10 — mVp
Operation Timing
Symbol Parameter Conditions Min. Typ. Max. Unit
TPowerupNote Startup Time from Power-up From Power up till system
ready for SPI communication — — 4 ms
TstSPDNote Startup Time from Soft Power Down
From clearing Powerdown=0
until system ready for SPI
communication
— — 1.8 ms
TstHPDNote Startup Time from Hard Power
Down
From conguring pin RSTPD=0
until system ready for SPI
communication
— — 2.4 ms
TstSTBY Startup Time from Standby Mode
From clearing Standby=0
until system ready for SPI
communication
— 0.5 — μs
Note: Startup time is depended on the characteristic of external 27.12MHz quartz crystal.

Rev. 1.20 7 October 28, 2020
BC45B4523
Regulator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VREG_IN Regulator Input Voltage — 3.6 5.0 5.5 V
VREG_OUT Regulator Output Voltage IOUT=10mA, 25°C 3.25 3.30 3.35 V
IOUT Output Regulator Current — — — 150 mA
∆VoutLineReg Line Regulation (∆Vout) IOUT=0mA, 3.6V < VREG_IN < 5.5V — 0.5 1.0 mV/V
∆VoutLoadReg Load Regulation (∆Vout) VREG_IN=5V, 0 < IOUT < 150mA — 0.25 — mV/mA
IREGq Regulator Quiestcent Current No Load, VREG_IN=5V, 25°C — 2 — μA
IOUT=100mA, VREG_IN=5V, 25°C — 100 —
SPI Characteristics
Symbol Parameter Min. Max. Unit
tSCK1 NCS Low to 1st SCK High 12 — ns
tSCK2 Last SCK Low to NCS High 12 — ns
tSCKH SCK High Period 25 — ns
tSCKL SCK Low Period 25 — ns
tSCKDin Data Change to SCK High 12 — ns
tSCKDout SCK Low to Data Change 12 — ns
tNCSHZ1 NCS Low to MISO Active 12 — ns
tNCSHZ2 NCS High to MISO Hi-Impedance 12 — ns
SPIclk SPI Clock — 10 MHz
Hi-Z
MOSI
SCK
NCS
MISO
t
SCKH
t
SCKL
t
SCK1
t
SCKDin
t
SCKDout
t
SCK2
t
NCSHZ1
t
NCSHZ2
Hi-Z
SPI Interface Timing
Supported Protocols
Protocol Transmitter Receiver
Rate (kbps) Coding Rate (kbps) Coding
ISO14443A 106, 212, 424, 848 Miller 106 Manchester
212, 424, 848 BPSK
ISO14443B 106, 212, 424, 848 NRZ 106, 212, 424, 848 BPSK
ISO15693 26, 1.67 1 of 4, 1 of 256 53, 26, 13, 6.7 Manchester
26, 13, 6.7 FSK
Crypto_M 106 Miller 106 Manchester

Rev. 1.20 8 October 28, 2020
BC45B4523
Peripheral Specications
Block Properties Min. Typ. Max. Unit
FIFO Total Size — 64 — Byte
Program Timer Time Count — — 39.6 Sec
Trigger Source TxStart, TxStop, RxStart, RxStop, User —
Wake Up Timer
Time Count (for WkUpCD) 61.0μs — 1 day —
Timer Accuracy -1.5 — +1.5 %
Trigger Source User conguration —
Interrupt Trigger Source — —
Output Level Toggle High, Toggle Low —
Crystal Requirement
Symbol XTAL Spec Min. Typ. Max. Unit
fXTAL Frequency — 27.12 — MHz
TOL Frequency Tolerance — — ±30 ppm
CLOAD Load Capacitance — 10 — pF
ESR Equivalent Series Resistance — — 120 Ω
Functional Overview
The BC45B4523 contains a transmitter, a receiver,
a baseband processor and a voltage regulator. The
functional block diagram of the device is shown in the
Block Diagram chapter.
The transmitter contains integrated dual drivers,
supporting operating voltage from 2.7V to 5.5V.
The transmitter can be congured to support various
antenna topologies such as dierential driving, single-
ended driving and pre-driving for external Class-E
amplifiers. An on-chip coder can generate a variety
of line-coding, namely Miller to support ISO14443A,
NRZ to support ISO14443B, and 1-of-4 and 1-of-256
to support ISO15693. Moreover, a direct modulation
from pin TD is allowed.
The receiver consists of an on-chip envelope detector,
a voltage reference generator, an on-chip oscillator, an
amplier & lter system, a lter tuning system, a BPSK
bit decoder, a Manchester-and-FSK bit decoder, a frame
decoder and a timing control generator. A receiver
input, pin RX, can accept a carrier modulated signal
or an envelope-demodulated signal from an external
envelope detector. Employing an external envelope
detector can yield an extended read range. With this
exibility, it enables a wide variety of RF connection
topologies. The envelope of the input signal is ltered
and amplified with optional control by an automatic
gain control (AGC), resulting in an amplitude control
to prevent shape distortion. The BPSK bit decoder
and Manchester-and-FSK bit decoder translates the
amplied signal to the digital data. The bit data is then
checked the validity and assembled into bytes by the
digital frame decoder. Next, the complete and valid
bytes are transferred into the FIFO. In case of the
encryption, the Crypto_M engine is provided to encrypt
and decrypt as well as execute the authentication
process for the Crypto_M card.
The digital part contains an FIFO controller, a CRC
generator, a programmable timer, a wake-up timer, a
state machine, a wake-up controller and congurable
registers in order to facilitate RF transmission
and reception activities. The BC45B4523 can be
controlled and accessed through a 4-wire SPI interface
and register pages with the communication speed of
up to 10Mbps. An interrupt system and a pin IRQ are
provided to support interrupt-oriented programming
after the end of RF activities.
In addition, there are two regulators, 3.3V and 1.6V
output. The 3.3V regulator is applied for supplying
external load, MCU or analog parts itself with 150mA
driving capability. The 1.6V output is regulated
voltage from pin IO_VDD to D_VDD for supplying
digital circuit itself.
Typical Operating Circuit
A basic operating circuit and a typical usage are
illustrated in the following figures. A differential
antenna is directly connected to the transmitter driver
of the BC45B4523, whereas the receiver senses the
tag-modulated signal from the envelope of RF carrier
through the voltage divider. The device is controlled
by a microcontroller via an SPI interface. In addition,
other circuit congurations such as Class-E ampliers
with external envelope detectors or single-ended
drivers can be implemented and will be described in
the “Circuit Conguration” section.

Rev. 1.20 9 October 28, 2020
BC45B4523
BC45B4523
TX1
TX2
RX
VMID
XTAL1
XTAL2
27.12MHz
VREG_IN
T_VDD
100nF
100nF
10µF
A_VDD
VREG_OUT
IO_VDD
MCU
(3.3V)
VDD
T_VSS D_VSS A_VSS
D_VDD
100nF
+1.6 V
+3.3 V Power
RSTPD
IRQ
NCS
SCK
MOSI
MISO
TA
TD
Bead
100nF
10µF
Bea d
+5.0 V from USB Power
Typical Operating Circuit for External Power Supply (Not Apply On-Chip 3.3V Regulator)
BC45B4523
TX1
TX2
RX
VMID
XTAL1
XTAL2
27.12MHz
VREG_IN
T_VDD
100nF
100nF
10µF
A_VDD
100nF
10µF
VREG_OUT
100nF
10µF
IO_VDD
MCU
(3.3V)
VDD
T_VSS
D_VSS
A_VSS
D_VDD
100nF
+1.6 V
+3.3 V
+3.3 V
+5.0 V from USB Power
RSTPD
IRQ
NCS
SCK
MOSI
MISO
TA
TD
Bead
Typical Conguration Employing On-Chip Regulator for MCU with 3.3V I/O

Rev. 1.20 10 October 28, 2020
BC45B4523
BC45B4523
TX1
TX2
RX
VMID
XTAL1
XTAL2
27.12MHz
VREG_IN
T_VDD
100nF
100nF
10µF
A_VDD
VREG_OUT
IO_VDD
MCU
(5V)
VDD
T_VSS
D_VSS
A_VSS
D_VDD
100nF
+1.6 V
+3.3 V
+5.0 V from USB Power
RSTPD
IRQ
NCS
SCK
MOSI
MISO
TA
TD
Bead
100nF
10µF
Typical Conguration Employing On-Chip Regulator for MCU with 5.0V I/O
SPI Interface
The BC45B4523 can be interfaced through a standard 4-wire SPI interface in order to access to internal registers.
The SPI interface is capable of handling input stream with a speed of up to 10Mbps. There are 4 modes available
where their timing diagrams are depicted in the following figures. Depending on activities of the interfacing
controller, the purpose and usage of each SPI mode are shown in the table below. The timing constrain is shown
in “SPI Interface Timing” diagram presented in the “SPI Characteristics” section. Note that if NCS is set to high,
MISO will become high-impedance. This allows multiple SPI devices, in which Hi-Z feature in MISO is available,
controlled from the same MCU shown as the last gure in this section.
Mode Purpose and Usage
Single register/single byte write Setting value from a single setting register
Single register/single byte read Reading value from a single setting register
Single register/multiple-byte write Writing consecutive data to FIFO
Multiple register/multiple-byte read Reading consecutive data from FIFO. Monitoring status of the device
SPI Mode
Hi-Z
A[5]0A[3]A[4] A[1]A[2] 0A[0] D[6]D[7] D[4]D[5] D[2]D[3] D[0]D[1]MOSI
SCK
NCS
MISO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Command Write Input data
“0” indicated write command
Register address
Hi-Z
SPI Interface for Single Register/Single Byte Write

Rev. 1.20 11 October 28, 2020
BC45B4523
A[5]1A[3]A[4] A[1]A[2] 0A[0] 00 00 00 00MOSI
SCK
NCS
D[6]D[7] D[4]D[5] D[2]D[3] D[0]D[1]MISO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Output dataCommand Read
“1” indicated read command
Register address
SPI Interface for Single Register/Single Byte Read
00 A
0
[4:0]MOSI
SCK
NCS
0
12345678910
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MISO
Hi
-Z Hi-Z
D
0
[7:0] D
1
[7:0] D
2
[7:0]
SPI Interface for Single Register/Multiple-Byte Write
01 A
0
[4:0]MOSI
SCK
NCS
0 00 A
1
[4:0] 0 00 A
2
[4:0] 0 00 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
00 00 0
MISO D
0
[7:0] D
1
[7:0] D
2
[7:0]
Hi
-Z
Hi‐Z
SPI Interface for Multiple Register/Multiple-Byte Read
BC45B4523
MCU
MISO
MOSI
NCS1
SCK
NCS2
Other SPI
Device
MISO
MOSI
NCS
SCK
MISO
MOSI
NCS
SCK
MISO MOSI
SCK
NCS3
SPI Interface to Multiple SPI Devices Having hi-Z Feature in MISO Output

Rev. 1.20 12 October 28, 2020
BC45B4523
Registers
Register Overview
The device consists of 6-bit addressable registers which is grouped into 2 sectors. Each sector separated into
multiple pages by their functions. There are 4 types of registers, namely Dynamic, Write Only, Read/Write and
Read Only, in which their behaviours are described in the following table. The overview of the registers is shown
in the “Register List” tables.
Type Description
Dynamic (DY)
The Dynamic register is used to control behaviours of the reader IC as wells as display the status.
The Dynamic register can be either set by the external controller or automatically updated by
the internal state machine.
Write Only (W)
The write-only register is used for control behaviours of the reader IC, especially timers and
FIFO. These registers can only be written by the external controller. Reading from these
registers returns zero.
Read/Write (R/W) The read-write register is used to congure and control behaviours of the reader IC.
These registers can be written and read by the external controller.
Read Only (R) The read only register is used to display the status of the internal state machine.
Writing these registers will not a󰀨ect their values.
—These registers are intentionally left blank or reserved for future use, reading from these
registers returns zero.
Register Types
Register List
Sector 0
Page Addr. Register Name
Bit
7 6 54 3 2 1 0
Command and Status
0
0 0 Sector Select — — — — — — — Sector
0 1 Command Command[7:0]
0 2 FIFOData FIFOData[7:0]
0 3 PrimaryStatus — ModemState[2:0] IRQ ERR HiAlert LoAlert
0 4 FIFOLength — FIFOLength[6:0]
0 5 SecondaryStatus Trunning RF_Det CRCReady EMD_Det SubC_Det RxLastBit[2:0]
0 6 InterruptEnable SetIEn CDIEn TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
0 7 InterruptFlag SetIRq CDIRq TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
Control and Status
1
0 8 — — — — — — — — —
0 9 Control — WkUpCD StandBy PowerDown Crypto_MOn TStopNow TStartNow FlushFIFO
0 A Error — KeyErr — FIFOOvf CRCErr FramingErr ParityErr CollErr
0 B CollPos CollPos[7:0]
0 C TimerValue TimerValue[7:0]
0 D CRCResultLSB CRCResultLSB[7:0]
0 E CRCResultMSB CRCResultMSB[7:0]
0 F BitFraming — RxAlign[2:0] — TxLastBits[2:0]
TX and Coder
2
1 0 — — — — — — — — —
1 1 TxControl Tx1Inv ModulatorSource 100ASK Tx2Inv Tx2Cw Tx2RFEn Tx1RFEn
1 2 TxCfgCW — — TxCfgCW[5:0]
1 3 TxCfgMod — — TxCfgMod[5:0]
1 4 CoderControl Send1Pulse — CoderRate[2:0] TxCoding[2:0]
1 5 ModWidth ModWidth[7:0]
1 6 ModWidthSOF ModWidthSOF[7:0]
1 7 TypeBTxFraming NoTxSOF NoTxEOF EOFWidth CharSpacing[2:0] SOFWidth[1:0]
RX and Decoder
3
1 8 — — — — — — — — —
1 9 RxControl1 SubCPulses[2:0] SubCCarrier[1:0] LP_O󰀨 Gain[1:0]
1 A DecoderControl RxMultiple CollMarkVal ZeroAfterColl RxFraming[1:0] — RxCoding[1:0]
1 B BitPhase BitPhase[7:0]
1 C RxThreshold MinLevel[2:0] — CollLevel[2:0] —
1 D BPSKDemControl NoRxSOF NoRxEGT NoRxEOF HP2O󰀨 TauD[1:0] AGCEn TauAGC
1 E RxControl2 Cont_Int RxAutoPD — — Reserved ByPassEnv Reserved DecoderSrc
1 F RxControl3 BPSKDecMeth BPSKDataRec SOFSel15693 — — — EMD_
Suppress SOF43A_5Bits

Rev. 1.20 13 October 28, 2020
BC45B4523
Page Addr. Register Name
Bit
7 6 54 3 2 1 0
RF-Timming, Channel
Redundancy and ADC
4
2 0 Reserved Reserved
2 1 RxWait RxWait[7:0]
2 2 ChannelRedundancy — MSBFirst CRC3309 CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn
2 3 CRCPresetMSB CRCPresetMSB[7:0]
2 4 CRCPresetLSB CRCPresetLSB[7:0]
2 5 ADCCtrl — — ADC_Delay[1:0] FD_MinLvl ADC_
FastMode ADC_Rsln Reserved
2 6 ADC_Result_I ADC_Result_I[7:0]
2 7 ADC_Result_Q ADC_Result_Q[7:0]
FIFOLevel, Prog. Timer and
Wake Up Timer
5
2 8 — — — — — — — — —
2 9 FIFOLevel — — WaterLevel[5:0]
2 A TimerClock — — TAutoRestart TPreScaler[4:0]
2 B TimerControl — — — — TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin
2 C TimerReloadValue TReloadValue[7:0]
2 D WkTimerControl WkTStartNow WkTStopNow WkTRunning WkTAutoRestart WkTPreScaler[3:0]
2 E WkTimerReloadValue WkTReloadValue[7:0]
2 F WkTtrigTime — — — — WkTtrigTime[3:0]
Field Detection and
Card Detection
6
3 0 FDControl Reserved FDDetectTime[2:0] — — FDAverage[1:0]
3 1 WkCDControl Reserved WkCDGoActive WkIgnoreFD WkFDEn Reserved CDTxDelay CDAverage[1:0]
3 2 FDThreshold_I_H FDThreshold_I_H[7:0]
3 3 FDThreshold_Q_H FDThreshold_Q_H[7:0]
3 4 CDThreshold_I_L CDThreshold_I_L[7:0]
3 5 CDThreshold_I_H CDThreshold_I_H[7:0]
3 6 CDThreshold_Q_L CDThreshold_Q_L[7:0]
3 7 CDThreshold_Q_H CDThreshold_Q_H[7:0]
Test, IO Control and
RX Adjustment
7
3 8 — — — — — — — — —
3 9 TDIRqCtrl — — IO1_InValue IO0_InValue TDSelect IO1_Mode IO0_Mode IRqInv
3 A Test Reserved Test[6:0]
3 B Reserved Reserved
3 C Rx43A_Option Reserved RxCorrIntTime[1:0] Reserved SOFSel43A Reserved
3 D Reserved Reserved
3 E Reserved Reserved
3 F Gain_ST3 Reserved Gain_ST3[2:0] Reserved
Sector 1
Page Addr. Register Name
Bit
7 6 54 3 2 1 0
LFO and ADC Adjustment
0
0 0 Sector Select — — — — — — — Sector
0 1 LFOTrimResult LFOTrimResult[7:0]
0 2 ManLFOTrimValue ManLFOTrimValue[7:0]
0 3 LFOTrimSel Reserved — — — ManLFOTrim
0 4 FDCDIRqCong — — — — FDIRqCfg[1:0] CDIRqCfg[1:0]
0 5 ADC_Adjust — — — — Reserved ADC_
FullScaleAdj[1:0]
0 6 — — — — — — — — —
0 7 — — — — — — — — —
Production Parameter
1
0 8 Reserved Reserved
0 9 Reserved Reserved
0 A — — — — — — — — —
0 B Reserved Reserved
0 C — — — — — — — — —
0 D MaskSet MaskSet[7:0]
0 E ProductionParam ProductionParam[7:0]
0 F Revision Revision[7:0]

Rev. 1.20 14 October 28, 2020
BC45B4523
Page Addr. Register Name
Bit
7 6 54 3 2 1 0
TX Overshoot Control
2
1 0 TxFallingCtrl TxOvsT1Fall[3:0] TxOvsT2Fall[3:0]
1 1 TxRisingCtrl TxOvsT1Rise[3:0] TxOvsT2Rise[3:0]
1 2 TxCfgFall — — TxCfgFall[5:0]
1 3 TxCfgRise — — TxCfgRise[5:0]
1 4 — — — — — — — — —
1 5 — — — — — — — — —
1 6 — — — — — — — — —
1 7 — — — — — — — — —
3
1 8 — — — — — — — — —
1 9 — — — — — — — — —
1 A — — — — — — — — —
1 B — — — — — — — — —
1 C — — — — — — — — —
1 D — — — — — — — — —
1 E — — — — — — — — —
1 F — — — — — — — — —
4
2 0 — — — — — — — — —
2 1 — — — — — — — — —
2 2 — — — — — — — — —
2 3 — — — — — — — — —
2 4 — — — — — — — — —
2 5 — — — — — — — — —
2 6 — — — — — — — — —
2 7 — — — — — — — — —
RX Amplier Corner
5
2 8 — — — — — — — — —
2 9 — — — — — — — — —
2 A — — — — — — — — —
2 B — — — — — — — — —
2 C — — — — — — — — —
2 D — — — — — — — — —
2 E ManualFilter M_HP1[1:0] M_LP1[1:0] M_HP2[1:0] M_LP2[1:0]
2 F FilterAdjust ManFilterSel EnAutoTune — — Filter_Corner_Coef[3:0]
AGC_SSI and RX Freq.
Tuning
6
3 0 — — — — — — — — —
3 1 — — — — — — — — —
3 2 — — — — — — — — —
3 3 — — — — — — — — —
3 4 — — — — — — — — —
3 5 — — — — — — — — —
3 6 — — — — — — — — —
3 7 Signal indicator SSI[3:0] CFTV[3:0]
7
3 8 — — — — — — — — —
3 9 — — — — — — — — —
3 A — — — — — — — — —
3 B — — — — — — — — —
3 C — — — — — — — — —
3 D — — — — — — — — —
3 E — — — — — — — — —
3 F — — — — — — — — —

Rev. 1.20 15 October 28, 2020
BC45B4523
Register Details
Sector 0 – Page 0: Command and Status
• Sector Select Register
This register is used for sector selection.
Address Bit 7 6 543210
0x00
Name — — — — — — — Sector
Type — — — — — — — R/W
Reset Value — — — — — — — 0
Bit 7~1 Unimplemented, read as “0”
Bit 0 Sector: Dene sector for register page control
• Command Register
This register is used for command execution.
Address Bit 7 6 543210
0x01
Name Command[7:0]
Type DY
Reset Value 0 0 0 0 0 0 0 0
Bit 7~0 Command[7:0]: Commands for the device execution
Code Command
0x00 Idle
0x1A Transmit
0x16 Receive
0x1E Transceive
0x12 CalCRC
0x19 LoadKeyFIFO
0x1C Authent
0x10 RxFilterTune
0x20 LFOTune
0x21 ADCCalibrate
0x22 CardDetect
0x23 FieldDetect
0x31 ReadSignature
• FIFOData Register
This register is the input and output channel for the 64-byte FIFO.
Address Bit 7 6 543210
0x02
Name FIFOData[7:0]
Type DY
Reset Value x x x x x x x x
“x”: Unknown
Bit 7~0 FIFOData[7:0]: Input and output channel for transmission, reception and key initialization.

Rev. 1.20 16 October 28, 2020
BC45B4523
• PrimaryStatus Register
This register contains ags for indicating the status of modem, interrupt and FIFO.
Address Bit 7 6 543210
0x03
Name — ModemState[2:0] IRQ ERR HiAlert LoAlert
Type — R R R R R
Reset Value — 0 0 0 0 1 0 1
Bit 7 Unimplemented, read as “0”
Bit 6~4 ModemState[2:0]: Indicate the state of RX, TX and FIFO
000: Idle – No operation, neither the transmitter nor the receiver is in operation
001: TxSOF – The transmitter is transmitting “Start of Frame” pattern
010: TxData – The transmitter is transmitting data from FIFO or CRC
011: TxEOF – The transmitter is transmitting “End of Frame” pattern
100: RxPrepare – Receiver circuitry is initialized at this state and wait for time period dened by the
RxWait and BitPhase bits before starting to receive data
101: RxAwaiting – The receiver starts and is waiting for RX Start of Frame from tag
110: Receiving – The receiver is receiving data
Bit 3 IRQ: Interrupt request indication
If there are one or more interrupt requests in InterruptFlag register, the IRQ ag will be set to 1.
Bit 2 ERR: Error indication
If one or more errors occur in the Error register (Sector0-0x0A), the ERR ag will be set to 1.
Bit 1 HiAlert: FIFO HiAlert warning ag
If FIFOLength ≥ 64-Waterlevel, the HiAlert ag will be set to 1.
Bit 0 LoAlert: FIFO LoAlert warning ag
If FIFOLength ≤ Waterlevel, the LoAlert ag will be set to 1.
• FIFOLength Register
This register indicates the number of data remaining in the FIFO buer.
Address Bit 7 6 54 3 2 1 0
0x04
Name — FIFOLength[6:0]
Type — R
Reset Value — 0 0 0 0 0 0 0
Bit 7 Unimplement, read as “0”
Bit 6~0 FIFOLength[6:0]: Indicates the number of data remaining in the FIFO buer
• SecondaryStatus Register
This register contains the status ags and values related to timers, CRC and receiver status.
Address Bit 7 6 54 3 2 1 0
0x05
Name Trunning RF_Det CRCReady EMD_Det SubC_Det RxLastBit[2:0]
Type R R R R R R
Reset Value 0 0 1 0 0 0 0 0
Bit 7 Trunning: Timer running state indication
If Timer is running, Trunning will be set to 1. The value in TimerValue register decreases at the rate of
timer clock, prescaling from 13.56MHz by TPreScaler bit eld.

Rev. 1.20 17 October 28, 2020
BC45B4523
Bit 6 RF_Det: RF eld detection indication
RF_Det being set to 1 indicates that external RF eld level is higher than threshold level after execute
FieldDetect command or WkUpCD Power Saving Mode.
Bit 5 CRCReady: CRC ready indication
CRCReady being set to 1 indicates that the CRC co-processor is in idle state and ready to operate.
Bit 4 EMD_Det: EMD detection indication
The EMD_Det will be set to 1 if the reader system suppresses a frame that falls in EMD criteria. This
indicator bit is active when control bit EMD_Suppress (Sector0-0x1F.1) is enabled and is automatically
cleared during “RxAwaiting” state.
Bit 3 SubC_Det: Subcarrier detection indication
The SubC_Det is set to 1 when preamble or SOF is detected. In case of BPSK coding, SubC_Det
asserts when preamble is detected. In case of Manchester and FSK coding, SubC_Det asserts when
SOF is detected. This bit is automatically cleared during “RxAwaiting” state.
Bit 2~0 RxLastBit[2:0]: Indicates the number of valid bits in the last received byte
RxLastBit displays the number of valid bits in the last received byte in the bit-oriented frame response.
If RxLastBit is zero, the last received byte is complete and valid.
• InterruptEnable Register
This register is used for interrupt enable control.
Address Bit 7 6 54 3 2 1 0
0x06
Name SetIEn CDIEn TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
Type W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Bit 7 SetIEn: Interrupt enable setup
SetIEn is a mask bit used in setting and resetting interrupt enable bits. Setting this bit to 1 makes the
interrupt enable bits, which are written with 1, set. While clearing this bit to 0 makes the interrupt
enable bits, which are written with 1, cleared.
E.g. Writing 7F to this interruptEnable register clears all interrupt enable bits.
Writing FF to this interruptEnable register sets all interrupt enable bits.
Bit 6 CDIEn: Card detection interrupt enable
If this bit is set to 1, the card detection interrupt request (CDIRq) will be sent to pin IRQ.
Bit 5 TimerIEn: Timer interrupt enable
If this bit is set to 1, the timer interrupt request (TimerIRq) will be sent to pin IRQ.
Bit 4 TxIEn: Transmitter interrupt enable
If this bit is set to 1, the transmitter interrupt request (TxIRq) will be sent to pin IRQ.
Bit 3 RxIEn: Receiver interrupt enable
If this bit is set to 1, the receiver interrupt request (RxIRq) will be sent to pin IRQ.
Bit 2 IdleIEn: Idle interrupt enable
If this bit is set to 1, the idle interrupt request (IdleIRq) will be sent to pin IRQ.
Bit 1 HiAlertIEn: FIFO HiAlert interrupt enable
If this bit is set to 1, the FIFO HiAlert interrupt request (HiAlertIRq) will be sent to pin IRQ.
Bit 0 LoAlerIEn: FIFO LoAlert interrupt enable
If this bit is set to 1, the FIFO LoAlert interrupt request (LoAlertIRq) will be sent to pin IRQ.

Rev. 1.20 18 October 28, 2020
BC45B4523
• InterruptRequest Register
This register contains the interrupt request bits.
Address Bit 7 6 54 3 2 1 0
0x07
Name SetIRq CDIRq TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
Type W DY DY DY DY DY DY DY
Reset Value 0 0 0 0 0 1 0 1
Bit 7 SetIRq: Interrupt request setup
SetIRq is a mask bit used in resetting interrupt request bits. Clearing this bit to 0 makes the interrupt
request bits, which are written with 1, cleared. Setting this bit to 1 has no eect.
E.g.: Writing 7F to the interruptFlag register clears all interrupt request bits.
Bit 6 CDIRq: Card detection interrupt request ag
CDIRq is set to 1 when ADC_Result from Card Detection operation, both direct command or Wake Up
Card Detection mode, follows the following conditions
- ADC_Result > CDThreshold_H or
- ADC_Result < CDThreshold_L
Bit 5 TimerIRq: Timer interrupt request ag
TimerIRq is set to 1 when the program timer value (13.56MHz) decreases to zero, or counter value of
Wake up timer (16.38kHz) decreases to zero, refer to the registers in page 5 of Sector 0 for details.
Bit 4 TxIRq: Transmitter interrupt request ag
TxIRq is set to 1 when one of these events occurs:
- Transmit Command: All data have been transmitted
- Transceive Command: All data have been transmitted
- CalCRC Command: All data have been processed
- LoadKeyFIFO Command: Key is already in the buer
Bit 3 RxIRq: Receiver interrupt request ag
RxIRq is set to 1 when the receiver nishes receiving, which can be one of these events:
- Transceive Command: All data have been received
- Receiver Command: All data have been received
Or in Field Detection operation, both direct command or Wake Up Card Detection mode, follows this
condition
- ADC_Result > FDThreshold_H, which refers to FDIRq of system.
Bit 2 IdleIRq: Idle interrupt request ag
IdleIRq is set to 1 when the operation of command is nished and the state is changed to idle. End
of operation of all commands causes the IdleIRq being set to 1. Setting power down, standby or Idle
command does not set IdleIRq.
Bit 1 HiAlertIRq: FIFO HiAlert interrupt request ag
HiAlertIRq is set to 1 when FIFOLength > 64 - WaterLevel
Bit 0 LoAlertIRq: FIFO LoAlert interrupt request ag
LoAlertIRq is set to 1 when FIFOLength < WaterLevel

Rev. 1.20 19 October 28, 2020
BC45B4523
Sector 0 – Page 1: Control and Status
• Control Register
This register contains the control bits for all operation of reader system.
Address Bit 7 6 54 3 2 1 0
0x09
Name — WkUpCD StandBy PowerDown Crypto_MOn TStopNow TStartNow FlushFIFO
Type — DY DY DY DY W W W
Reset Value — 0 0 0 0 0 0 0
Bit 7 Unimplemented, read as “0”
Bit 6 WkUpCD: Wake Up Card Detection Mode control
Setting this bit to 1 enables Wake Up Card Detection Mode. The device automatically changes mode
between Sleep Mode, which is low power mode, and Active Mode that turn on RF eld and measure
RF amplitude.
Bit 5 Standby: Standby Mode control
Setting this bit to 1 enters the Standby mode. In this mode, the oscillator is still running. All current
consuming blocks are turned o.
Bit 4 PowerDown: Soft Power Down Mode control
Setting this bit to 1 enters the Soft Power Down mode. In this mode, the oscillator is turned o and all
current consuming blocks are turned o.
Bit 3 Crypto_MOn: Crypto_M engine control
If Crypto_MOn is set to 1, the crypto engine will be switched on and the RF communication will be
encrypted. Crypto_MOn is set to 1 only if the authentication process is successful. This bit can be
cleared by external control.
Bit 2 TStopNow: Timer immediate stop control
Setting this bit to 1 stops the program timer (13.56MHz) immediately. Reading result from this bit is
always 0.
Bit 1 TStartNow: Timer immediate start control
Setting this bit to 1 starts the program timer (13.56MHz) immediately. Reading result from this bit is
always 0.
Bit 0 FlushFIFO: Flush FIFO
If this bit is set to 1, the FIFO read/write-pointer and the FIFOOvf ag will be cleared as well as the
FIFOLength will become to zero. Reading result from this bit is always 0.
• Error Register
This register contains error ags for the last executed command.
Address Bit 7 6 54 3 2 1 0
0x0A
Name — KeyErr — FIFOOvf CRCErr FramingErr ParityErr CollErr
Type — R — R R R R R
Reset Value — 1 — 0 0 0 0 0
Bit 7 Unimplemented, read as “0”
Bit 6 KeyErr: Key format error
KeyErr will be set to 1 if the key format in the key buffer is incorrect. As the key buffer is not
initialized, KeyErr is set after reset.
Bit 5 Unimplemented, read as “0”
Bit 4 FIFOOvf: FIFO overow ag
FIFOOvf will be set to 1 if FIFO is written from the external microprocessor or the state machine while
FIFO is full. FIFOOvf is cleared when FIFO is ushed.

Rev. 1.20 20 October 28, 2020
BC45B4523
Bit 3 CRCErr: CRC error
CRCErr will be set to 1 if RxCRCEn is set and the comparison between received CRC and calculated
CRC giving a mismatched result. CRCErr is automatically cleared to 0 every time the receiver starts to
receive.
Bit 2 FramingErr: Framing error
FramingErr will be set to 1 if the received frame format does not conform to the defined protocol.
FramingErr is automatically cleared to 0 every time the receiver starts to receive.
Bit 1 ParityErr: Parity error
ParityErr will be set to 1 if the parity check has failed. ParityErr is automatically cleared to 0 every time
the receiver starts to receive.
Bit 0 CollErr: Collision error
CollErr will be set to 1 if the bit-collision in ISO14443A and ISO15693 is detected. CollErr is
automatically cleared to 0 every time the receiver starts to receive.
• CollPos Register
This register indicates the bit collision position.
Address Bit 7 6 543210
0x0B
Name CollPos[7:0]
Type R
Reset Value 0 0 0 0 0 0 0 0
Bit 7~0 CollPos[7:0]: Collision position
0x00: the bit collision occurs at the start bit
0x01: the bit collision occurs at the 1st bit
0x0A: the bit collision occurs at the 10th bit
CollPos indicates the bit position of the rst detected collision in a received frame. For receving frame
with parity, ISO14443A, if the collision occurred at parity position, CollPos value is not increased, it
will display the last uncollision bit. Refer to the “Collision Detection” chapter for more details.
• TimerValue Register
This register contains the timer counter value.
Address Bit 7 6 543210
0x0C
Name TimerValue[7:0]
Type R
Reset Value 1 1 1 1 1 1 1 1
Bit 7~0 TimerValue[7:0]: Timer counter value
• CRCResultLSB Register
This register contains the CRC result.
Address Bit 7 6 54 3 2 1 0
0x0D
Name CRCResultLSB[7:0]
Type R
Reset Value 0 1 1 0 0 0 1 1
Bit 7~0 CRCResultLSB[7:0]: The least signicant byte of the CRC result
The value of this register is valid only if the CRCReady bit is set to 1.