Holtek HT46R65 User manual

HT46R65/HT46C65
A/D with LCD Type 8-Bit MCU
Rev. 1.90 1 February 14, 2006
Features
·Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
·24 bidirectional I/O lines
·Two external interrupt input
·Two 16-bit programmable timer/event counter with
PFD (programmable frequency divider) function
·LCD driver with 41´3or40´4 segments
(logical output option for SEG0~SEG23)
·8K´16 program memory
·384´8 data memory RAM
·Supports PFD for sound generation
·Real Time Clock (RTC)
·8-bit prescaler for RTC
·Watchdog Timer
·Buzzer output
·On-chip crystal, RC and 32768Hz crystal oscillator
·HALT function and wake-up feature reduce power
consumption
·16-level subroutine nesting
·8 channels 10-bit resolution A/D converter
·4-channel 8-bit PWM output shared with 4 I/O lines
·Bit manipulation instruction
·16-bit table read instruction
·Up to 0.5ms instruction cycle with 8MHz system clock
·63 powerful instructions
·All instructions in 1 or 2 machine cycles
·Low voltage reset/detector function
·52-pin QFP, 56-pin SSOP, 100-pin QFP packages
General Description
The HT46R65/HT46C65 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C65 is fully pin and
functionally compatible with the OTP version HT46R65
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
Technical Document
·Tools Information
·FAQs
·Application Note
-HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
-HA0004E HT48 & HT46 MCU UART Software Implementation Method
-HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
-HA0047E An PWM application example using the HT46 series of MCUs

Block Diagram
HT46R65/HT46C65
Rev. 1.90 2 February 14, 2006
P r o g r a m
C o u n t e r
P r o g r a m
E P R O M
I n s t r u c t i o n
R e g i s t e r
I n s t r u c t i o n
D ecoder
T i m i n g
G e n e r a t i o n
O S C 2
O S C 4
O S C 1
R E S
V D D
V S S
O S C 3
I n t e r r u p t
C i r c u i t
I N T C
M P MX
M X
D A T A
M e m o r y
A L
S h i f t e r
S T A T S
A C C
T M R 0 C
T M R 0
MX
MX
W D T O S C
R T C O S C
O S C 3
O S C 4
R T C
S T A C K
L C D
M e m o r y
B P
L C D D R I V E R
C O M 0 ~
C O M 2
C O M 3 /
S E G 4 0
S E G 0 ~
S E G 3 9
T i m e B a s e
W D T
T M R 1 C
T M R 1
MX
P F D 0
P F D 1
fS Y S / 4
fS Y S
P r e s c a l e r
P D 6 / T M R 0
fS Y S / 4
P A C
P A
P o r t A
P D C
P D
P o r t D
P D 0 / P W M 0 ~ P D 3 / P W M 3
P D 4 / I N T 0
P D 5 / I N T 1
P D 6 / T M R 0
P D 7 / T M R 1
P o r t B
P B
PBC
P B 0 / A N 0 ~ P B 7 / A N 7
P A 0 / B Z
P A 1 / B Z
PA2
P A 3 / P F D
PA4~PA7
P W M
8-C hannel
A / D C o n v e r t e r
H A L T E N / D I S
L V D / L V R
32768H z
P D 7 / T M R 1

Pin Assignment
Note: The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must
select the R type by option.
HT46R65/HT46C65
Rev. 1.90 3 February 14, 2006
H T 4 6 R 6 5 / H T 4 6 C 6 5
1 0 0 Q F P - A
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
81828384858687888990919293949596979899100 8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
P A 5
N C
N C
N C
N C
N C
P A 6
P A 7
P B 0 / A N 0
P B 1 / A N 1
P B 2 / A N 2
P B 3 / A N 3
P B 4 / A N 4
P B 5 / A N 5
P B 6 / A N 6
P B 7 / A N 7
V S S
P D 0 / P W M 0
P D 1 / P W M 1
P D 2 / P W M 2
P D 3 / P W M 3
P D 4 / I N T 0
P D 5 / I N T 1
P D 6 / T M R 0
P D 7 / T M R 1
N C
N C
N C
N C
N C
S E G 3 0 S E G 3 1 S E G 3 2 S E G 3 3 S E G 3 4 S E G 3 5 S E G 3 6 S E G 3 7 S E G 3 8 S E G 3 9 C O M 3 / S E G 4 0
C O M 2
C O M 1
C O M 0
C 2 C 1 V 2 V 1 V M A X
V L C D
S E G 9
S E G 1 0
S E G 1 1
N C
N C
N C
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
N C
N C
N C
N C
N C
N C
S E G 8 S E G 7 S E G 6 S E G 5 S E G 4 S E G 3 S E G 2 S E G 1 S E G 0
O S C 4 O S C 3
V D D
O S C 2 O S C 1
R E S
P A 0 / B Z
P A 1 / B Z
P A 2
P A 3 / P F D
P A 4
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
H T 4 6 R 6 5 / H T 4 6 C 6 5
5 6 S S O P - A
P A 0 / B Z
P A 1 / B Z
P A 2
P A 3 / P F D
P A 4
P A 5
P A 6
P A 7
P B 0 / A N 0
P B 1 / A N 1
P B 2 / A N 2
P B 3 / A N 3
P B 4 / A N 4
P B 5 / A N 5
V S S
P D 0 / P W M 0
P D 1 / P W M 1
P D 2 / P W M 2
P D 4 / I N T 0
P D 5 / I N T 1
P D 6 / T M R 0
V L C D
V M A X
V 1
V 2
C 1
C 2
C O M 0
R E S
O S C 1
O S C 2
V D D
O S C 3
O S C 4
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
S E G 3 2
S E G 3 3
S E G 3 4
C O M 3 / S E G 4 0
C O M 2
C O M 1
P A 5
P A 6
P A 7
P B 0 / A N 0
P B 1 / A N 1
P B 2 / A N 2
P B 3 / A N 3
P B 4 / A N 4
P B 5 / A N 5
V S S
P D 0 / P W M 0
P D 1 / P W M 1
P D 2 / P W M 2
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
3 4
3 5
3 6
3 7
3 8
3 9
4 84 95 05 15 2
2 3 2 4 2 5 2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
H T 4 6 R 6 5 / H T 4 6 C 6 5
5 2 Q F P - A
4 04 14 24 34 44 54 64 7
S E G 1 8 S E G 1 7
O S C 4 O S C 3
V D D
O S C 2 O S C 1
R E S
P A 0 / B Z P A 1 / B Z
P A 2
P A 3 / P F D
P A 4
S E G 3 2 S E G 3 3 S E G 3 4 C O M 3 / S E G 4 0 C O M 2 C O M 1 C O M 0 V 1 V M A X
V L C D P D 6 / T M R 0
P D 5 / I N T 1 P D 4 / I N T 0

Pin Description
Pin Name I/O Options Description
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
I/O
Wake-up
Pull-high
Buzzer
PFD
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up in-
put by ROM code option. Software instructions determine the CMOS output
or Schmitt trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The BZ, BZ and PFD are pin-shared with PA0,
PA1 and PA3, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mined by pull-high option: bit option) or A/D input. Once a PB line is selected
as an A/D input (by using software control), the I/O function and pull-high re-
sistor are disabled automatically.
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
I/O Pull-high
PWM
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (deter-
mined by pull-high option: bit option). The PWM0/PWM1/PWM2/PWM3 out-
put function are pin-shared with PD0/PD1/PD2/PD3 (dependent on PWM
options).
PD4/INT0
PD5/INT1
PD6/TMR0
PD7/TMR1
I/O Pull-high
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (deter-
mined by pull-high option: bit option). The INT0, INT1, TMR0 and TMR1 are
pin-shared with PD4/PD5/PD6/PD7.
VSS ¾¾ Negative power supply, ground
VLCD I ¾LCD power supply
VMAX I ¾IC maximum voltage connect to VDD, VLCD or V1
V1, V2, C1, C2 I ¾Voltage pump
COM0~COM2
COM3/SEG40 O1/3or1
/4 Duty SEG40 can be set as a segment or as a common output driver for LCD panel
by options. COM0~COM2 are outputs for LCD panel plate.
SEG0~SEG39 O Logical Output LCD driver outputs for LCD panel segments. SEG0~SEG23 can be optioned
as logical outputs.
OSC1
OSC2
I
OCrystal or RC
OSC1 and OSC2 are connected to an RC network or a crystal (by options) for
the internal system clock. In the case of RC operation, OSC2 is the output ter-
minal for 1/4 system clock. The system clock may come from the RTC oscilla-
tor. If the system clock comes from RTCOSC, these two pins can be floating.
OSC3
OSC4
I
O
RTC or
System Clock
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes or to a system clock source (depending
on the options). No built-in capacitor
VDD ¾¾ Positive power supply
RES I¾Schmitt trigger reset input, active low
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT46R65/HT46C65
Rev. 1.90 4 February 14, 2006

D.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage
¾fSYS=4MHz 2.2 ¾5.5 V
¾fSYS=8MHz 3.3 ¾5.5 V
IDD1 Operating Current
(Crystal OSC, RC OSC)
3V No load, ADC Off,
fSYS=4MHz
¾12mA
5V ¾35mA
IDD2 Operating Current
(Crystal OSC, RC OSC) 5V No load, ADC Off, fSYS=8MHz ¾48mA
IDD3
Operating Current
(fSYS=32768Hz)
3V
No load, ADC Off
¾0.3 0.6 mA
5V ¾0.6 1 mA
ISTB1
Standby Current
(*fS=T1)
3V No load, system HALT,
LCD Off at HALT
¾¾ 1mA
5V ¾¾ 2mA
ISTB2
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, C type
¾2.5 5 mA
5V ¾10 20 mA
ISTB3
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
LCD On at HALT, C type
¾25 mA
5V ¾610
mA
ISTB4
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
¾17 30 mA
5V ¾34 60 mA
ISTB5
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
¾13 25 mA
5V ¾28 50 mA
ISTB6
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
¾14 25 mA
5V ¾26 50 mA
ISTB7
Standby Current
(*fS=WDT OSC)
3V No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
¾10 20 mA
5V ¾19 40 mA
VIL1 Input Low Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1 ¾¾ 0¾0.3VDD V
VIH1 Input High Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1 ¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.4VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
VLVR Low Voltage Reset Voltage ¾¾ 2.7 3.0 3.3 V
VLVD Low Voltage Detector Voltage ¾¾ 3.0 3.3 3.6 V
IOL1 I/O Port Segment Logic Output
Sink Current
3V VOL=0.1VDD
612
¾mA
5V 10 25 ¾mA
IOH1 I/O Port Segment Logic Output
Source Current
3V VOH=0.9VDD
-2-4¾mA
5V -5-8¾mA
HT46R65/HT46C65
Rev. 1.80 5 July 14, 2005

Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
IOL2 LCD Common and Segment
Current
3V VOL=0.1VDD
210 420 ¾mA
5V 350 700 ¾mA
IOH2 LCD Common and Segment
Current
3V VOH=0.9VDD
-80 -160 ¾mA
5V -180 -360 ¾mA
RPH Pull-high Resistance of I/O Ports
and INT0, INT1
3V ¾20 60 100 kW
5V ¾10 30 50 kW
VAD A/D Input Voltage ¾¾ 0¾VDD V
EAD A/D Conversion Integral
Nonlinearity Error ¾¾ ¾±0.5 ±1LSB
IADC Additional Power Consumption
if A/D Converter is Used
3V ¾¾0.5 1 mA
5V ¾1.5 3 mA
Note: ²*fS²please refer to clock option of Watchdog Timer
A.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
fSYS1 System Clock
¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fSYS2 System Clock
(32768Hz Crystal OSC) ¾2.2V~5.5V ¾32768 ¾Hz
fRTCOSC RTC Frequency ¾¾ ¾
32768 ¾Hz
fTIMER Timer I/P Frequency
(TMR0/TMR1)
¾2.2V~5.5V 0 ¾4000 kHz
¾3.3V~5.5V 0 ¾8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾45 90 180 ms
5V ¾32 65 130 ms
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Power-up or wake-up from
HALT ¾1024 ¾tSYS
tLVR Low Voltage Width to Reset ¾¾ 1¾¾
ms
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
tAD A/D Clock Period ¾¾ 1¾¾ms
tADC A/D Conversion Time ¾¾ ¾
76 ¾tAD
tADCS A/D Sampling Time ¾¾ ¾
32 ¾tAD
Note: tSYS= 1/fSYS
HT46R65/HT46C65
Rev. 1.90 6 February 14, 2006

HT46R65/HT46C65
Rev. 1.90 7 February 14, 2006
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
Program Counter -PC
The program counter (PC) is 13 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 8192 addresses.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading a PCL register, a subroutine call, an ini-
tial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C P C + 1 P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
Execution Flow
Mode Program Counter
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0000000000000
External Interrupt 0 0000000000100
External Interrupt 1 0000000001000
Timer/Event Counter 0 Overflow 0000000001100
Timer/Event Counter 1 Overflow 0000000010000
Time Base Interrupt 0000000010100
RTC Interrupt 0000000011000
Skip Program Counter+2
Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *12~*0: Program counter bits S12~S0: Stack register bits
#12~#0: Instruction code bits @7~@0: PCL bits

HT46R65/HT46C65
Rev. 1.90 8 February 14, 2006
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL per-
forms a short jump. The destination is within 256 loca-
tions.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory -EPROM
The program memory (EPROM) is used to store the pro-
gram instructions which are to be executed. It also con-
tains data, table, and interrupt entries, and is organized
into 8192´16 bits which are addressed by the program
counter and table pointer.
Certain locations in the ROM are reserved for special
usage:
·Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
·Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
·Location 008H
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
·Location 00CH
Location 00CH is reserved for the Timer/Event Coun-
ter 0 interrupt service program. If a timer interrupt re-
sults from a Timer/Event Counter 0 overflow, and if the
interrupt is enabled and the stack is not full, the pro-
gram begins execution at location 00CH.
·Location 010H
Location 010H is reserved for the Timer/Event Coun-
ter 1 interrupt service program. If a timer interrupt re-
sults from a Timer/Event Counter 1 overflow, and if the
interrupt is enabled and the stack is not full, the pro-
gram begins execution at location 010H.
·Location 014H
Location 014H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 014H.
·Location 018H
Location 018H is reserved for the real time clock inter-
rupt service program. If a real time clock interrupt oc-
curs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 018H.
·Table location
Any location in the ROM can be used as a look-up ta-
ble. The instructions ²TABRDC [m]²(the current page,
1 page=256 words) and ²TABRDL [m]²(the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the ta-
ble word are all transferred to the lower portion of
TBLH. The TBLH is read only, and the table pointer
(TBLP) is a read/write register (07H), indicating the ta-
ble location. Before accessing the table, the location
should be placed in TBLP. All the table related instruc-
tions require 2 cycles to complete the operation.
These areas may function as a normal ROM depend-
ing upon the user¢s requirements.
D e v i c e i n i t i a l i z a t i o n p r o g r a m
E x t e r n a l i n t e r r u p t 0 s u b r o u t i n e
T i m e r / e v e n t c o u n t e r 0 i n t e r r u p t s u b r o u t i n e
P r o g r a m
M e m o r y
E x t e r n a l i n t e r r u p t 1 s u b r o u t i n e
T i m e B a s e I n t e r r u p t
R T I n t e r r u p t
T i m e r / e v e n t c o u n t e r 1 i n t e r r u p t s u b r o u t i n e
0 0 0 H
0 0 4 H
0 0 8 H
0 1 4 H
0 1 8 H
0 0 H
0 1 0 H
Look-up table (256 w ords)
1 F F F H
N o t e : n r a n g e s f r o m 0 t o 1 F
Look-up table (256 w ords)
n00H
n F F H
1 6 b i t s
1F00H
Program Memory
Instruction(s) Table Location
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *12~*0: Table location bits P12~P8: Current program counter bits
@7~@0: Table pointer bits

HT46R65/HT46C65
Rev. 1.90 9 February 14, 2006
Stack Register -STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledg-
ment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL²is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
Data Memory -RAM
The data memory (RAM) is designed with 417´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers 33´8 bit and general purpose data
memory, Bank0: 192´8 bit and Bank2: 192´8 bit most of
which are readable/writeable, although some are read
only. The special function register are overlapped in any
banks.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event
Counter 0 control register (TMR0C;0EH), a Timer/Event
Counter 1 (TMR1H:0FH;TMR1L:10H), a Timer/Event
Counter 1 control register (TMR1C; 11H), Interrupt con-
trol register 1 (INTC1;1EH) , PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH),
the A/D result lower-order byte register (ADRL;24H), the
A/D result higher-order byte register (ADRH;25H), the
A/D control register (ADCR;26H), the A/D clock setting
register (ACSR;27H), I/O registers (PA;12H, PB;14H,
PD;18H) and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is re-
served for future expanded usage and reading these lo-
cations will get ²00H². The space before 40H is
overlapping in each bank. The general purpose data
memory, addressed from 40H to FFH (Bank0; BP=0 or
Bank2; BP=2), is used for data and control information
under instruction commands. All of the data memory ar-
eas can handle arithmetic, logic, increment, decrement
and rotate operations directly. Except for some dedi-
cated bits, each bit in the data memory can be set and
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 H
1 D H
1 E H
1 F H
: U n u s e d
R e a d a s " 0 0 "
G e n e r a l P u r p o s e
D a t a M e m o r y
( 3 8 4 B y t e s )
F F H
40H
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
B P
A
P L
T B L P
T B L H
R T
S T A T U S
I N T 0
T M R 0 H
T M R 0 L
T M R 0
T M R 1 H
T M R 1 L
T M R 1
P A
P A
P B
P B
P D
P D
P W M 0
P W M 1
P W M 2
P W M 3
I N T 1
A D R L
A D R H
A D R
A S R
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
3 F H
RAM Mapping

HT46R65/HT46C65
Rev. 1.90 10 February 14, 2006
reset by ²SET [m].i²and ²CLR [m].i². They are also indi-
rectly accessible through memory pointer registers
(MP0;01H/MP1;03H). The space before 40H is overlap-
ping in each bank.
After first setting up BP to the value of ²01H²or ²02H²to
access either bank 1 or bank 2 respectively, these banks
must then be accessed indirectly using the Memory
Pointer MP1. With BP set to a value of either ²01H²or
²02H², using MP1 to indirectly read or write to the data
memory areas with addresses from 40H~FFH will result
in operations to either bank 1 or bank 2. Directly ad-
dressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of BP.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
Accumulator -ACC
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit -ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
·Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·Logic operations (AND, OR, XOR, CPL)
·Rotation (RL, RR, RLC, RRC)
·Increment and Decrement (INC, DEC)
·Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register -STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clear-
ing the Watchdog Timer and executing the ²HALT²in-
struction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Bit No. Label Function
0C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
1AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4 PDF PDF is cleared by either a system power-up or executing the ²CLR WDT²instruction. PDF is
set by executing the ²HALT²instruction.
5TO
TO is cleared by a system power-up or executing the ²CLR WDT²or ²HALT²instruction. TO
is set by a WDT time-out.
6, 7 ¾Unused bit, read as ²0²
Status (0AH) Register

HT46R65/HT46C65
Rev. 1.90 11 February 14, 2006
Interrupts
The device provides two external interrupts, two internal
timer/event counter interrupts, an internal time base in-
terrupt, and an internal real time clock interrupt. The in-
terrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the pro-
gram counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
External interrupts are triggered by a an edge transition
of INT0 or INT1 (ROM code option: high to low, low to
high, low to high or high to low), and the related interrupt
request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0)
is set as well. After the interrupt is enabled, the stack is
not full, and the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The interrupt request
flag (EIF0 or EIF1) and EMI bits are all cleared to disable
other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 6 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 4 of
INTC1) and its subroutine call location is 10H.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
Bit No. Label Function
0 EMI Control the master (global) interrupt (1=enabled; 0=disabled)
1 EEI0 Control the external interrupt 0 (1=enabled; 0=disabled)
2 EEI1 Control the external interrupt 1 (1=enabled; 0=disabled)
3 ET0I Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
4 EIF0 External interrupt 0 request flag (1=active; 0=inactive)
5 EIF1 External interrupt 1 request flag (1=active; 0=inactive)
6 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
7¾For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No. Label Function
0 ET1I Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
1 ETBI Control the time base interrupt (1=enabled; 0:disabled)
2 ERTI Control the real time clock interrupt (1=enabled; 0:disabled)
3, 7 ¾Unused bit, read as ²0²
4 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
5 TBF Time base request flag (1=active; 0=inactive)
6 RTF Real time clock request flag (1=active; 0=inactive)
INTC1 (1EH) Register

HT46R65/HT46C65
Rev. 1.90 12 February 14, 2006
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC1), that is caused by a regular real time clock sig-
nal. After the interrupt is enabled, and the stack is not
full, and the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag (RTF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI²instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI²may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source Priority Vector
External interrupt 0 1 04H
External interrupt 1 2 08H
Timer/Event Counter 0 overflow 3 0CH
Timer/Event Counter 1 overflow 4 10H
Time base interrupt 5 14H
Real time clock interrupt 6 18H
The Timer/Event Counter 0 interrupt request flag (T0F),
external interrupt 1 request flag (EIF1), external inter-
rupt 0 request flag (EIF0), enable Timer/Event Counter
0 interrupt bit (ET0I), enable external interrupt 1 bit
(EEI1), enable external interrupt 0 bit (EEI0), and en-
able master interrupt bit (EMI) make up of the Interrupt
Control register 0 (INTC0) which is located at 0BH in the
RAM. The real time clock interrupt request flag (RTF),
time base interrupt request flag (TBF), Timer/Event
Counter 1 interrupt request flag (T1F), enable real time
clock interrupt bit (ERTI), and enable time base interrupt
bit (ETBI), enable Timer/Event Counter 1 interrupt bit
(ET1I) on the other hand, constitute the Interrupt Control
register 1 (INTC1) which is located at 1EH in the RAM.
EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (RTF, TBF, T0F,
T1F, EIF1, EIF0) are all set, they remain in the INTC1 or
INTC0 respectively until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program should not use the
²CALL subroutine²within the interrupt subroutine. It¢sbe
-
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of the
²call²in the interrupt subroutine may damage the origi-
nal control sequence.
Oscillator Configuration
The device provides three oscillator circuits for system
clocks, i.e., RC oscillator, crystal oscillator and 32768Hz
crystal oscillator, determined by options. No matter what
type of oscillator is selected, the signal is used for the
system clock. The HALT mode stops the system oscilla-
tor (RC and crystal oscillator only) and ignores external
signal in order to conserve power. The 32768Hz crystal
oscillator still runs at HALT mode. If the 32768Hz crystal
oscillator is selected as the system oscillator, the system
oscillator is not stopped; but the instruction execution is
stopped. Since the 32768Hz oscillator is also designed
for timing purposes, the internal timing (RTC, time base,
WDT) operation still runs even if the system enters the
HALT mode.
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and VSS is required,
and the range of the resistance should be from 30kWto
750kW. The system clock, divided by 4, is available on
OSC2 with pull-high resistor, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature, and the
chip itself due to process variations. It is therefore, not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
C r y s t a l O s c i l l a t o r
O S C 2
O S C 1
3 2 7 6 8 H z C r y s t a l / R T C O s c i l l a t o r
O S C 3
O S C 4
R C O s c i l l a t o r
O S C 1
O S C 2
fS Y S / 4
V
D D
470pF
System Oscillator
Note: 32768Hz crystal enable condition: For WDT clock source or for system clock source.
The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to pro-
vide oscillation. For applications where precise RTC frequencies are essential, these components may be re-
quired to provide frequency compensation due to different crystal manufacturing tolerances.

HT46R65/HT46C65
Rev. 1.90 13 February 14, 2006
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscil-
lator can be applied. The crystal should be connected
between OSC3 and OSC4.
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the ²QOSC²bit (bit 4 of RTCC). It is
recommended to turn on the quick oscillating function
upon power on, and then turn it off after 2 seconds.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Although
the system enters the power down mode, the system
clock stops, and the WDT oscillator still works with a pe-
riod of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer -WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
Once an internal WDT oscillator (RC oscillator with pe-
riod 65ms at 5V normally) is selected, it is divided by
212~215 (by ROM code option to get the WDT time-out
period). The minimum period of WDT time-out period is
about 300ms~600ms. This time-out period may vary
with temperature, VDD and process variations. By se-
lection the WDT ROM code option, longer time-out peri-
ods can be realized. If the WDT time-out is selected 215,
the maximum time-out period is divided by 215~216about
2.1s~4.3s. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ate in the same manner except that in the halt state the
WDT may stop counting and lose its protecting purpose.
In this situation the logic can only be restarted by exter-
nal logic. If the device operates in a noisy environment,
using the on-chip RC oscillator (WDT OSC) is strongly
recommended, since the HALT will stop the system
clock.
The WDT overflow under normal operation initializes a
²chip reset²and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), soft-
ware instruction, and a ²HALT²instruction. There are
two types of software instructions; ²CLR WDT²and the
other set -²CLR WDT1²and ²CLR WDT2². Of these
two types of instruction, only one type of instruction can
be active at a time depending on the options -²CLR
WDT²times selection option. If the ²CLR WDT²is se-
lected (i.e., CLR WDT times equal one), any execution
of the ²CLR WDT²instruction clears the WDT. In the
case that ²CLR WDT1²and ²CLR WDT2²are chosen
(i.e., CLR WDT times equal two), these two instructions
have to be executed to clear the WDT; otherwise, the
WDT may reset the chip due to time-out.
Multi-function Timer
The HT46R65/HT46C65 provides a multi-function timer
for the WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of an
8-stage divider and a 7-bit prescaler, with the clock
source coming from the WDT OSC or RTC OSC or the
instruction clock (i.e., system clock divided by 4). The
multi-function timer also provides a selectable fre-
quency signal (ranges from fS/22to fS/28) for LCD driver
circuits, and a selectable frequency signal (ranging from
fS/22to fS/29) for the buzzer output by options. It is rec-
ommended to select a nearly 4kHz signal for the LCD
driver circuits to have proper display.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 212/fSto 215/fSselected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 14H occurs.
T i m e - o u t R e s e t
2
1 5
/ f
S
~ 2
1 6
/ f
S
2
1 4
/ f
S
~ 2
1 5
/ f
S
2
1 3
/ f
S
~ 2
1 4
/ f
S
2
1 2
/ f
S
~ 2
1 3
/ f
S
S y s t e m C l o c k / 4
D i v i d e r
W D T C l e a r
R O M
C o d e
O p t i o n
W D T
O S C
1 2 k H z
R T C
O S C
32768H z
C K T
R
C K T
R
f
S
W D T
P r e s c a l e r
M a s k O p t i o n
fS/ 2 8
Watchdog Timer

HT46R65/HT46C65
Rev. 1.90 14 February 14, 2006
Real Time Clock -RTC
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular in-
ternal interrupt. Its time-out period ranges from fS/28to
fS/215 by software programming . Writing data to RT2,
RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a sub-
routine call to location 18H occurs.
RT2 RT1 RT0 RTC Clock Divided Factor
000 2
8*
001 2
9*
010 2
10*
011 2
11*
100 2
12
101 2
13
110 2
14
111 2
15
Note: * not recommended to be used
Power Down Operation -HALT
The HALT mode is initialized by the ²HALT²instruction
and results in the following.
·The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
·The contents of the on-chip RAM and of the registers
remain unchanged.
·The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
·All I/O ports maintain their original status.
·The PDF flag is set but the TO flag is cleared.
·LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a ²warm reset².
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared
by system power-up or by executing the ²CLR WDT²in-
struction, and is set by executing the ²HALT²instruction.
On the other hand, the TO flag is set if WDT time-out oc-
curs, and causes a wake-up that only resets the pro-
gram counter and SP, and leaves the others at their
original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place.
When an interrupt request flag is set before entering the
²HALT²status, the system cannot be awakened using
that interrupt.
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
D i v i d e r
f
S
8 t o 1
M u x .
P r e s c a l e r
R T 2
R T 1
R T 0 R T C I n t e r r u p t
28/ f S~ 2 1 5 / f S
Real Time Clock
f s
D i v i d e r P r e s c a l e r
R O M C o d e O p t i o n
L C D D r i v e r ( f S/ 2 2~ f S/ 2 8)
B u z z e r ( f S/ 2 2~ f S/ 2 9)
T i m e B a s e I n t e r r u p t
21 2 / f S~ 2 1 5 / f S
R O M
C o d e
O p t i o n
Time Base

HT46R65/HT46C65
Rev. 1.90 15 February 14, 2006
Reset
There are three ways in which reset may occur.
·RES is reset during normal operation
·RES is reset during HALT
·WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset²that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition²once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
TO PDF RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u²stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Program Counter 000H
Interrupt Disabled
Prescaler, Divider Cleared
WDT, RTC,
Time Base
Cleared. After master reset,
WDT starts counting
Timer/event Counter Off
Input/output Ports Input mode
Stack Pointer Points to the top of the stack
R E S
V
D D
1 0 0 k W
1 0 k W
0 . 1 mF *
0 . 0 1 mF *
Reset Circuit
Note: ²*²Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
R E S
V D D
S S T T i m e - o u t
C h i p R e s e t
tS S T + t O P D
Reset Timing Chart
W D T
H A L T
W D T
T i m e - o u t
R e s e t
E x t e r n a l
R E S
C o l d
R e s e t
P o w e r - o n D e t e c t i o n
S S T
1 0 - b i t R i p p l e
C o u n t e r
O S C 1
W a r m R e s e t
Reset Configuration

HT46R65/HT46C65
Rev. 1.90 16 February 14, 2006
The register states are summarized below:
Register Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
BP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Program
Counter 0000H 0000H 0000H 0000H 0000H
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
RTCC --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
TMR0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMR1C 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
PWM2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
PWM3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu
ADRL xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ----
ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu
ACSR 1--- --00 1--- --00 1--- --00 ---- --00 u--- --uu
Note: ²*²stands for warm reset
²u²stands for unchanged
²x²stands for unknown

HT46R65/HT46C65
Rev. 1.90 17 February 14, 2006
Timer/Event Counter
Two timer/event counters (TMR0,TMR1) are imple-
mented in the microcontroller. The Timer/Event Counter
0 contains a 16-bit programmable count-up counter and
the clock may come from an external source or an inter-
nal clock source. An internal clock source comes from
fSYS. The Timer/Event Counter 1 contains a 16-bit pro-
grammable count-up counter and the clock may come
from an external source or an internal clock source. An
internal clock source comes from fSYS/4 or 32768Hz se-
lected by option. The external clock input allows the
user to count external events, measure time intervals or
pulse widths, or to generate an accurate time base.
There are six registers related to the Timer/Event Coun-
ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and
the Timer/Event Counter 1; TMR1H (0FH), TMR1L
(10H), TMR1C (11H). Writing TMR0L (TMR1L) will only
put the written data to an internal lower-order byte buffer
(8-bit) and writing TMR0H (TMR1H) will transfer the
specified data and the contents of the lower-order byte
buffer to TMR0H (TMR1H) and TMR0L (TMR1L) regis-
ters, respectively. The Timer/Event Counter 1/0 preload
register is changed by each writing TMR0H (TMR1H)
operations. Reading TMR0H (TMR1H) will latch the
contents of TMR0H (TMR1H) and TMR0L (TMR1L)
counters to the destination and the lower-order byte
buffer, respectively. Reading the TMR0L (TMR1L) will
read the contents of the lower-order byte buffer. The
TMR0C (TMR1C) is the Timer/Event Counter 0 (1) con-
trol register, which defines the operating mode, counting
enable or disable and an active edge.
The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)
bits define the operation mode. The event count mode is
used to count external events, which means that the
clock source is from an external (TMR0, TMR1) pin. The
timer mode functions as a normal timer with the clock
source coming from the internal selected clock source.
Finally, the pulse width measurement mode can be used
to count the high or low level duration of the external sig-
nal (TMR0, TMR1), and the counting is based on the in-
ternal selected clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFFFH. Once an over-
T 0 M 1
T 0 M 0
T M R 0
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
8 - s t a g e P r e s c a l e r
8 - 1 M X
fS Y S
fI N T
T 0 P S C 2 ~ T 0 P S C 0
( 6 + 2 ) o r ( 7 + 1 )
C o m p a r e
P W M
T o P D 0 / P D 1 / P D 2 / P D 3 c i r c u i t
1 6 - B i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w t o I n t e r r u p t
L o w B y t e
B u f f e r
H i g h B y t e L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
P F D 0
Timer/Event Counter 0
T 1 M 1
T 1 M 0
T M R 1
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
P u l s e W i d t h
M e a s u r e m e n t
M o d e C o n t r o l
fI N T
fS Y S / 4
32768H z
T 1 S
MX
1 6 - B i t
P r e l o a d R e g i s t e r
D a t a B u s
R e l o a d
O v e r f l o w t o I n t e r r u p t
L o w B y t e
B u f f e r
H i g h B y t e L o w B y t e
1 6 - B i t T i m e r / E v e n t C o u n t e r
P F D 1
Timer/Event Counter 1
M
X
1 / 2 P F D
P F D S o u r c e O p t i o n
P A 3 D a t a C T R L
P F D 0
P F D 1
PFD Source Option

HT46R65/HT46C65
Rev. 1.90 18 February 14, 2006
flow occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In
the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to 1, after the
TMR0 (TMR1) has received a transient from low to high
(or high to low if the T0E/T1E bit is ²0²), it will start count-
ing until the TMR0 (TMR1) returns to the original level
and resets the T0ON/T1ON. The measured result re-
mains in the timer/event counter even if the activated
transient occurs again. In other words, only 1-cycle
measurement can be made until the T0ON/T1ON is set.
The cycle measurement will re-function as long as it re-
ceives further transient pulse. In this operation mode,
the timer/event counter begins counting not according
to the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt re-
quest, as in the other two modes, i.e., event and timer
modes.
Bit No. Label Function
0
1
2
T0PSC0
T0PSC1
T0PSC2
To define the prescaler stages.
T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3 T0E
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4 T0ON Enable/disable timer counting (0=disabled; 1=enabled)
5¾Unused bit, read as ²0²
6
7
T0M0
T0M1
Defines the operating mode T0M1, T0M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR0C (0EH) Register
Bit No. Label Function
0~2 ¾Unused bit, read as ²0²
3 T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4 T1ON Enable/disable timer counting (0= disabled; 1= enabled)
5 T1S Defines the TMR1 internal clock source (0=fSYS/4; 1=32768Hz)
6
7
T1M0
T1M1
Defines the operating mode T1M1, T1M0=
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register

HT46R65/HT46C65
Rev. 1.90 19 February 14, 2006
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of TMR0C; T1ON: 4 bit of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON/T1ON is automatically cleared after the measure-
ment cycle is completed. But in the other two modes, the
T0ON/T1ON can only be reset by instructions. The
overflow of the Timer/Event Counter 0/1 is one of the
wake-up sources and can also be applied to a PFD (Pro-
grammable Frequency Divider) output at PA3 by op-
tions. Only one PFD (PFD0 or PFD1) can be applied to
PA3 by options. If PA3 is set as PFD output, there are
two types of selections; One is PFD0 as the PFD output,
the other is PFD1 as the PFD output. PFD0, PFD1 are
the timer overflow signals of the Timer/Event Counter 0,
Timer/Event Counter 1 respectively. No matter what the
operation mode is, writinga0toET0I or ET1I disables
the related interrupt service. When the PFD function is
selected, executing ²SET [PA].3²instruction to enable
PFD output and executing ²CLR [PA].3²instruction to
disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may re-
sults in a counting error. Blocking of the clock should be
taken into account by the programmer. It is strongly rec-
ommended to load a desired value into the TMR0/TMR1
register first, before turning on the related timer/event
counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event coun-
ter scheme, the programmer should pay special atten-
tion on the instruction to enable then disable the timer
for the first time, whenever there is a need to use the
timer/event counter function, to avoid unpredictable re-
sult. After this procedure, the timer/event function can
be operated normally.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal. The timer prescaler is also
used as the PWM counter.
Input/Output Ports
There are 24 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PD, which are
mapped to the data memory of [12H], [14H] and [18H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]²(m=12H, 14H
or 18H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt Trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the inter-
nal bus. The latter is possible in the ²read-modify-write²
instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i²and ²CLR [m].i²(m=12H, 14H or
18H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i²,²CLR
[m].i²,²CPL [m]²,²CPLA [m]²read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always retain
its original functions. Once the PFD option is selected,
the PFD output signal is controlled by PA3 data register
only. Writing ²1²to PA3 data register will enable the PFD
output function and writing 0 will force the PA3 to remain
at ²0². The I/O functions of PA3 are shown below.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
PA3 Logical
Input
Logical
Output
Logical
Input
PFD
(Timer on)
Note: The PFD frequency is the timer/event counter
overflowfrequencydivided by2.
The PA0, PA1, PA3, PD4, PD5, PD6 and PD7 are
pin-shared with BZ, BZ, PFD, INT0, INT1, TMR0 and
TMR1 pins respectively.

HT46R65/HT46C65
Rev. 1.90 20 February 14, 2006
The PA0 and PA1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PA0/PA1 will be the buzzer sig-
nal generated by multi-function timer. The input mode
always remain in its original function. Once the BZ/BZ
option is selected, the buzzer output signal are con-
trolled by the PA0/PA1 data register only.
The I/O function of PA0/PA1 are shown below.
PA0I/O I I OOOOOOOO
PA1I/O I O I I I OOOOO
PA0 Mode X X C B B C BBBB
PA1 Mode X C X X X C C C B B
PA0 Data X X D 0 1 D00101
PA1 Data X D X X X D1 D D X X
PA0 Pad Status I I D 0 B D00B0B
PA1 Pad Status I D I I I D1DD0 B
Note: ²I²input; ²O²output
²D, D0, D1²Data
²B²buzzer option, BZ or BZ
²X²don¢t care
²C²CMOS output
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). Writing ²1²to
PD0~PD3 data register will enable the PWM output
function and writing ²0²will force the PD0~PD3 to re-
main at ²0². The I/O functions of PD0/PD1/PD2/PD3 are
as shown.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0~
PD3
Logical
Input
Logical
Output
Logical
Input
PWM0~
PWM3
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3 Pad
State
PFD
Frequency
OFF X 0 0 X
OFF X 1 U X
ON N 0 0 X
ON N 1 PFD fTMR/[2´(M-N)]
Note: ²X²stands for unused
²U²stands for unknown
²M²is ²65536²for PFD0 or PFD1
²N²is preload value for timer/event counter
²fTMR²is input clock frequency for timer/event
counter
VD D
M
X
M
X
P F D E N
( P A 3 )
W a k e - u p O p t i o n s
I N T 0 f o r P D 4 o n l y
I N T 1 f o r P D 5 o n l y
T M R 0 f o r P D 6 o n l y
T M R 1 f o r P D 7 o n l y
S y s t e m W a k e - u p
( P A o n l y )
R e a d D a t a R e g i s t e r
P A 0 / P A 1 / P A 3 / P D 0 / P D 1 / P D 2 / P D 3
DQ
C K
S
DQ
C K Q
S
C o n t r o l B i t P u l l - h i g h
O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P A 0 / B Z
P A 1 / B Z
P A 2
P A 3 / P F D
P A 4 ~ P A 7
P B 0 / A N 0 ~ P B 7 / A N 7
P D 0 / P W M 0
P D 1 / P W M 1
P D 2 / P W M 2
P D 3 / P W M 3
P D 4 / I N T 0
P D 5 / I N T 1
P D 6 / T M R 0
P D 7 / T M R 1
Q
B Z / B Z / P F D / P W M 0 / P W M 1 / P W M 2 / P W M 3
Input/Output Ports