Holtek HT48R05A-1 User manual

HT48R05A-1, HT48R06A-1, HT48R07A-1,
HT48R08A-1, HT48R09A-1
Cost-Effective I/O Type MCU
Handbook
Second Edition
June 2006
Copyright Ó2006 by HOLTEK SEMICONDUCTOR INC. All rights reserved. Printed in Taiwan. No part of this publication
may be reproduced, stored in a retrieval system, or transmitted in any form by any means, electronic, mechanical photo-
copying, recording, or otherwise without the prior written permission of HOLTEK SEMICONDUCTOR INC.

Contents
Part I Microcontroller Profile....................................................................1
Chapter 1 Hardware Structure ...........................................................................................3
Introduction......................................................................................................................3
Features...........................................................................................................................4
Technology Features.................................................................................................4
Kernel Features.........................................................................................................4
Peripheral Features...................................................................................................4
Selection Table ................................................................................................................5
Block Diagram .................................................................................................................5
Pin Assignment................................................................................................................6
Pin Description.................................................................................................................6
Absolute Maximum Ratings .............................................................................................8
D.C. Characteristics.........................................................................................................9
A.C. Characteristics .......................................................................................................10
System Architecture.......................................................................................................11
Clocking and Pipelining ...........................................................................................11
Program Counter.....................................................................................................12
Stack .......................................................................................................................13
Arithmetic and Logic Unit -ALU .............................................................................14
Program Memory ...........................................................................................................14
Organization............................................................................................................14
Special Vectors .......................................................................................................15
Look-up Table..........................................................................................................15
Table Program Example..........................................................................................16
Data Memory .................................................................................................................17
Organization............................................................................................................17
General Purpose Data Memory ..............................................................................18
Special Purpose Data Memory ...............................................................................18
Contents
i

Special Function Registers ............................................................................................19
Indirect Addressing Register -IAR .........................................................................19
Memory Pointer -MP..............................................................................................19
Accumulator -ACC.................................................................................................20
Program Counter Low Register -PCL ...................................................................20
Look-up Table Registers -TBLP, TBLH .................................................................20
Watchdog Timer Register -WDTS .........................................................................20
Status Register -STATUS ......................................................................................21
Interrupt Control Register -INTC ...........................................................................22
Timer/Event Counter Registers ...............................................................................22
Input/Output Ports and Control Registers ...............................................................22
Input/Output Ports .........................................................................................................23
Pull-high Resistors ..................................................................................................23
Port A Wake-up .......................................................................................................23
I/O Port Control Registers .......................................................................................23
Pin-shared Functions ..............................................................................................24
Programming Considerations .................................................................................26
Timer/Event Counters ....................................................................................................26
Configuring the Timer/Event Counter Input Clock Source ......................................26
Timer Register -TMR ............................................................................................27
Timer Control Register -TMRC ..............................................................................27
Configuring the Timer Mode ...................................................................................28
Configuring the Event Counter Mode .....................................................................29
Configuring the Pulse Width Measurement Mode ..................................................29
Programmable Frequency Divider (PFD) and Buzzer Application ..........................30
Prescaler .................................................................................................................31
I/O Interfacing .........................................................................................................31
Programming Considerations .................................................................................31
Interrupts .......................................................................................................................32
Interrupt Register ....................................................................................................32
Interrupt Priority .......................................................................................................33
External Interrupt ....................................................................................................33
Timer/Event Counter Interrupt ................................................................................33
Programming Considerations .................................................................................33
Reset and Initialization ..................................................................................................34
Reset ......................................................................................................................34
Oscillator .......................................................................................................................38
System Clock Configurations .................................................................................38
System Crystal/Ceramic Oscillator .........................................................................38
System RC Oscillator .............................................................................................39
Watchdog Timer Oscillator .....................................................................................39
Power Down Mode and Wake-up .................................................................................39
Power Down Mode .................................................................................................39
Entering the Power Down Mode .............................................................................39
Standby Current Considerations .............................................................................40
Wake-up ..................................................................................................................40
ii
Cost-Effective I/O Type MCU

Watchdog Timer.............................................................................................................41
Configuration Options....................................................................................................43
Application Circuits ........................................................................................................44
Part II Programming Language...............................................................45
Chapter 2 Instruction Set Introduction ...........................................................................47
Instruction Set................................................................................................................47
Instruction Timing ....................................................................................................47
Moving and Transferring Data.................................................................................47
Arithmetic Operations..............................................................................................48
Logical and Rotate Operations................................................................................48
Branches and Control Transfer ...............................................................................48
Bit Operations .........................................................................................................48
Table Read Operations ...........................................................................................49
Other Operations.....................................................................................................49
Instruction Set Summary ...............................................................................................49
Convention ..............................................................................................................49
Chapter 3 Instruction Definition ......................................................................................53
Chapter 4 Assembly Language and Cross Assembler..................................................65
Notational Conventions..................................................................................................65
Statement Syntax ..........................................................................................................66
Name.......................................................................................................................66
Operation ................................................................................................................66
Operand ..................................................................................................................66
Comment.................................................................................................................67
Assembly Directives ......................................................................................................67
Conditional Assembly Directives.............................................................................67
File Control Directives .............................................................................................68
Program Directives..................................................................................................69
Data Definition Directives........................................................................................72
Macro Directives .....................................................................................................74
Assembly Instructions....................................................................................................76
Name.......................................................................................................................76
Mnemonic................................................................................................................76
Operand, Operator and Expression ........................................................................76
Miscellaneous................................................................................................................78
Forward References................................................................................................78
Local Labels ............................................................................................................78
Reserved Assembly Language Words....................................................................79
Contents
iii

Cross Assembler Options ..............................................................................................80
Assembly Listing File Format.........................................................................................80
Source Program Listing...........................................................................................80
Summary of Assembly ............................................................................................81
Miscellaneous .........................................................................................................81
Part III Development Tools ......................................................................83
Chapter 5 MCU Programming Tools................................................................................85
HT-IDE Development Environment................................................................................85
Holtek In-Circuit Emulator -HT-ICE ..............................................................................86
HT-ICE Interface Card.............................................................................................86
OTP Programmer....................................................................................................87
OTP Adapter Card ..................................................................................................87
System Configuration ....................................................................................................87
HT-ICE Interface Card Settings...............................................................................88
Installation......................................................................................................................89
System Requirement...............................................................................................89
Hardware Installation ..............................................................................................89
Software Installation................................................................................................89
Chapter 6 Quick Start .......................................................................................................95
Step 1 -Create a New Project................................................................................95
Step 2 -Add Source Program Files to the Project .................................................95
Step 3 -Build the Project........................................................................................95
Step 4 -Programming the OTP Device..................................................................95
Step 5 -Transmit Code to Holtek ...........................................................................96
Appendix.....................................................................................................97
Appendix A Device Characteristic Graphics ..................................................................99
Appendix B Package Information.................................................................................109
iv
Cost-Effective I/O Type MCU

Preface
Since the founding of the company, Holtek Semiconductor Inc. has concentrated much of its de-
sign efforts in the area of microcontroller development. Although supplying a wide range of semi-
conductor devices, the microcontroller category has always been a key product category within
the Holtek range, and one which will continue to expand as their devices increase in functionality
and maturity. By capitalizing on the substantial accumulated skills within its dedicated
microcontroller development department, Holtek has been able to release a comprehensive
range of high quality low-cost microcontroller devices for a wide range of application areas.
Holtek¢s high quality embedded I/O microcontroller solutions provide a means for customers to
greatly enhance the functional contents of their products, which when combined with Holtek¢s com-
prehensive range of development tools provide designers with the means to reduce their design to
market times and greatly increasing their added value.
This handbook is divided into three parts for user convenience. Most details regarding general
datasheet information and device specification is located within Part I. Information related to
microcontroller programming such as device instruction set, instruction definition, and assembly
language directives is found within Part II. Part III relates to the Holtek range of Development Tools
where information can be found on their installation and use.
By compiling all relevant data together in one handbook we hope users of the Holtek range of
Cost-Effective I/O Type microcontroller devices will have at their fingertips a useful, complete and
simple means to efficiently implement their microcontroller applications. Holtek¢s efforts to com-
bine information on device specifications, programming and development tools into one publica-
tion have produced a handbook which with careful use by the user should result in trouble free
designs and the maximum benefit being gained from the many features of Holtek microcontroller
devices. We recommend that users regularly check our website for the latest updates to our hand-
book and also welcome feedback and comments from our customers regarding further improve-
ments.
Preface
v

vi
Cost-Effective I/O Type MCU

Part I
Microcontroller Profile
Part I Microcontroller Profile
1

2
Cost-Effective I/O Type MCU

Chapter 1
Hardware Structure
This section is the main datasheet section of the Cost-Effective I/O Type microcontroller hand-
book and contains all the parameters and information related to the hardware. The information
contained provides designers with details on all the main hardware features of the Cost-Effective
I/O Type MCU series which together with the programming section contains the information to en-
able swift and successful implementation of user microcontroller applications. By proper consulta-
tion of the relevant parts of this section, users can ensure that they make the most efficient use of
the flexible and multi-function features within the Cost-Effective I/O Type microcontroller series.
Introduction
The HT48R05A-1/HT48C05, HT48R06A-1/HT48C06, HT48R07A-1/HT48C07, HT48R08A-1/
HT48C08 and HT48R09A-1/HT48C09 are 8-bit high performance, cost-effective RISC architec-
ture microcontroller devices specifically designed for multiple I/O control product applications. De-
vice flexibility is enhanced with their internal special features such as HALT and wake-up
functions, oscillator options, buzzer driver, etc. These features combine to ensure applications re-
quire a minimum of external components and therefore reduce overall product costs. Having the
advantages of low power consumption, high performance, I/O flexibility as well as low-cost, these
devices have the versatility to suit a wide range of application possibilities such as industrial con-
trol, consumer products, subsystem controllers, etc. All devices share the same functions and fea-
tures, their main difference is in Data Memory and Program Memory capacity.
The HT48R05A-1, HT48R06A-1, HT48R07A-1, HT48R08A-1 and HT48R09A-1 are OTP devices
offering the advantages of easy and effective program updates, using the Holtek range of develop-
ment and programming tools. These devices provide the designer with the means for fast and cost
effective product development cycles. However, for applications that are at a mature state in their
design process, the HT48C05, HT48C06, HT48C07, HT48C08 and HT48C09 mask version de-
vices offer a complementary device for products with high volume and low-cost demands. Fully
pin and functionally compatible with their OTP version devices, such mask version devices pro-
vide the ideal substitute for products which have gone beyond their development cycle and are fac-
ing cost down demands.
Chapter 1 Hardware Structure
3
1

Features
Technology Features
·High-performance RISC Architecture
·Low-power Fully Static CMOS Design
·Operating Voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
·Power Consumption:
2mA Typical at 5V 4MHz
Maximum of 1mA Standby Current at 3V with WDT Disabled
·Temperature Range:
Operating Temperature -40°Cto85°C (Industrial Grade)
Storage Temperature -50°Cto125°C
Kernel Features
·Program Memory:
0.5K´14 OTP/Mask ROM (HT48R05A-1/HT48C05)
1K´14 OTP/Mask ROM (HT48R06A-1/HT48C06, HT48R07A-1/HT48C07)
2K´14 OTP/Mask ROM (HT48R08A-1/HT48C08, HT48R09A-1/HT48C09)
·Data Memory:
32´8 RAM (HT48R05A-1/HT48C05)
64´8 RAM (HT48R06A-1/HT48C06, HT48R07A-1/HT48C07)
96´8 RAM (HT48R08A-1/HT48C08, HT48R09A-1/HT48C09)
·Table Read Function
·Two-level Hardware Stack
·Direct and Indirect Data Addressing Mode
·Bit Manipulation Instructions
·63 Powerful Instructions
·Most Instructions Implemented in 1 Machine Cycle
Peripheral Features
·From 13 to 19 Bidirectional I/O with Pull-high Options
·Port A Wake-up Options
·External Interrupt Input
·Event Counter Input
·8-bit Timer with 8-stage Prescaler and Interrupt
·Watchdog Timer (WDT)
·HALT and Wake-up Feature for Power Saving Operation
·PFD/Buzzer Driver Outputs
·On-chip Crystal and RC Oscillator
·Low Voltage Reset (LVR) Feature for Brown-out Protection
·Programming Interface with Code Protection
·Mask Version Devices Available for High-volume Production
·Full Suite of Supported Hardware and Software Tools Available
4
Cost-Effective I/O Type MCU

Selection Table
The series of Cost-Effective I/O microcontrollers include a comprehensive range of features,
some of which are standard and some of which are device dependent. Most features are common
to all devices, the main feature distinguishing them are Program Memory, Data Memory capacity
and I/O count. To assist users in their selection of the most appropriate device for their application,
the following table, which summarizes the main features of each device, is provided.
Part No. VDD Program
Memory
Data
Memory I/O Timer Int. PFD Stack Package
Types
HT48R05A-1
HT48C05 2.2V~5.5V 0.5K´14 32´813 8-bit´12Ö216SSOP,
18DIP/SOP
HT48R06A-1
HT48C06 2.2V~5.5V 1K´14 64´813 8-bit´12Ö216SSOP,
18DIP/SOP
HT48R07A-1
HT48C07 2.2V~5.5V 1K´14 64´819 8-bit´12Ö224SKDIP/
SOP/SSOP
HT48R08A-1
HT48C08 2.2V~5.5V 2K´14 96´813 8-bit´12Ö216SSOP,
18DIP/SOP
HT48R09A-1
HT48C09 2.2V~5.5V 2K´14 96´819 8-bit´12Ö224SKDIP/
SOP/SSOP
Note 1. Part numbers including ²C²are mask version devices while ²R²are OTP devices.
2. There is a Low Voltage Reset within the range 2.7V~3.3V, if the LVR function is disabled,
the operating voltage can be reduced to 2.2V.
Block Diagram
The following block diagram illustrates the main functional blocks of the Cost-Effective I/O Type
microcontroller series of devices.
Note This block diagram represents the OTP devices, for the mask device there is no Device Pro-
gramming Circuitry.
Chapter 1 Hardware Structure
5
T i m i n g
G e n e r a t o r
S y s t e m R C /
X ' t a l O s c i l l a t o r I n s t r u c t i o n
D ecoder
I n s t r u c t i o n
R e g i s t e r
W D T
O s c i l l a t o r
D a t a
M e m o r y
A d d r e s s D e c o d e r
M e m o r y
P o i n t e r
M X A C C
Look-up
T a b l e
R e g i s t e r
C o n f i g .
R e g i s t e r
W a t c h d o g
T i m e r
R e s e t &
L V R
C o n f i g .
R e g i s t e r
T i m e r /
C o u n t e r
B u z z e r
D r i v e r
C o n f i g .
R e g i s t e r
I n t e r r u p t
C i r c u i t
C o n f i g .
R e g i s t e r
I/O
P o r t s
D e v i c e
P r o g r a m m i n g
C i r c u i t r y
C o n f i g u r a t i o n
O p t i o n
P r o g r a m
M e m o r y
A d d r e s s D e c o d e r
S t a c k
S t a c k P o i n t e r
P r o g r a m
C o u n t e r
Look-up
T a b l e
P o i n t e r
T o P r o g r a m
M e m o r y
A L
S h i f t e r
MX

Pin Assignment
Pin Description
HT48R05A-1/HT48C05, HT48R06A-1/HT48C06
Pin Name I/O Options Description
PA0~PA7 I/O Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each individual bit on this port
can be configured as a wake-up input by a configuration option.
Software instructions determine if the pin is a CMOS output or
Schmitt Trigger input. A configuration option determines if all pins
on all ports have pull-high resistors.
PB0/BZ
PB1/BZ
PB2
I/O Pull-high
I/O or BZ/BZ
Bidirectional 3-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. A configuration
option determines if all pins on all ports have pull-high resistors.
PB0 and PB1 are pin-shared with BZ and BZ, respectively.
PC0/INT
PC1/TMR I/O Pull-high
Bidirectional 2-bit input/output port. Software instructions deter-
mine if the pin is a CMOS output or Schmitt Trigger input. A config-
uration option determines if all pins on all ports have pull-high
resistors. The external interrupt and timer input are pin-shared
with PC0 and PC1, respectively.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external
crystal (determined by configuration option) for the internal system
clock. For external RC system clock operation, OSC2 is an output
pin for 1/4 system clock.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
6
Cost-Effective I/O Type MCU
H T 4 8 R 0 7 A - 1 / H T 4 8 C 0 7
H T 4 8 R 0 9 A - 1 / H T 4 8 C 0 9
2 4 S K D I P - A / S O P - A / S S O P - A
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
H T 4 8 R 0 5 A - 1 / H T 4 8 C 0 5
H T 4 8 R 0 6 A - 1 / H T 4 8 C 0 6
H T 4 8 R 0 8 A - 1 / H T 4 8 C 0 8
1 6 S S O P - A
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P A 3
P A 2
P A 1
P A 0
P B 0 / B Z
V S S
P C 0 / I N T
P C 1 / T M R
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 1 / T M R
H T 4 8 R 0 5 A - 1 / H T 4 8 C 0 5
H T 4 8 R 0 6 A - 1 / H T 4 8 C 0 6
H T 4 8 R 0 8 A - 1 / H T 4 8 C 0 8
1 8 D I P - A / S O P - A
P A 3
P A 2
P A 1
P A 0
P B 2
P B 1 / B Z
P B 0 / B Z
V S S
P C 0 / I N T
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
1
2
3
4
5
6
7
8
9
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P A 3
P A 2
P A 1
P A 0
P B 2
P B 1 / B Z
P B 0 / B Z
V S S
P C 0 / I N T
P B 3
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 1 / T M R
P C 2
P B 5 P B 6
P B 4 P B 7

Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins or ports cannot be selected to have pull-high resistors. If the pull-high configura-
tion option is chosen, then all input pins of all ports will be connected to pull-high resistors.
3. Pins PB1/BZ and PB2 only exist on the 18-pin package.
HT48R08A-1/HT48C08
Pin Name I/O Options Description
PA0~PA7 I/O Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each individual bit on this port
can be configured as a wake-up input by a configuration option.
Software instructions determine if the pin is a CMOS output or
Schmitt Trigger input. A configuration option determines if all pins
on this port have pull-high resistors.
PB0/BZ
PB1/BZ
PB2
I/O Pull-high
I/O or BZ/BZ
Bidirectional 3-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. A configuration
option determines if all pins on this port have pull-high resistors.
PB0 and PB1 are pin-shared with BZ and BZ, respectively.
PC0/INT
PC1/TMR I/O Pull-high
Bidirectional 2-bit input/output port. Software instructions deter-
mine if the pin is a CMOS output or Schmitt Trigger input. A config-
uration option determines if all pins on this port have pull-high
resistors. The external interrupt and timer input are pin-shared
with PC0 and PC1, respectively.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external
crystal (determined by configuration option) for the internal system
clock. For external RC system clock operation, OSC2 is an output
pin for 1/4 system clock.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is
chosen for a particular port, then all input pins on this port will be connected to pull-high resis-
tors.
3. Pins PB1/BZ and PB2 only exist on the 18-pin package.
Chapter 1 Hardware Structure
7

HT48R07A-1/HT48C07, HT48R09A-1/HT48C09
Pin Name I/O Options Description
PA0~PA7 I/O Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each individual bit on this port
can be configured as a wake-up input by a configuration option.
Software instructions determine if the pin is a CMOS output or
Schmitt Trigger input. A configuration option determines if all pins
on this port have pull-high resistors.
PB0/BZ
PB1/BZ
PB2~PB7
I/O Pull-high
I/O or BZ/BZ
Bidirectional 8-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. A configuration
option determines if all pins on this port have pull-high resistors.
PB0 and PB1 are pin-shared with BZ and BZ, respectively.
PC0/INT
PC1/TMR
PC2
I/O Pull-high
Bidirectional 3-bit input/output port. Software instructions deter-
mine if the pin is a CMOS output or Schmitt Trigger input. A config-
uration option determines if all pins on this port have pull-high
resistors. The external interrupt and timer input are pin-shared
with PC0 and PC1, respectively.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external
crystal (determined by configuration option) for the internal system
clock. For external RC system clock operation, OSC2 is an output
pin for 1/4 system clock.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is
chosen for a particular port, then all input pins on this port will be connected to pull-high resis-
tors.
Absolute Maximum Ratings
Supply Voltage.............................................................................................VSS-0.3V to VSS+6.0V
Input Voltage ...............................................................................................VSS-0.3V to VDD+0.3V
Storage Temperature.............................................................................................-50°Cto125°C
Operating Temperature............................................................................................-40°Cto85°C
These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum
Ratings may cause substantial damage to the device. Functional operation of this device at other
conditions beyond those listed in the specification is not implied and prolonged exposure to ex-
treme conditions may affect device reliability.
8
Cost-Effective I/O Type MCU

D.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾fSYS=4MHz 2.2 ¾5.5 V
¾fSYS=8MHz 3.3 ¾5.5 V
IDD1 Operating Current (Crystal OSC)
3V No load, fSYS=4MHz ¾0.6 1.5 mA
5V ¾24mA
IDD2 Operating Current (RC OSC)
3V No load, fSYS=4MHz ¾0.8 1.5 mA
5V ¾2.5 4 mA
IDD3 Operating Current
(Crystal OSC, RC OSC) 5V No load, fSYS=8MHz ¾48mA
ISTB1 Standby Current (WDT Enabled)
3V
No load, system HALT ¾¾ 5mA
5V ¾¾10 mA
ISTB2 Standby Current (WDT Disabled)
3V
No load, system HALT ¾¾ 1mA
5V ¾¾ 2mA
VIL1 Input Low Voltage for I/O Ports,
TMR and INT ¾¾ 0¾0.3VDD V
VIH1 Input High Voltage for I/O Ports,
TMR and INT ¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.4VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
VLVR Low Voltage Reset ¾LVR enabled 2.7 3 3.3 V
IOL I/O Port Sink Current
3V VOL=0.1VDD 48
¾mA
5V VOL=0.1VDD 10 20 ¾mA
IOH I/O Port Source Current
3V VOH=0.9VDD -2-4¾mA
5V VOH=0.9VDD -5-10 ¾mA
RPH Pull-high Resistance
3V ¾20 60 100 kW
5V ¾10 30 50 kW
Chapter 1 Hardware Structure
9

A.C. Characteristics Ta=25°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD Conditions
fSYS1 System Clock (Crystal OSC) ¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fSYS2 System Clock (RC OSC) ¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fTIMER Timer I/P Frequency (TMR) ¾2.2V~5.5V 0 ¾4000 kHz
¾3.3V~5.5V 0 ¾8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾45 90 180 ms
5V ¾32 65 130 ms
tWDT1 Watchdog Time-out Period (RC) 3V Without WDT prescaler 11 23 46 ms
5V 8 17 33 ms
tWDT2 Watchdog Time-out Period
(System Clock) ¾Without WDT prescaler ¾1024 ¾*tSYS
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Wake-up from HALT ¾1024 ¾*tSYS
tLVR Low Voltage Width to Reset ¾¾ 0.25 1 2 ms
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
*tSYS=1/fSYS1 or 1/fSYS2
10
Cost-Effective I/O Type MCU

System Architecture
A key factor in the high-performance features of the Holtek range of Cost-Effective I/O Type
microcontrollers is attributed to the internal system architecture. The range of devices take advan-
tage of the usual features found within RISC microcontrollers providing increased speed of opera-
tion and enhanced performance. The pipelining scheme is implemented in such a way that
instruction fetching and instruction execution are overlapped, hence instructions are effectively ex-
ecuted in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in
practically all operations of the instruction set. It carries out arithmetic operations, logic operations,
rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by mov-
ing data through the Accumulator and the ALU. Certain internal registers are implemented in the
Data Memory and can be directly or indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external com-
ponents is required to provide a functional I/O control system with maximum reliability and flexibil-
ity. This makes these devices suitable for low-cost, high-volume production for controller
applications requiring from 0.5K up to 2K words of program memory and from 32 to 96 bytes of
data storage.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into
four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at
the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecu-
tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the con-
tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the in-
struction will take one more instruction cycle to execute.
Note When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This
T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
Chapter 1 Hardware Structure
11
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 ) F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C ) F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C P C + 1 P C + 2
O s c i l l a t o r C l o c k
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining

For instructions involving branches, such as jump or call instructions, two machine cycles are re-
quired to complete instruction execution. An extra cycle is required as the program takes one cy-
cle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in tim-
ing sensitive applications.
Program Counter
During program execution, the Program Counter is used to keep track of the address of the next in-
struction to be executed. It is automatically incremented by one each time an instruction is exe-
cuted except for instructions, such as ²JMP²or ²CALL²that demand a jump to a non-consecutive
Program Memory address. For the Cost-Effective I/O series, the Program Counter is 9 bits wide
for the HT48R05A-1/HT48C05, 10 bits wide for HT48R06A-1/HT48C06 and HT48R07A-1/
HT48C07 devices and 11 bits wide for the HT48R08A-1/HT48C08 and HT48R09A-1/HT48C09 de-
vices. However, it must be noted that only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by user.
When executing instructions requiring jumps to non-consecutive addresses, such as a jump in-
struction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the pres-
ent instruction execution, is discarded and a dummy cycle takes its place while the correct instruc-
tion is obtained.
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writable register. By transferring data directly
into this register a short program jump can be executed directly, however, as only this low byte is
available for manipulation, the jumps are limited to the present page of memory, that is 256 loca-
tions. When such program jumps are executed it should also be noted that a dummy cycle will be
inserted.
Note The lower byte of the Program Counter is fully accessible under program control. The use of the
PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information
on the PCL register can be found in the Special Function Register section.
12
Cost-Effective I/O Type MCU
F e t c h I n s t . 1 E x e c u t e I n s t . 1
F e t c h I n s t . 2
F l u s h P i p e l i n e
1
2
3
4
5
6D E L A Y :
M O V A [ 1 2 H ]
C A L L D E L A Y
C P L [ 1 2 H ]
:
:
N O P
E x e c u t e I n s t . 2
F e t c h I n s t . 3
F e t c h I n s t . 6 E x e c u t e I n s t . 6
F e t c h I n s t . 7

Note 1. PC10~PC8: Current Program Counter bits
2. @7~@0: PCL bits
3. #10~#0: Instruction code bits
4. S10~S0: Stack register bits
5. For the HT48R08A-1/HT48C08 and HT48R09A-1/HT48C09, the Program Counter is 11 bits
wide, i.e. from b10~b0.
6. For the HT48R06A-1/HT48C06 and HT48R07A-1/HT48C07, since their Program Counter
is 10 bits wide, the b10 column in the table is not applicable.
7. For the HT48R05A-1/HT48C05, since its Program Counter is 9 bits wide, the b9 and b10
columns in the table are not applicable.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is organized into two levels and is neither part of the data nor part of the program
space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer
(SP) and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the
contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an inter-
rupt routine, signaled by a return instruction (RET or RETI), the Program Counter is restored to its
previous value from the stack. After a chip reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented (by RET or
RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the program-
mer to use the structure more easily. However, when the stack is full, a CALL subroutine instruc-
tion can still be executed which will result in a stack overflow. Precautions should be taken to avoid
such cases which might cause unpredictable program branching. Only the most recent 2 return ad-
dresses are stored.
Chapter 1 Hardware Structure
13
Mode Program Counter Bits
b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Initial Reset 00000000000
External Interrupt 00000000100
Timer/Event Counter Overflow 00000001000
Skip Program Counter + 2
Loading PCL PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0