HopeRF RF 65 User manual

Page 1
RF65
Tel: [phone] Fax: [phone] E-mail: [e-mail] http://www.hoperf.com
Part Number
Delivery
MOQ / Multiple
RF65
Tape & Reel
3000 pieces
Decimation and
&
Filtering
Demodulator &
Bit
Synchronizer
Packet Engine
& 66 Bytes
FIFO
Control Registers
- Shift
Registers
- SPI
Interface
Low Power Integrated UHF Receiver With -120dBm High Sensitivity
VBAT1&2 VR_ANA VR_DIG
Power
Distribution System
RC
Oscillator
RFIN
LNA Single
to
Differential
Mixers
Σ/ Δ
Modulators
RESET
SPI
Division by
2, 4 or 6
RSSI AFC
GND
Tank
I nductor
Loop
NC Filter
NC
NC
Frac-N PLL
Synthesizer
XO
32 MHz
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
XTAL GND
KEY PRODUCT FEATURES
The RF65 is a highly integrated RF receiver capable of
operation over a wide frequency range, including the
315,433,868 and 915 MHz license-free ISM (Industry
Scientific and Medical) frequency bands. Its highly
integrated architecture allows for a minimum of external
components whilst maintaining maximum design flexibility.
All major RF communication parameters are programmable
and most of them can be dynamically set. The RF65 offers
the unique advantage of programmable narrow-band and
wide-band communication modes without the need to
modify external components. The RF65 is optimized for
low power consumption while offering high sensitivity and
channelized operation. TrueRF™technology enables a
lowcost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
High Sensitivity: down to -120 dBm at 1.2 kbps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK demodulation
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
MARKETS
Europe: EN 300-220-1
North America: FCC Part 15.247, 15.249,
15.231
Narrow Korean and Japanese bands
QFN 28 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product

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3.4.15.
Frequency Error Indicator.......................................................................................................................
26
3.4.16.
Automatic Frequency Correction ............................................................................................................
27
3.4.17.
Optimized Setup for Low Modulation Index Systems .............................................................................
28
ADVANCED COMMUNICATIONS & SENSING DATASHEET
Table of Contents
Page
1. General
Description................................................................................................................................................. 8
1.1. Simplified Block Diagram ................................................................................................................................. 8
1.2. Pin and Marking Diagram................................................................................................................................... 9
1.3. Pin Description ...................................................................................................................................... 10
2. Electrical Characteristics.......................................................................................................................................... 11
2.1. ESD Notice....................................................................................................................................................... 11
2.2. Absolute Maximum Ratings ................................................................................................................... 11
2.3. Operating Range.............................................................................................................................................. 11
2.4. Chip Specification................................................................................................................................ 12
2.4.1. Power Consumption ................................................................................................................................. 12
2.4.2. Frequency Synthesis ................................................................................................................................ 12
2.4.3. Receiver ..................................................................................................................................................... 13
2.4.4. Digital Specification .................................................................................................................................. 14
3. Chip Description...................................................................................................................................................... 15
3.1. Power Supply Strategy..................................................................................................................................... 15
3.2. Low Battery Detector........................................................................................................................................ 15
3.3. Frequency Synthesis........................................................................................................................................ 15
3.3.1. Reference Oscillator ................................................................................................................................. 15
3.3.2. CLKOUT Output .......................................................................................................................................16
3.3.3. PLL Architecture ....................................................................................................................................... .16
3.3.4. Lock Time .................................................................................................................................................17
3.3.5. Lock Detect Indicator.................................................................................................................................17
3.4. Receiver Description ...............................................................................................................................17
3.4.1. Block Diagram ...........................................................................................................................................17
3.4.2. LNA - Single to Differential Buffer .............................................................................................................18
3.4.3. Automatic Gain Control............................................................................................................................. 18
3.4.4. Continuous-TimeDAGC............................................................................................................................20
3.4.5. Quadrature Mixer - ADCs - Decimators..................................................................................................... 20
3.4.6. Channel Filter ............................................................................................................................................20
3.4.7. DC Cancellation ........................................................................................................................................21
3.4.8. Complex Filter - OOK ................................................................................................................................22
3.4.9. RSSI ............................................................................................................................................................ 22
3.4.10. Cordic ........................................................................................................................................................ 22
3.4.11. Bit Rate Setting .......................................................................................................................................22
3.4.12. FSK Demodulator ....................................................................................................................................23
3.4.13. OOK Demodulator ..................................................................................................................................24
3.4.14. Bit Synchronizer .................................................................................................................................... 26

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5.4.1. General Description..................................................................................................................................
43
5.4.2. Rx Processing..........................................................................................................................................
43
5.5. Packet Mode .................................................................................................................................................
44
5.5.1.
General Description..................................................................................................................................
44
5.5.2.
Packet Format ..........................................................................................................................................
44
5.5.3.
Processing (without AES).........................................................................................................................
47
5.5.4.
AES..........................................................................................................................................................
47
5.5.5.
Handling Large Packets...........................................................................................................................
48
5.5.6.
Packet Filtering.........................................................................................................................................
48
5.5.7.
DC-Free Data Mechanisms ......................................................................................................................
50
Configuration and Status Registers ...................................................................................................................... 52
6.1.
General Description......................................................................................................................................
52
6.2.
Common Configuration Registers .................................................................................................................
55
6.3.
Receiver Registers ........................................................................................................................................
58
ADVANCED COMMUNICATIONS & SENSING DATASHEET
3.4.18. Temperature Sensor ............................................................................................................................29
3.4.19. Timeout Function.................................................................................................................................... 29
4. Operating Modes .................................................................................................................................................. 30
4.1. Basic Modes.................................................................................................................................................. 30
4.2. Automatic Sequencer and Wake-Up Times .................................................................................................30
4.2.1. Receiver Startup Time.............................................................................................................................30
4.2.2. Rx Start Procedure ..................................................................................................................................32
4.2.3. Optimized Frequency Hopping Sequences ..............................................................................................32
4.3. Listen Mode ................................................................................................................................................... 33
4.3.1. Timings ..................................................................................................................................................... 33
4.3.2. Criteria ...................................................................................................................................................... 34
4.3.3. End of Cycle Actions............................................................................................................................... 34
4.3.4. RC Timer Accuracy..................................................................................................................................35
4.4. AutoModes .................................................................................................................................................... . 36
5. Data Processing.................................................................................................................................................... . 37
5.1. Overview ......................................................................................................................................................... 37
5.1.1. Block Diagram ..........................................................................................................................................37
5.1.2. Data Operation Modes .............................................................................................................................37
5.2. Control Block Description .............................................................................................................................. 38
5.2.1. SPI Interface.............................................................................................................................................. 38
5.2.2. FIFO .......................................................................................................................................................... 39
5.2.3. Sync Word Recognition ............................................................................................................................ 40
5.2.4. Packet Handler .........................................................................................................................................41
5.2.5. Control ........................................................................................................................................................ 41
5.3. Digital IO Pins Mapping ................................................................................................................................... 42
5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 42
5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 42
5.4. Continuous Mode ............................................................................................................................................ 43
6.

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8.1.
Package Outline Drawing..............................................................................................................................
69
8.2.
Thermal Impedance ......................................................................................................................................
69
9. Chip Revisions ........................................................................................................................................................ 70
9.1. RC Oscillator Calibration...............................................................................................................................
70
9.2. Listen Mode...................................................................................................................................................
70
9.2.1. Resolutions...............................................................................................................................................
70
9.2.2. Exiting Listen Mode ..................................................................................................................................
71
9.3. OOK Floor Threshold Default Setting ...........................................................................................................
71
9.4. AFC Control ..................................................................................................................................................
71
9.4.1. AfcAutoClearOn.......................................................................................................................................
71
9.4.2. AfcLowBetaOn and LowBetaAfcOffset.....................................................................................................
71
9.5. ContinuousDagc............................................................................................................................................
71
ADVANCED COMMUNICATIONS & SENSING DATASHEET
6.4.
IRQ and Pin Mapping Registers ....................................................................................................................
60
6.5.
Packet Engine Registers ...............................................................................................................................
62
6.6.
Temperature Sensor Registers .....................................................................................................................
65
6.7.
Test Registers ...............................................................................................................................................
65
7. Application Information.........................................................................................................................................66
7.1.
Crystal Resonator Specification ....................................................................................................................
66
7.2.
Reset of the Chip ..........................................................................................................................................
66
7.2.1. POR............................................................................................................................................................ 66
7.2.2. Manual Reset ...........................................................................................................................................67
7.3. Reference Design ......................................................................................................................................... 67
8. Packaging Information ...........................................................................................................................................69

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Index of Figures Page
Figure 1. Block Diagram ................................................................................................................................................ 8
Figure 2. Pin Diagram .................................................................................................................................................... 9
Figure 3. Marking Diagram ............................................................................................................................................ 9
Figure 4. TCXO Connection ........................................................................................................................................ 15
Figure 5. Receiver Block Diagram ............................................................................................................................... 17
Figure 6. AGC Thresholds Settings ............................................................................................................................. 19
Figure 7. Cordic Extraction .......................................................................................................................................... 22
Figure 8. OOK Peak Demodulator Description ............................................................................................................ 24
Figure 9. Floor Threshold Optimization ....................................................................................................................... 25
Figure 10. Bit Synchronizer Description ...................................................................................................................... 26
Figure 11. FEI Process ................................................................................................................................................ 27
Figure 12. Optimized Afc (AfcLowBetaOn=1) .............................................................................................................. 28
Figure 13. Temperature Sensor Response ................................................................................................................. 29
Figure 14. Rx Startup - No AGC, no AFC .................................................................................................................... 31
Figure 15. Rx Startup - AGC, no AFC ......................................................................................................................... 31
Figure 16. Rx Startup - AGC and AFC ........................................................................................................................ 31
Figure 17. Listen Mode Sequence (no wanted signal is received) .............................................................................. 33
Figure 18. Listen Mode Sequence (wanted signal is received) ................................................................................... 35
Figure 19. Auto Modes of Packet Handler ................................................................................................................... 36
Figure 20. RF65 Data Processing Conceptual View ................................................................................................... 37
Figure 21. SPI Timing Diagram (single access) .......................................................................................................... 38
Figure 22. FIFO and Shift Register (SR) ..................................................................................................................... 39
Figure 23. FifoLevel IRQ Source Behavior .................................................................................................................. 40
Figure 24. Sync Word Recognition .............................................................................................................................. 41
Figure 25. Continuous Mode Conceptual View ........................................................................................................... 43
Figure 26. Rx Processing in Continuous Mode ........................................................................................................... 43
Figure 27. Packet Mode Conceptual View ................................................................................................................... 44
Figure 28. Fixed Length Packet Format ...................................................................................................................... 45
Figure 29. Variable Length Packet Format .................................................................................................................. 46
Figure 30. Unlimited Length Packet Format ................................................................................................................ 46
Figure 31. CRC Implementation .................................................................................................................................. 50
Figure 32. Manchester Decoding ................................................................................................................................ 50
Figure 33. Data De-Whitening ..................................................................................................................................... 51
Figure 34. POR Timing Diagram ................................................................................................................................. 66
Figure 35. Manual Reset Timing Diagram ................................................................................................................... 67
Figure 36. Application Schematic ................................................................................................................................ 67
Figure 37. Package Outline Drawing ........................................................................................................................... 68
Figure 38. Listen Mode Resolutions, V2a ................................................................................................................... 69
Figure 39. Listen Mode Resolution, V2b ..................................................................................................................... 69

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Figure 40. Exiting Listen Mode in RF65 V2a
............................................................................................................... 70
Figure 41. RegTestOok Description ............................................................................................................................ 70
Index of Tables Page
Table 1. RF65 Pinouts .................................................................................................................................................. 10
Table 2. Absolute Maximum Ratings ............................................................................................................................ 11
Table 3. Operating Range ............................................................................................................................................ 11
Table 4. Power Consumption Specification .................................................................................................................. 12
Table 5. Frequency Synthesizer Specification .............................................................................................................. 12
Table 6. Receiver Specification .................................................................................................................................... 13
Table 7. Digital Specification ........................................................................................................................................ 14
Table 8. LNA Gain Settings .......................................................................................................................................... 18
Table 9. Receiver Performance Summary .................................................................................................................... 19
Table 10. Available RxBw Settings ............................................................................................................................... 21
Table 11. Bit Rate Examples ........................................................................................................................................ 23
Table 12. Basic Receiver Modes .................................................................................................................................. 30
Table 13. Range of Durations in Listen Mode .............................................................................................................. 33
Table 14. Signal Acceptance Criteria in Listen Mode ................................................................................................... 34
Table 15. End of Listen Cycle Actions .......................................................................................................................... 34
Table 16. Status of FIFO when Switching Between Different Modes of the Chip ......................................................... 40
Table 17. DIO Mapping, Continuous Mode .................................................................................................................. 42
Table 18. DIO Mapping, Packet Mode ......................................................................................................................... 42
Table 19. Registers Summary ...................................................................................................................................... 52
Table 20. Common Configuration Registers ................................................................................................................. 55
Table 21. Receiver Registers ....................................................................................................................................... 58
Table 22. IRQ and Pin Mapping Registers ................................................................................................................... 60
Table 23. Packet Engine Registers .............................................................................................................................. 62
Table 24. Temperature Sensor Registers ..................................................................................................................... 65
Table 25. Test Registers .............................................................................................................................................. 65
Table 26. Crystal Specification ..................................................................................................................................... 66
Table 27. Chip Identification ......................................................................................................................................... 70
Table 28. Revision History ............................................................................................................................................ 72

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Acronyms
BOM Bill Of Materials LSB Least Significant Bit
BR Bit Rate MSB Most Significant Bit
BW Bandwidth NRZ Non Return to Zero
CCITT ComitéConsultatif International
Téléphonique et Télégraphique - ITU OOK On Off Keying
CRC Cyclic Redundancy Check PA Power Amplifier
DAC Digital to Analog Converter PCB Printed Circuit Board
ETSI European Telecommunications Standards
Insti t ute
PLL Phase-Locked Loop
FCC Federal Communications Commission POR Power On Reset
Fdev Frequency Deviation RBW Resolution BandWidth
FIFO First In First Out RF Radio Frequency
FIR Finite Impulse Response RSSI Received Signal Strength Indicator
FS Frequency Synthesizer Rx Receiver
FSK Frequency Shift Keying SAW Surface AcousticWave
GUI Graphical User Interface SPI Serial Peripheral Interface
IC Integrated Circuit SR Shift Register
ID IDentificator Stby Standby
IF Intermediate Frequency Tx Transmitter
IRQ Interrupt ReQuest uC Microcontroller
ITU International Telecommunication Union VCO Voltage Controlled Oscillator
LFSR Linear Feedback Shift Register XO Crystal Oscillator
LNA Low Noise Amplifier XOR eXclusive OR
LO Local Oscillator

Page 8
RF65
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Decimation and
& Filtering
Demodulator &
Bit Synchronizer
Packet Engine & 66 Bytes FIFO
Control Registers - Shift Registers - SPI Interface
ADVANCED COMMUNICATIONS & SENSING DATASHEET
This product datasheet contains a detailed description of the RF65 performance and functionality.
.
1. General Description
The RF65 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
RF65's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF receiver for robust frequency agile RF links, and where stable
and constant RF performance is required over the full operating range of the device down to 1.8V.
The RF65 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and
the 902-928 MHz North American ISM bands. Coupled with a very aggressive sensitivity, the advanced system features of
the RF65 include a 66 byte RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and
configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU
requirements.
The RF65 complies with both ETSI and FCC regulatory requirements and is available in a 5 x 5 mm QFN 28 lead
package
1.1. Simplified Block Diagram
VBAT1&2 VR_ANA VR_DIG
Power Distribution System RC
Oscillator
LNA Single to
Differential
Mixers
Σ/Δ
Modulators
RFIN RESET
SPI
Tank
Inductor
Loop
NC
Filter
NC
NC
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI AFC GND
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Frequency Synthesis
Receiver Blocks
XTAL GND
Control Blocks Primarily Analog
Primarily Digital
Figure 1. Block
Diagram

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
1.2. Pin and Marking Diagram
The following diagram shows the pin arrangement of the QFN package, top view.
Figure 2. Pin
Diagram
Notes yyww refers to the date code
xxxxxx refers to the lot number
Figure 3. Marking Diagram
RF65

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
1.3. Pin Description
Table 1 RF65 Pinouts
Number
Name
Type
Description
0
GROUND
-
Exposed ground pad
1
VBAT1
-
Supply voltage
2
VR_ANA
-
Regulated supply voltage for analogue circuitry
3
VR_DIG
-
Regulated supply voltage for digital blocks
4
XTA
I/O
XTAL connection
5
XTB
I/O
XTAL connection
6
RESET
I/O
Reset trigger input
7
NC
-
Connect to GND or Do not connect
8
DIO0
I/O
Digital I/O, software configured
9
DIO1/DCLK
O
Digital Output, software configured
10
DIO2/DATA
O
Digital Output, software configured
11
DIO3
I/O
Digital I/O, software configured
12
DIO4
I/O
Digital I/O, software configured
13
DIO5
I/O
Digital I/O, software configured
14
NC
-
Connect to GND or Do not connect
15
VBAT2
-
Supply voltage
16
GND
-
Ground
17
SCK
I
SPI Clock input
18
MISO
O
SPI Data output
19
MOSI
I
SPI Data input
20
NSS
I
SPI Chip select input
21
NC
-
Connect to GND or Do not connect
22
NC
-
Do not connect
23
GND
-
Ground
24
RFIN
I
RF input
25
2
GND
-
Ground
26
NC
-
Do not connect
27
NC
-
Do not connect
28
NC
-
Connect to GND or Do not connect