HopeRF RF 65 User manual

Page 1
RF65
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Part Number
Delivery
MOQ / Multiple
RF65
Tape & Reel
3000 pieces
Decimation and
&
Filtering
Demodulator &
Bit
Synchronizer
Packet Engine
& 66 Bytes
FIFO
Control Registers
- Shift
Registers
- SPI
Interface
Low Power Integrated UHF Receiver With -120dBm High Sensitivity
VBAT1&2 VR_ANA VR_DIG
Power
Distribution System
RC
Oscillator
RFIN
LNA Single
to
Differential
Mixers
Σ/ Δ
Modulators
RESET
SPI
Division by
2, 4 or 6
RSSI AFC
GND
Tank
I nductor
Loop
NC Filter
NC
NC
Frac-N PLL
Synthesizer
XO
32 MHz
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
XTAL GND
KEY PRODUCT FEATURES
The RF65 is a highly integrated RF receiver capable of
operation over a wide frequency range, including the
315,433,868 and 915 MHz license-free ISM (Industry
Scientific and Medical) frequency bands. Its highly
integrated architecture allows for a minimum of external
components whilst maintaining maximum design flexibility.
All major RF communication parameters are programmable
and most of them can be dynamically set. The RF65 offers
the unique advantage of programmable narrow-band and
wide-band communication modes without the need to
modify external components. The RF65 is optimized for
low power consumption while offering high sensitivity and
channelized operation. TrueRF™technology enables a
lowcost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
High Sensitivity: down to -120 dBm at 1.2 kbps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Constant RF performance over voltage range of chip
FSK Bit rates up to 300 kb/s
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK demodulation
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 encryption and 66-
byte FIFO
Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
MARKETS
Europe: EN 300-220-1
North America: FCC Part 15.247, 15.249,
15.231
Narrow Korean and Japanese bands
QFN 28 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product

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3.4.15.
Frequency Error Indicator.......................................................................................................................
26
3.4.16.
Automatic Frequency Correction ............................................................................................................
27
3.4.17.
Optimized Setup for Low Modulation Index Systems .............................................................................
28
ADVANCED COMMUNICATIONS & SENSING DATASHEET
Table of Contents
Page
1. General
Description................................................................................................................................................. 8
1.1. Simplified Block Diagram ................................................................................................................................. 8
1.2. Pin and Marking Diagram................................................................................................................................... 9
1.3. Pin Description ...................................................................................................................................... 10
2. Electrical Characteristics.......................................................................................................................................... 11
2.1. ESD Notice....................................................................................................................................................... 11
2.2. Absolute Maximum Ratings ................................................................................................................... 11
2.3. Operating Range.............................................................................................................................................. 11
2.4. Chip Specification................................................................................................................................ 12
2.4.1. Power Consumption ................................................................................................................................. 12
2.4.2. Frequency Synthesis ................................................................................................................................ 12
2.4.3. Receiver ..................................................................................................................................................... 13
2.4.4. Digital Specification .................................................................................................................................. 14
3. Chip Description...................................................................................................................................................... 15
3.1. Power Supply Strategy..................................................................................................................................... 15
3.2. Low Battery Detector........................................................................................................................................ 15
3.3. Frequency Synthesis........................................................................................................................................ 15
3.3.1. Reference Oscillator ................................................................................................................................. 15
3.3.2. CLKOUT Output .......................................................................................................................................16
3.3.3. PLL Architecture ....................................................................................................................................... .16
3.3.4. Lock Time .................................................................................................................................................17
3.3.5. Lock Detect Indicator.................................................................................................................................17
3.4. Receiver Description ...............................................................................................................................17
3.4.1. Block Diagram ...........................................................................................................................................17
3.4.2. LNA - Single to Differential Buffer .............................................................................................................18
3.4.3. Automatic Gain Control............................................................................................................................. 18
3.4.4. Continuous-TimeDAGC............................................................................................................................20
3.4.5. Quadrature Mixer - ADCs - Decimators..................................................................................................... 20
3.4.6. Channel Filter ............................................................................................................................................20
3.4.7. DC Cancellation ........................................................................................................................................21
3.4.8. Complex Filter - OOK ................................................................................................................................22
3.4.9. RSSI ............................................................................................................................................................ 22
3.4.10. Cordic ........................................................................................................................................................ 22
3.4.11. Bit Rate Setting .......................................................................................................................................22
3.4.12. FSK Demodulator ....................................................................................................................................23
3.4.13. OOK Demodulator ..................................................................................................................................24
3.4.14. Bit Synchronizer .................................................................................................................................... 26

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5.4.1. General Description..................................................................................................................................
43
5.4.2. Rx Processing..........................................................................................................................................
43
5.5. Packet Mode .................................................................................................................................................
44
5.5.1.
General Description..................................................................................................................................
44
5.5.2.
Packet Format ..........................................................................................................................................
44
5.5.3.
Processing (without AES).........................................................................................................................
47
5.5.4.
AES..........................................................................................................................................................
47
5.5.5.
Handling Large Packets...........................................................................................................................
48
5.5.6.
Packet Filtering.........................................................................................................................................
48
5.5.7.
DC-Free Data Mechanisms ......................................................................................................................
50
Configuration and Status Registers ...................................................................................................................... 52
6.1.
General Description......................................................................................................................................
52
6.2.
Common Configuration Registers .................................................................................................................
55
6.3.
Receiver Registers ........................................................................................................................................
58
ADVANCED COMMUNICATIONS & SENSING DATASHEET
3.4.18. Temperature Sensor ............................................................................................................................29
3.4.19. Timeout Function.................................................................................................................................... 29
4. Operating Modes .................................................................................................................................................. 30
4.1. Basic Modes.................................................................................................................................................. 30
4.2. Automatic Sequencer and Wake-Up Times .................................................................................................30
4.2.1. Receiver Startup Time.............................................................................................................................30
4.2.2. Rx Start Procedure ..................................................................................................................................32
4.2.3. Optimized Frequency Hopping Sequences ..............................................................................................32
4.3. Listen Mode ................................................................................................................................................... 33
4.3.1. Timings ..................................................................................................................................................... 33
4.3.2. Criteria ...................................................................................................................................................... 34
4.3.3. End of Cycle Actions............................................................................................................................... 34
4.3.4. RC Timer Accuracy..................................................................................................................................35
4.4. AutoModes .................................................................................................................................................... . 36
5. Data Processing.................................................................................................................................................... . 37
5.1. Overview ......................................................................................................................................................... 37
5.1.1. Block Diagram ..........................................................................................................................................37
5.1.2. Data Operation Modes .............................................................................................................................37
5.2. Control Block Description .............................................................................................................................. 38
5.2.1. SPI Interface.............................................................................................................................................. 38
5.2.2. FIFO .......................................................................................................................................................... 39
5.2.3. Sync Word Recognition ............................................................................................................................ 40
5.2.4. Packet Handler .........................................................................................................................................41
5.2.5. Control ........................................................................................................................................................ 41
5.3. Digital IO Pins Mapping ................................................................................................................................... 42
5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 42
5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 42
5.4. Continuous Mode ............................................................................................................................................ 43
6.

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8.1.
Package Outline Drawing..............................................................................................................................
69
8.2.
Thermal Impedance ......................................................................................................................................
69
9. Chip Revisions ........................................................................................................................................................ 70
9.1. RC Oscillator Calibration...............................................................................................................................
70
9.2. Listen Mode...................................................................................................................................................
70
9.2.1. Resolutions...............................................................................................................................................
70
9.2.2. Exiting Listen Mode ..................................................................................................................................
71
9.3. OOK Floor Threshold Default Setting ...........................................................................................................
71
9.4. AFC Control ..................................................................................................................................................
71
9.4.1. AfcAutoClearOn.......................................................................................................................................
71
9.4.2. AfcLowBetaOn and LowBetaAfcOffset.....................................................................................................
71
9.5. ContinuousDagc............................................................................................................................................
71
ADVANCED COMMUNICATIONS & SENSING DATASHEET
6.4.
IRQ and Pin Mapping Registers ....................................................................................................................
60
6.5.
Packet Engine Registers ...............................................................................................................................
62
6.6.
Temperature Sensor Registers .....................................................................................................................
65
6.7.
Test Registers ...............................................................................................................................................
65
7. Application Information.........................................................................................................................................66
7.1.
Crystal Resonator Specification ....................................................................................................................
66
7.2.
Reset of the Chip ..........................................................................................................................................
66
7.2.1. POR............................................................................................................................................................ 66
7.2.2. Manual Reset ...........................................................................................................................................67
7.3. Reference Design ......................................................................................................................................... 67
8. Packaging Information ...........................................................................................................................................69

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Index of Figures Page
Figure 1. Block Diagram ................................................................................................................................................ 8
Figure 2. Pin Diagram .................................................................................................................................................... 9
Figure 3. Marking Diagram ............................................................................................................................................ 9
Figure 4. TCXO Connection ........................................................................................................................................ 15
Figure 5. Receiver Block Diagram ............................................................................................................................... 17
Figure 6. AGC Thresholds Settings ............................................................................................................................. 19
Figure 7. Cordic Extraction .......................................................................................................................................... 22
Figure 8. OOK Peak Demodulator Description ............................................................................................................ 24
Figure 9. Floor Threshold Optimization ....................................................................................................................... 25
Figure 10. Bit Synchronizer Description ...................................................................................................................... 26
Figure 11. FEI Process ................................................................................................................................................ 27
Figure 12. Optimized Afc (AfcLowBetaOn=1) .............................................................................................................. 28
Figure 13. Temperature Sensor Response ................................................................................................................. 29
Figure 14. Rx Startup - No AGC, no AFC .................................................................................................................... 31
Figure 15. Rx Startup - AGC, no AFC ......................................................................................................................... 31
Figure 16. Rx Startup - AGC and AFC ........................................................................................................................ 31
Figure 17. Listen Mode Sequence (no wanted signal is received) .............................................................................. 33
Figure 18. Listen Mode Sequence (wanted signal is received) ................................................................................... 35
Figure 19. Auto Modes of Packet Handler ................................................................................................................... 36
Figure 20. RF65 Data Processing Conceptual View ................................................................................................... 37
Figure 21. SPI Timing Diagram (single access) .......................................................................................................... 38
Figure 22. FIFO and Shift Register (SR) ..................................................................................................................... 39
Figure 23. FifoLevel IRQ Source Behavior .................................................................................................................. 40
Figure 24. Sync Word Recognition .............................................................................................................................. 41
Figure 25. Continuous Mode Conceptual View ........................................................................................................... 43
Figure 26. Rx Processing in Continuous Mode ........................................................................................................... 43
Figure 27. Packet Mode Conceptual View ................................................................................................................... 44
Figure 28. Fixed Length Packet Format ...................................................................................................................... 45
Figure 29. Variable Length Packet Format .................................................................................................................. 46
Figure 30. Unlimited Length Packet Format ................................................................................................................ 46
Figure 31. CRC Implementation .................................................................................................................................. 50
Figure 32. Manchester Decoding ................................................................................................................................ 50
Figure 33. Data De-Whitening ..................................................................................................................................... 51
Figure 34. POR Timing Diagram ................................................................................................................................. 66
Figure 35. Manual Reset Timing Diagram ................................................................................................................... 67
Figure 36. Application Schematic ................................................................................................................................ 67
Figure 37. Package Outline Drawing ........................................................................................................................... 68
Figure 38. Listen Mode Resolutions, V2a ................................................................................................................... 69
Figure 39. Listen Mode Resolution, V2b ..................................................................................................................... 69

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Figure 40. Exiting Listen Mode in RF65 V2a
............................................................................................................... 70
Figure 41. RegTestOok Description ............................................................................................................................ 70
Index of Tables Page
Table 1. RF65 Pinouts .................................................................................................................................................. 10
Table 2. Absolute Maximum Ratings ............................................................................................................................ 11
Table 3. Operating Range ............................................................................................................................................ 11
Table 4. Power Consumption Specification .................................................................................................................. 12
Table 5. Frequency Synthesizer Specification .............................................................................................................. 12
Table 6. Receiver Specification .................................................................................................................................... 13
Table 7. Digital Specification ........................................................................................................................................ 14
Table 8. LNA Gain Settings .......................................................................................................................................... 18
Table 9. Receiver Performance Summary .................................................................................................................... 19
Table 10. Available RxBw Settings ............................................................................................................................... 21
Table 11. Bit Rate Examples ........................................................................................................................................ 23
Table 12. Basic Receiver Modes .................................................................................................................................. 30
Table 13. Range of Durations in Listen Mode .............................................................................................................. 33
Table 14. Signal Acceptance Criteria in Listen Mode ................................................................................................... 34
Table 15. End of Listen Cycle Actions .......................................................................................................................... 34
Table 16. Status of FIFO when Switching Between Different Modes of the Chip ......................................................... 40
Table 17. DIO Mapping, Continuous Mode .................................................................................................................. 42
Table 18. DIO Mapping, Packet Mode ......................................................................................................................... 42
Table 19. Registers Summary ...................................................................................................................................... 52
Table 20. Common Configuration Registers ................................................................................................................. 55
Table 21. Receiver Registers ....................................................................................................................................... 58
Table 22. IRQ and Pin Mapping Registers ................................................................................................................... 60
Table 23. Packet Engine Registers .............................................................................................................................. 62
Table 24. Temperature Sensor Registers ..................................................................................................................... 65
Table 25. Test Registers .............................................................................................................................................. 65
Table 26. Crystal Specification ..................................................................................................................................... 66
Table 27. Chip Identification ......................................................................................................................................... 70
Table 28. Revision History ............................................................................................................................................ 72

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
Acronyms
BOM Bill Of Materials LSB Least Significant Bit
BR Bit Rate MSB Most Significant Bit
BW Bandwidth NRZ Non Return to Zero
CCITT ComitéConsultatif International
Téléphonique et Télégraphique - ITU OOK On Off Keying
CRC Cyclic Redundancy Check PA Power Amplifier
DAC Digital to Analog Converter PCB Printed Circuit Board
ETSI European Telecommunications Standards
Insti t ute
PLL Phase-Locked Loop
FCC Federal Communications Commission POR Power On Reset
Fdev Frequency Deviation RBW Resolution BandWidth
FIFO First In First Out RF Radio Frequency
FIR Finite Impulse Response RSSI Received Signal Strength Indicator
FS Frequency Synthesizer Rx Receiver
FSK Frequency Shift Keying SAW Surface AcousticWave
GUI Graphical User Interface SPI Serial Peripheral Interface
IC Integrated Circuit SR Shift Register
ID IDentificator Stby Standby
IF Intermediate Frequency Tx Transmitter
IRQ Interrupt ReQuest uC Microcontroller
ITU International Telecommunication Union VCO Voltage Controlled Oscillator
LFSR Linear Feedback Shift Register XO Crystal Oscillator
LNA Low Noise Amplifier XOR eXclusive OR
LO Local Oscillator

Page 8
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Decimation and
& Filtering
Demodulator &
Bit Synchronizer
Packet Engine & 66 Bytes FIFO
Control Registers - Shift Registers - SPI Interface
ADVANCED COMMUNICATIONS & SENSING DATASHEET
This product datasheet contains a detailed description of the RF65 performance and functionality.
.
1. General Description
The RF65 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
RF65's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF receiver for robust frequency agile RF links, and where stable
and constant RF performance is required over the full operating range of the device down to 1.8V.
The RF65 is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European and
the 902-928 MHz North American ISM bands. Coupled with a very aggressive sensitivity, the advanced system features of
the RF65 include a 66 byte RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and
configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU
requirements.
The RF65 complies with both ETSI and FCC regulatory requirements and is available in a 5 x 5 mm QFN 28 lead
package
1.1. Simplified Block Diagram
VBAT1&2 VR_ANA VR_DIG
Power Distribution System RC
Oscillator
LNA Single to
Differential
Mixers
Σ/Δ
Modulators
RFIN RESET
SPI
Tank
Inductor
Loop
NC
Filter
NC
NC
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI AFC GND
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Frequency Synthesis
Receiver Blocks
XTAL GND
Control Blocks Primarily Analog
Primarily Digital
Figure 1. Block
Diagram

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
1.2. Pin and Marking Diagram
The following diagram shows the pin arrangement of the QFN package, top view.
Figure 2. Pin
Diagram
Notes yyww refers to the date code
xxxxxx refers to the lot number
Figure 3. Marking Diagram
RF65

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
1.3. Pin Description
Table 1 RF65 Pinouts
Number
Name
Type
Description
0
GROUND
-
Exposed ground pad
1
VBAT1
-
Supply voltage
2
VR_ANA
-
Regulated supply voltage for analogue circuitry
3
VR_DIG
-
Regulated supply voltage for digital blocks
4
XTA
I/O
XTAL connection
5
XTB
I/O
XTAL connection
6
RESET
I/O
Reset trigger input
7
NC
-
Connect to GND or Do not connect
8
DIO0
I/O
Digital I/O, software configured
9
DIO1/DCLK
O
Digital Output, software configured
10
DIO2/DATA
O
Digital Output, software configured
11
DIO3
I/O
Digital I/O, software configured
12
DIO4
I/O
Digital I/O, software configured
13
DIO5
I/O
Digital I/O, software configured
14
NC
-
Connect to GND or Do not connect
15
VBAT2
-
Supply voltage
16
GND
-
Ground
17
SCK
I
SPI Clock input
18
MISO
O
SPI Data output
19
MOSI
I
SPI Data input
20
NSS
I
SPI Chip select input
21
NC
-
Connect to GND or Do not connect
22
NC
-
Do not connect
23
GND
-
Ground
24
RFIN
I
RF input
25
2
GND
-
Ground
26
NC
-
Do not connect
27
NC
-
Do not connect
28
NC
-
Connect to GND or Do not connect

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
2. Electrical Characteristics
2.1. ESD Notice
The RF65 is a high performance radio frequency device.
Class 2 of the JEDEC standard JESD22-A114-B(Human Body Model) on all pins.
Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins.
Class IV of the JEDEC standard JESD22-C101C (Charged Device Model) on pins 2-3-24-26-27, Class III on all other pins.
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2 Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
VDDmr
Supply Voltage
-0.5
3.9
V
Tmr
Temperature
-55
+115
°C
Tj
Junction temperature
-
+125
°C
Pmr
RF Input Level
-
+6
dBm
2.3. Operating Range
Table 3 Operating Range
Symbol
Description
Min
Max
Unit
VDDop
Supply voltage
1.8
3.6
V
Top
Operational temperature range
-40
+85
°C
Clop
Load capacitance on digital ports
-
25
pF
ML
RF Input Level
-
0
dBm

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
2.4. Chip Specification
The tables below give the electrical specifications of the receiver under the following conditions: Supply voltage VBAT1=
VBAT2=VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, 2-level FSK modulation without pre-filtering,
Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified.
Note Unless otherwise specified, the performances in the other frequency bands are similar or better.
2.4.1. Power Consumption
Table 4 Power Consumption Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
IDDSL
Supply current in sleep mode
-
0.1
1
uA
IDDIDLE
Supply current in Idle mode
RC oscillator enabled
-
1.2
-
uA
IDDST
Supply current in standby mode
Crystal oscillator enabled
-
1.25
1.5
mA
IDDFS
Supply current in synthesizer
mode
-
9
-
mA
IDDR
Supply current in receive mode
-
16
-
mA
2.4.2. Frequency Synthesis
Table 5 Frequency Synthesizer Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
FR
Synthesizer Frequency Range
Programmable
290
424
862
-
-
-
340
510
1020
MHz
MHz
MHz
FXOSC
Crystal oscillator frequency
See section 7.1
-
32
-
MHz
TS_OSC
Crystal oscillator wake-up time
-
250
500
us
TS_FS
Frequency synthesizer wake-up
time to PllLock signal
From Standby mode
-
80
150
us
TS_HOP
Frequency synthesizer hop time
at most 10 kHz away from the
target
200 kHz step
1 MHz step
5 MHz step
7 MHz step
12 MHz step
20 MHz step
25 MHz step
-
-
-
-
-
-
-
20
20
50
50
80
80
80
-
-
-
-
-
-
-
us
us
us
us
us
us
us
FSTEP
Frequency synthesizer step
FSTEP = FXOSC/219
-
61.0
-
Hz
FRC
RC Oscillator frequency
After calibration
-
62.5
-
kHz
BRF
Bit rate, FSK
Programmable
1.2
-
300
kbps
BRO
Bit rate, OOK
Programmable
1.2
-
32.768
kbps

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
2.4.3. Receiver
All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a
PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set
to 200 Ohms, by setting bit LnaZin in RegLna to 1. Blocking tests are performed with an unmodulated interferer. The
wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity
level.
Table 6 Receiver Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
RFS_F
FSK sensitivity, highest LNA gain
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s
-
-
-
-118
-114
-105
-
-
-
dBm
dBm
dBm
FDA = 5 kHz, BR = 1.2 kb/s*
-
-120
-
dBm
RFS_O
OOK sensitivity, highest LNA gain
BR = 4.8 kb/s
-
-112
-109
dBm
CCR
Co-Channel Rejection
-13
-10
-
dB
ACR
Adjacent Channel Rejection
Offset = +/- 25 kHz
Offset = +/- 50 kHz
-
37
42
42
-
-
dB
dB
BI
Blocking Immunity
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-
-
-45
-40
-32
-
-
-
dBm
dBm
dBm
Blocking Immunity
Wanted signal at sensitivity
+16dB
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-
-
-36
-33
-25
-
-
-
dBm
dBm
dBm
AMR
AM Rejection , AM modulated
interferer with 100% modulation
depth, fm = 1 kHz, square
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
-
-
-45
-40
-32
-
-
-
dBm
dBm
dBm
IIP2
2nd order Input Intercept Point
Unwanted tones are 20 MHz
above the LO
Lowest LNA gain
Highest LNA gain
-
-
+75
+35
-
-
dBm
dBm
IIP3
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Lowest LNA gain
Highest LNA gain
-
-23
+20
-18
-
-
dBm
dBm
BW_SSB
Single Side channel filter BW
Programmable
2.6
-
500
kHz
IMR_OOK
Image rejection in OOK mode
Wanted signal level = -106 dBm
27
30
-
dB
TS_RE
Receiver wake-up time, from PLL
locked state to RxReady
RxBw = 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
-
-
1.7
96
-
-
ms
us
TS_RE_AGC
Receiver wake-up time, from PLL
locked state, AGC enabled
RxBw= 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
-
3.0
163
ms
us
TS_RE_AGC
&AFC
Receiver wake-up time, from PLL
lock state, AGC and AFC enabled
RxBw= 10 kHz, BR = 4.8 kb/s
RxBw = 200 kHz, BR = 100 kb/s
4.8
265
ms
us

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ADVANCED COMMUNICATIONS & SENSING DATASHEET
TS_FEI
FEI sampling time
Receiver is ready
-
4.Tbit
-
-
TS_AFC
AFC Response Time
Receiver is ready
-
4.Tbit
-
-
TS_RSSI
RSSI Response Time
Receiver is ready
-
2.Tbit
-
-
DR_RSSI
RSSI Dynamic Range
AGC enabled Min
Max
-
-
-115
0
-
-
dBm
dBm
* Set SensitivityBoostin RegTestLna to 0x2D to reduce the noise floor in the receiver
2.4.4. Digital Specification
Conditions: Temp = 25°C, VDD = 3.3V, FXOSC = 32 MHz, unless otherwise specified.
Table 7 Digital Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
VIH
Digital input level high
0.8
-
-
VDD
VIL
Digital input level low
-
-
0.2
VDD
VOH
Digital output level high
Imax = 1 mA
0.9
-
-
VDD
VOL
Digital output level low
Imax = -1 mA
-
-
0.1
VDD
FSCK
SCK frequency
-
-
10
MHz
tch
SCK high time
50
-
-
ns
tcl
SCK low time
50
-
-
ns
trise
SCK rise time
-
5
-
ns
tfall
SCK fall time
-
5
-
ns
tsetup
MOSI setup time
from MOSI change to SCK rising
edge
30
-
-
ns
thold
MOSI hold time
from SCK rising edge to MOSI
change
60
-
-
ns
tnsetup
NSS setup time
from NSS falling edge to SCK rising
edge
30
-
-
ns
tnhold
NSS hold time
from SCK falling edge to NSS rising
edge, normal mode
30
-
-
ns
tnhigh
NSS high time between SPI
accesses
20
-
-
ns
T_DATA
DATA hold and setup time
250
-
-
ns

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3. Chip Description
This section describes in depth the architecture of the RF65 low-power, highly integrated receiver.
3.1. Power Supply Strategy
The RF65 employs an advanced power supply scheme, which provides stable operating characteristics over the full
temperature and voltage range of operation.
The RF65 can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be
connected, as suggested in the reference design on VR_DIG and VR_ANA pins to ensure a correct operation of the
built-in voltage regulators.
3.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to passing a
programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to any of the DIO
pins, through the programmation of RegDioMapping.
3.3. Frequency Synthesis
The LO generation on the RF65 is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with
automatic calibration.
3.3.1. Reference Oscillator
The crystal oscillator is the main timing reference of the RF65. It is used as a reference for the frequency synthesizer and
as a clock for the digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the built-
in sequencer, the RF65 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To
manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will
only be made available on the output buffer when a stable XO oscillation is achieved.
An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at
address 0x59 should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, CD.
XTA
XTB
TCXO
32 MHz
NC
OP
Vcc
Vcc
GND
C
D
Figure 4. TCXO
Connection

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F =
XOS C
ADVANCED COMMUNICATIONS & SENSING DATASHEET
3.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 13) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note to minimize the current consumption of the RF65, please ensure that the CLKOUT signal is disabled when not
required.
3.3.3. PLL Architecture
The frequency synthesizer generating the LO frequency for the receiver is a fractional-N sigma-delta PLL. The PLL
incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the loop filter
are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit.
3.3.3.1. VCO
The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO
leakage in receiver mode, to improve the quadrature precision of the receiver.
The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is
performed each time the RF65 PLL is activated. Automatic calibration times are fully transparent to the end-user, as their
processing time is included in the TS_RE specifications.
3.3.3.2. PLL Bandwidth
The bandwidth of the RF65 Fractional-N PLL is wide enough to allow for very fast PLL lock times, enabling both short
startup and fast hop times required for frequency agile applications.
3.3.3.3. Carrier Frequency and Resolution
The RF65 PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency
range, and is given by: F
STE P ----------------
2
19
The carrier frequency is programmed through RegFrf, split across addresses 0x07 to 0x09:
FRF = FSTEP × Frf(23,0)
Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the
least significant byte FrfLsb in RegFrfLsb is written.

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Decimator
Processing
ADVANCED COMMUNICATIONS & SENSING DATASHEET
3.3.4. Lock Time
PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc.
When using the built-in sequencer, the RF65 optimizes the startup time and automatically starts the receiver when the
PLL has locked. To manually control the startup time, the user should either wait for TS_FS max given in the specification,
or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range.
When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately:
In a frequency hopping scheme, the timings TS_HOP given in the table of specifications give an order of magnitude for the
expected lock times.
3.3.5. Lock Detect Indicator
A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its
locking range. Please refer to Table 17 and Table 18 to map this interrupt to the desired pins.
3.4. Receiver Description
The RF65 features a digital receiver with the analog to digital conversion process being performed directly following the
LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is,
however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet
handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The
receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements.
3.4.1. Block Diagram
Rx Calibration
Reference
RFIN
LNA
Single to
Differential
Mixers
Σ/ Δ
Modulators
Channel
Filter
DC
Cancellation
Complex
Filter
CORDIC
Phase
Output
Module
Output
RSSI
FSK
Demodulator
OOK
Demodulator
Local
Oscillator
AFC
Bypassed
in FSK
AGC
Figure 5. Receiver Block
Diagram
The following sections give a brief description of each of the receiver blocks.

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3.4.2. LNA - Single to Differential Buffer
The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is
designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegLna), and the parasitic
capacitance at the LNA input port is cancelled with the external RF choke. A single to differential buffer is implemented to
improve the second order linearity of the receiver.
The LNA gain, including the single-to-differentialbuffer, is programmable over a 48 dB dynamic range, and control is either
manual or automatic with the embedded AGC function.
Note In the specific case where the LNA gain is manually set by the user, the receiver will not be able to properly handle
FSK signals with a modulation index smaller than 2 at an input power greater than the 1dB compression point,
tabulated in section 3.4.3.
Table 8 LNA Gain Settings
LnaGainSelect
LNA Gain
Gain Setting
000
Any of the below, set by the AGC loop
-
001
Max gain
G1
010
Max gain - 6 dB
G2
011
Max gain - 12 dB
G3
100
Max gain - 24 dB
G4
101
Max gain - 36 dB
G5
110
Max gain - 48 dB
G6
111
Reserved
-
3.4.3. Automatic Gain Control
By default (LnaGainSelect = 000), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/
linearity trade-off.
Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver
is enabled:
The receiver stays in WAIT mode, until RssiValue exceeds RssiThreshold for two consecutive samples. Its power
consumption is the receiver power consumption.
When this condition is satisfied, the receiver automaticallyselects the most suitable LNA gain, optimizing the sensitivity/
linearity trade-off.
The programmed LNA gain, read-accessible with LnaCurrentGain in RegLna, is carried on for the whole duration of the
packet, until one of the following conditions is fulfilled:
Packet mode: if AutoRxRestartOn = 0, the LNA gain will remain the same for the reception of the following packet. If
AutoRxRestartOn = 1, after the controller has emptied the FIFO the receiver will re-enter the WAIT mode described
above, after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false
RSSI detection. In both cases (AutoRxRestartOn=0or AutoRxRestartOn=1),the receiver can also re-enter the WAIT
mode by setting RestartRx bit to 1. The user can decide to do so, to manually launch a new AGC procedure.
Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same
LNA gain, or to restart the procedure, by setting RestartRx bit to 1, resuming the WAIT mode of the receiver, described
above.
Notes - the AGC procedure must be performed while receiving preamble in FSK mode
- in OOK mode, the AGC will give better results if performed while receiving a constant “1”
sequence

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The following figure illustrates the AGC behavior::
Towards
-125 dBm
16dB 7dB 11dB 9dB 11dB
Pin [dBm]
G1 G2 G3 G4 G5
G6
Higher
Sensitivity
Lower Linearity
Lower Noise Figure
Lower Sensitivity
Higher Linearity
Higher Noise Figure
Figure 6. AGC Thresholds
Settings
The following table summarizes the performance (typical figures) of the complete receiver:
Table 9 Receiver Performance Summary
Input Power
Pin
Gain
Setting
Receiver Performance (typ)
P-1dB
[dBm]
NF
[dB]
IIP3
[dBm]
IIP2
[dBm]
Pin < AgcThresh1
G1
-37
7
-18
+35
AgcThresh1 < Pin < AgcThresh2
G2
-31
13
-15
+40
AgcThresh2 < Pin < AgcThresh3
G3
-26
18
-8
+48
AgcThresh3 < Pin < AgcThresh4
G4
-14
27
-1
+62
AgcThresh4 < Pin < AgcThresh5
G5
>-6
36
+13
+68
AgcThresh5 < Pin
G6
>0
44
+20
+75
3.4.3.1. RssiThreshold Setting
For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the receiver. The
receiver will remain in WAIT mode until RssiThreshold is exceeded.
Note When AFC is enabled and performed automatically at the receiver startup, the channel filter used by the receiver
during the AFC and the AGC is RxBwAfc instead of the standard RxBw setting. This may impact the sensitivity of
the receiver, and the setting of RssiThreshold accordingly
3.4.3.2. AGC Reference
The AGC reference level is automaticallycomputed in the RF65, according to:
AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*RxBw) + FadingMargin [dBm]

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3.4.4. Continuous-Time DAGC
In addition to the automatic gain control described in section 3.4.3, the RF65 is capable of continuously adjusting its gain in
the digital domain, after the analog to digital conversion has occured. This feature, named DAGC, is fully transparent to the
end user. The digital gain adjustment is repeated every 2 bits, and has the following benefits:
Fully transparent to the end user
Improves the fading margin of the receiver during the reception of a packet, even if the gain of the LNA is frozen
Improves the receiver robustness in fast fading signal conditions, by quickly adjusting the receiver gain (every 2 bits)
Works in Continuous, Packet, and unlimited length Packet modes
The DAGC is enabled by setting RegTestDagc to 0x10 for low modulation index systems (i.e. when AfcLowBetaOn=1,
refer to section 3.4.17), and 0x30 for other systems. See section 9.5 for details. It is recommended to always enable the
DAGC.
3.4.5. Quadrature Mixer - ADCs - Decimators
The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the
receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high
IIP2 and IIP3 responses.
In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the
rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers.
The I and Q digitalization is made by two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their
gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no
impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This
ADC can also be used for temperature measurement, please refer to section 3.4.18 for more details.
The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of
the following receiver blocks.
3.4.6. Channel Filter
The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the RF65 is
implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection
performance, even for narrowband applications.
Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value
than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw)
The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw: