Infineon TC1782 Installation and operating instructions

Microcontrollers
.
TC1782 Scalable Pads
Timing and Electromagnetic Emission
A
P32146
A
pplication Note
V1.0 2010-01

Edition 2010-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
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AP32146
TC1782 Scalable Pads
Timing and Electromagnetic Emission
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Application Note 3 V1.0, 2010-01

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TC1782 Scalable Pads
Timing and Electromagnetic Emission
Table of Contents
1Preface ................................................................................................................................................5
2Introduction ........................................................................................................................................6
2.1 Pad driver scaling in detail...................................................................................................................6
2.2 Physical basics.....................................................................................................................................7
2.2.1 Load charging.......................................................................................................................................7
2.2.2 Signal integrity......................................................................................................................................8
2.2.3 Power integrity / Electromagnetic emission.......................................................................................12
3TC1782 test configuration...............................................................................................................14
4Specified timings .............................................................................................................................16
5Measured timings.............................................................................................................................17
5.1 Measurement conditions and naming conventions............................................................................17
5.2 Measured rise/fall times for Class A1 drivers.....................................................................................20
5.3 Measured rise/fall times for Class A1+ drivers...................................................................................21
5.4 Measured rise/fall times for Class A2 drivers.....................................................................................23
5.5 Rise/fall time diagrams for Class A1 drivers......................................................................................26
5.6 Rise/fall time diagrams for Class A1+ drivers....................................................................................27
5.7 Rise/fall time diagrams for Class A2 drivers......................................................................................29
5.8 Rise/fall time diagrams for increased capacitive loads......................................................................33
6Measured electromagnetic emission.............................................................................................37
6.1 Microcontroller operation mode..........................................................................................................37
6.2 Description of test equipment.............................................................................................................41
6.2.1 Conducted emission test configuration..............................................................................................41
6.2.2 Radiated emission test configuration.................................................................................................41
6.2.3 Measurement settings........................................................................................................................42
6.3 Emission test result discussion..........................................................................................................43
7Recommended pad driver settings................................................................................................51
7.1 Signal categories................................................................................................................................51
7.2 Decision tables and diagrams............................................................................................................52
7.2.1 Decision table for pad class A2..........................................................................................................55
7.2.2 Decision table for pad class A1+........................................................................................................57
7.2.3 Decision table for pad class A1..........................................................................................................59
7.2.4 Decision diagrams for pad class A2...................................................................................................60
7.2.5 Decision diagrams for pad class A1+.................................................................................................65
7.2.6 Decision diagrams for pad class A1...................................................................................................70
7.2.7 Decision diagrams for weak driver at high capacitive load................................................................75
7.2.8 Decision diagrams for medium driver at high capacitive load............................................................80
8Pad Scaling Calculator (PASTOR)..................................................................................................85
8.1 Scope of the software ........................................................................................................................85
8.2 How to use PASTOR .........................................................................................................................85
8.3 PASTOR screenshots........................................................................................................................86
Annex A: Measured rise/fall waveforms............................................................................................................90
Annex B: Glossary.............................................................................................................................................150
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Timing and Electromagnetic Emission
1 Preface
Output driver scaling, also referred to as „slew rate control“, is an effective technique to reduce the
electromagnetic emission and improve the signal integrity of an integrated circuit by reducing the driver strength
and/or smoothing the rising and falling edges of one or more pad output drivers.
Output driver scaling makes sense only when a certain margin regarding signal frequency and/or capacitive
output load is available. Any driver scaling must maintain proper signal integrity.
This application note presents a huge set of output driver characterization data plus a special software, which
shall enable the system designers to select proper driver settings to reduce the electromagnetic emission
caused by the driver switching, while maintaining the desired signal integrity. Parameters under consideration
are switching frequency, capacitive output load, pad supply voltage and ambient temperature.
Chapter 2 introduces physical basics behind the scaling.
Chapter 3 describes the TC1782 software initialization for timing and emission measurements.
Chapter 4 lists all specified timings which have been validated by measurements as documented in this
application note.
Chapter 5 provides values and comparison diagrams of measured rise/fall times under various conditions.
Chapter 6 compares several measured electromagnetic emissions under various conditions.
Chapter 7 recommends useful settings for the drivers by introducing signal categories and giving lots of
decision tables and graphs.
Chapter 8 introduces the new Microsoft Excel ™ based software PASTOR, which calculates pad driver timings
under various environmental conditions and proposes the best driver scaling under timing, EMC, load, voltage
and temperature constraints.
Annex A shows the waveforms of all measured rise/fall times.
Annex B explains all abbreviations used in this application note in a glossary.
Guideline to use this application note:
In most cases an appropriate driver setting is searched for,
based on a given signal data rate, a given capacitive load
connected to this signal, and a given maximal ambient
temperature. As a solution, the diagrams given in Chapter 7
provide the required pad driver settings. These suitable pad
driver settings lead to minimum electromagnetic emission
under the given constraints for data rate, capacitive load,
and operating temperature.
In addition, the measured values of rise and fall times for all
driver settings listed in the decision diagrams can be
referred in Chapter 5.
The impact of driver settings on electromagnetic emission
can be estimated from the diagrams in Chapter 5.
Annex A and B serve as data pool for detailled timing and
electromagnetic emission behaviour for all pad driver
settings under various temperature and capacitve load
conditions. Note that emissions are always measured at
room temperature (25°C).
Figure 1: 32-bit microcontroller TC1782
Important notes:
The information given in this application note is valid for Infineon microcontrollers of the AudoMax family,
fabricated in 90 nm CMOS technology.
Please note that all numbers given in this application note are not guaranteed in the microcontroller data
sheets. They are verified by design without being monitored during the IC fabrication process. The numbers are
based on timing measurements performed on center lot devices. Fabrication process windows may lead to
deviations of below 10%.
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Timing and Electromagnetic Emission
2 Introduction
The output driver scaling principle of the
TC1782 microcontroller is shown in Figure 2.
The driver configuration is possible by setting
corresponding control bits in the port-related
output control registers.
2.1 Pad driver scaling in detail
Basically, we distinguish between driver control
and edge control. Driver control bits set the
general DC driving capability of the respective
driver. Reducing the driver strength increases
the output’s internal resistance which attenuates
noise that is imported/exported via the output
line.
For a given external load, charging and
discharging time varies with the driver strength,
thus the rise/fall times will change accordingly.
For the sake of low electromagnetic emission,
low-speed signals should be driven by weak
output drivers. However, high DC-current sinks
like LEDs or power transistors may require a
stable high output current (strong driver)
although the toggle rate is very low.
The controllable output drivers of the TC1782
pins feature three differently sized transistors
(strong, medium, and weak) for each direction
(push and pull). The time of
activating/deactivating these transistors
determines the output characteristics of the
respective port driver.
The strength of the driver can be selected to
adapt the driver characteristics to the
application’s requirements:
In Strong Driver Mode, the medium and strong
transistors are activated. In this mode the driver
provides maximum output current even after the
target signal level is reached.
In Medium Driver Mode, only the medium
transistor is activated while the other transistors
remain off.
In Weak Driver Mode, only the weak transistor
is activated while the other transistors remain
off. This results in smooth transitions with low
current peaks (and reduced susceptibility for
noise) on the cost of increased transition times,
i.e. slower edges, depending on the capacitive
load, and low static current.
Signal slopes or edges define the rise/fall time
for the respective output, i.e. the output transition time. Soft edges reduce the peak currents that are drawn
when changing the voltage level of an external capacitive load. For a bus interface, however, sharp edges may
still be required. Edge characteristics are controlled by the pad pre-driver which controls the final output driver
stage.
Figure 2: Pad output driver schematic
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2.2 Physical basics
Two main constraints have to be met when deciding for a certain clock driver setting: signal integrity and power
integrity. Signal integrity must be maintained for all signals driven by the microcontroller. Conditions for good
signal integrity are:
- Maximal desired signal frequency is reached.
- Stable-Level-to-Slope ratio is high (at least 2:1, depending on protocol timing).
- High and low signal levels are reached.
- No overshoot or undershoot occurs.
Power integrity must be maintained to ensure proper operation and fulfil EMC requirements. Condititions for
good power integrity are:
- Low RF noise on all power supply domains.
- This is equivalent to low switching noise and low electromagnetic emission.
Both issues will be discussed after a general introduction to capacitive load charging.
2.2.1 Load charging
Generally, a switching transistor output stage delivers charge to its corresponding load capacitance during
rising edge and draws charge from its load capacitance during falling edge. The load capacitance is built by the
signal net (traces) on the PCB and all connected receiver input stages (ASIC input pins). Timing diagrams
normally show the signal’s voltage over time characteristics. However, the resulting timing is a result of the
electrical charge transfer to and from the load capacitance described above. Charge is transferred by flowing
current.
A bigger pad driver means a smaller resistance in the loading path of the external load. Figure 3 shows the load
current and voltage of two examples of pad drivers connected to a load of C=40pF. The strong driver has an
output resistance of 25Ω, the weak driver 50Ω. For times t<0, the output voltage is 0V. At t=0, the load
capacitor C is connected to the target output voltage U=5V via the respective driver pullup transistor. As a
reaction, the load current steps immediately to the value I=U/R. I is bigger for smaller values of R. This means
that the strong driver generates
a bigger current jump and
charges the load capacitor in a
shorter time.
In time domain this leads to
bigger reflections for not
adapted driver impedances.
Since typical trace impedances
range from 60 to 120Ω, a
strong driver with Z=10Ωis
poorly adapted and may cause
big voltage over- and
undershoots. A weak driver with
Z=100Ωmay fit perfectly and
generate a clean voltage
switching signal without over- or
undershoots. These effects are
discussed in chapter 2.2.2.
In frequency domain, the
current peak which is resulting
from the charging of the load
capacitor and from the over- or
undershoots, causes significant
RF energy and thus
electromagnetic emission on
the pad power supply. These
Charging Voltage and Current at 40pF Load
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-2.0E-09 0.0E+00 2.0E-09 4.0E-09 6.0E-09 8.0E-09 1.0E-08
Time [s]
Voltage [V]
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Current [A]
Voltage R=50Ohm Voltage R=25Ohm
Current R=50Ohm Current R=25Ohm
Figure 3: Current-/voltage charging curves for
different driver strengths
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TC1782 Scalable Pads
Timing and Electromagnetic Emission
effects are discussed in chapter 2.2.3.
Not only the pad driver impedance, but also the connected capacitive load determines the electromagnetic
emission amplitudes. Figure 4 illustrates the differences in charging current and voltage between a capacitive
load of 40pF and one of 20pF. In both cases, the driver impedance is set to 50Ω.
As expected, the charging voltage
increases faster for a smaller
load. However, the starting value
of the charging current is only
determined by the driver
impedance and is thus load-
independent. The load affects
only the speed of load current
decrease. It decreases faster if
the load is smaller. This means
on the other hand a bigger di/dt
for smaller loads, resulting in
higer emission for smaller loads.
This disadvantage can be
compensated by chosing a
smaller pad driver, i.e. a weaker
driver setting, causing bigger
driver impedance and thus
smaller di/dt for the charging
current.
The selection of a weaker driver
setting slows down the pad
switching time, so care must be
taken to maintain the required
signal integrity.
Charging Voltage and Currentat50OhmDriver Impedance
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-2.0E-09 0.0E+00 2.0E-09 4.0E-09 6.0E-09 8.0E-09 1.0E-08
Time [s]
Voltage [V]
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Current [A]
Voltage Cload=40pF Voltage Cload=20pF
Current Cload=40pF Current Cload=20pF
Figure 4: Current-/voltage charging curves for
different capacitive loads
2.2.2 Signal integrity
Maintaining signal integrity means to select the rise/fall times such that all signal handshaking and data
communication timings and levels are ensured for proper system operation. This means the data interchange
between the microcontroller and external ICs (e.g. Flash memory, line drivers, receivers) runs properly.
Therefore, it has to be taken into account that CMOS transistors become slower with rising temperature. Thus
the timing of a critical signal has to be matched for proper operation at highest ambient temperature.
Depending on the application, common ambient temperature ranges are up to 85°C or up to 125°C. Several
automotive control units specify an ambient temperature range from -40°C up to 140°C. The die temperature
may reach values above 150°C during operation.
Rules:
•Choose driver characteristics to meet the DC driving requirements. Make sure that the DC current
provided by the microcontroller’s pad drivers is sufficient to drive e.g. actuators or LEDs into the
desired logic state.
•Choose slope settings to meet system timing constraints at the highest system temperature. Make sure
that no too strong driver settings are selected. This would lead to unnecessarily fast signal edges,
causing two disadvantages regarding electromagnetic emission: (1) The slopes are too fast and cause
undesired high emission energy at higher frequencies; (2) Over- and undershoot appears with the
danger of latchup, spikes leading to wrong logic states or increased data delays and undesired high
frequency emission.
•If system timing requires strong drivers, consider series termination to avoid over-/undershoot at signal
transitions. The value of the termination resistor has to be chosen according the signal line impedance.
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Timing and Electromagnetic Emission
The following examples describe the signal integrity issues mentioned above.
Let us assume a CMOS push/pull output driver with scalable driver impedance connected to a scalable
microstrip trace on the PCB terminated by a reveiver input pin. The driver is controlled by a periodically toggling
clock with 2ns slopes at different frequencies.
This simple circuit is shown in Figure 5.
Figure 5: Signal over- and undershoots
Let us further assume the following system settings:
Driver scaling Microstrip scaling Clock rate scaling
Driver name Impedance Zdr
Strong-sharp 20Ω2cm long 1MHz
Strong-medium 50Ω5cm long 10MHz
Strong-soft 100Ω10cm long 100MHz
Medium 200Ω20cm long -
Weak 1000Ω- -
Please note that the “driver names” for these examples have been selected according the driver settings
implemented in the TC1782. Nevertheless, the signal shapes and timings shown in Figures 6 to 11 are based
on the simple model of Figure 5 and thus not identical to the physical realization of these drivers. For signal
shapes and signal integrity discussion of the real physical TC1782 drivers please refer to chapters 5 and 7 and
Annex A.
Figures 6, 7, 8 show the driver scaling impact on signal integrity. Stronger drivers may cause signal over- and
undershoot. Figures 9, 10, 11 show the PCB trace length impact. Driver strength should be selected to be as
weak as possible to avoid over/undershoot. Of course any timings required by communication protocols must
be maintained. Typically, weak driver settings can be used for signals up to 1MHz. Medium settings are valid
for signals in the low MHz range, whereas faster signals need strong drivers. Infineon microcontrollers refine
their strong drivers by slew-rate control like sharp/medium/soft edge, thus providing a fine tuning capability in
the high signal performance class which is especially critical for electromagnetic emission.
Figure 6: A 1MHz clock can be driven by a weak or medium driver. Any strong driver should be avoided due to
unnecessary over- and undershoots and higher electromagnetic emission.
Figure 7: A 10MHz signal cannot anymore be driven by a weak driver since the final high and low levels are
hardly reached in time. The medium driver may be possible in the shown case of a 10cm long PCB trace.
Depending on the communication protocol’s timing requirements, the strong-soft driver may be preferred due to
its slightly faster slopes. Strong-medium and strong-sharp drivers are not recommended due to resulting over-
and undershoot.
Figure 8: Depending on the protocol’s timing constraints, either strong-medium or strong-sharp drivers must be
used. Strong-sharp still has significant over- and undershoots, thus offers worse signal integrity, but has
steeper slopes.
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Timing and Electromagnetic Emission
Figure 6: Signal integrity for various driver settings at 1MHz clock signal
Figure 7: Signal integrity for various driver settings at 10MHz clock signal
Figure 8: Signal integrity for various driver settings at 100MHz clock signal
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Figure 9: The PCB trace length determines the signal integrity significantly. Longer traces lead to increased
over- and undershoot due to the larger inductive and capacitive components of the trace according the
transmission line theory. This ringing effect caused by the trace length is superimposed to the ringing effect
caused by strong drivers with steep slope which was discussed in Figures 6 to 8. The strong-sharp driver
shown in Figure 9 causes significant ringing on traces longer than 5cm.
Figure 10: For strong-medium driver, the ringing is significantly reduced and the timing even for 100MHz clocks
is good up to 10cm long traces.
Figure 11: The strong-soft driver is the preferred choice for signals up to 10MHz. It cannot be used for 100MHz
clocks because due to the long slopes the target signal levels are never reached.
Figure 9: Signal integrity for strong-sharp driver at various microstrip line lengths
Figure 10: Signal integrity for strong-medium driver at various microstrip line lengths
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Timing and Electromagnetic Emission
Figure 11: Signal integrity for strong-soft driver at various microstrip line lengths
2.2.3 Power integrity / Electromagnetic emission
Any switching between low and high voltage levels generates RF noise. Responsible for this electromagnetic
energy is the dynamic current which is required to charge and discharge a lot of on-chip and off-chip nodes. In
the logic core power supply domain of a microcontroller, the millions of transistors switching nearly
simultaneously – triggered by the synchronous clock – draw lots of dynamic current from on-chip capacitors,
decoupling capacitors on
the PCB and finally the
voltage regulator or
battery “somewhere” in
the system. Preferrably,
most of this dynamic
switching current should
be provided by the on-
chip capacitors because
in that case, only a small
part of high frequency
energy is propagated
over the PCB, where it is
efficiently radiated. If a
good RF decoupling
concept has been
implemented on the PCB
(i.e. decoupling
capacitors place close to
the microcontroller’s
power supply pins), most
of the RF current is kept
within small loops on the PCB.
Figure 12: Spectrum envelope for different clocks and edges
For the I/O domain, the switching currents are drawn by the pad drivers. In contrast to the logic core domain, no
on-chip capacitors can be implemented on the microcontroller due to very limited area of the pad frame. For the
I/O domain, a very good external decoupling concept must be implemented on the PCB. Nevertheless, the
electromagnetic emission caused by pad drivers can in most application cases significantly reduced by using
weaker drivers. This driver selection is done by software as explained in section 2.1. From theory, the
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Timing and Electromagnetic Emission
electromagnetic emission (EME) of trapezoidal pulses (as are typical clock waveforms) is determined by the
signal frequency and the signal slopes. In the emission spectrum, the limit curve is determined by two
kneepoints which separate the limit curve in damping sections of 0dB/decade, -20dB/decade and
-40dB/decade. Figure 12 shows the kneepoint frequencies for several cases of clock frequency and clock
edges (i.e. rise/fall times). Good signal integrity is assumed when the rise and fall time takes 10% of one clock
period. Any faster edge will not improve signal integrity significantly, but leads to heavily shited damping
kneepoints towards higher frequency – see the 1ns egde examples in Figure 12.
The steeper a switching pulse is, the higher frequencies (harmonics) are required to form the rising and falling
edges. A rise time of 1ns leads to a spectrum composed from harmonics up to at least 500 MHz.
Assuming a 100MHz (10ns period) clock signal consisting of 10% rise time, 40% high level, 10% fall time and
40% low level, this clock signal already generates at least harmonics up to 500MHz.
Figure 12 indicates that not the clock frequency, but the rise/fall times determine the resulting RF spectrum.
Even if a clock driver operates at a relatively low toggle rate, it may generate the same RF spectrum as if it
would operate at a significantly higher toggle rate – as long as its rise/fall times are not adjusted to the lower
toggle rate by slowing down the transitions. For example, if the mentioned 100MHz clock driver operates at
only 10 MHz, its rise/fall times should be extended from 1 ns to 10 ns, still maintaining the 10% ratio relatively
to the clock period time. This setting will reduce the emission by 10dB at 50MHz and by more than 30dB above
300MHz.
•General Rule: Choose driver and edge characteristics to result in lowest electromagnetic emission
while meeting all system timing requirements (i.e. good signal integrity) at given signal load and highest
system temperature.
Figure 13 refers to our pad driver and transmission line simulation model of Figure 5. It shows the simulated
electromagnetic emission at the probing point “MEAS” which is an AC-coupled test point with resistive divider to
match typical emission scales of up to 80dBµV. Important is the interpretation of relative emission reduction
potential when using weaker pad drivers.
For a 1MHz signal, Figure 6 shows that even the weakest driver delivers acceptable signal integrity. Moreover,
Figure 13 confirms that the weakest driver reduces electromagnetic emission significantly, compared to the
strong and medium settings. At 200MHz, the 1MHz harmonics are reduced by 34dB. At 100MHz, the reduction
is ca. 20dB; above ca. 450MHz, the emission stays below 10dBµV (i.e. is uncritical) for all driver settings.
Figure 13: Electromagnetic emission for various driver settings at 1MHz clock signal
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3 TC1782 test configuration
Timing measurements were performed at 3 pins, representing the 3 pad driver classes:
- Port pin P1.13 = Class A1 pin (low speed 3.3 V LVTTL output)
- Port pin P5.1 = Class A1+ pin (medium speed 3.3 V LVTTL output)
- Port pin P2.0 = Class A2 pin (high speed 3.3 V LVTTL output)
Electromagnetic emission measurements were performed on the I/O supply net VDDP.
Roughly, these settings can be linked to driven data rates, as documented in Chapter 7. Note that the actual
data rate which can be driven by the selected driver depends on additional parameters like external capacitive
load, pad supply voltage and ambient temperature.
The driver settings for the respective port pins are configured by bit fields PDx in the Port Driver Mode Register,
see Table 1.
Px_PDR
Port x Pad Driver Mode Register (F000 0C40H+x*100H) Reset Value: 0000 0000H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 PD7 0PD6 0PD5 0PD4
r rw r rw r rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 PD3 0PD2 0PD1 0PD0
r rw r rw r rw r rw
Field Bits Type Description
[2:0] rw
PD0 Pad Driver Mode for Px.[3:0]
(Class A1 or A2 pads; coding see Table 2)
[6:4] rw
PD1 Pad Driver Mode for Px.[7:4]
(Class A1 or A2 pads; coding see Table 2)
[10:8] rw
PD2 Pad Driver Mode for Px.[11:8]
(Class A1 or A2 pads; coding see Table 2)
[14:12] rw
PD3 Pad Driver Mode for Px.[15:12]
(Class A1 or A2 pads; coding see Table 2)
[18:16] rw
PD4 Pad Driver Mode for Px.[19:16]
(not used for 16-bit ports)
[22:20] rw
PD5 Pad Driver Mode for Px.[23:20]
(not used for 16-bit ports)
[26:24] rw
PD6 Pad Driver Mode for Px.[27:24]
(not used for 16-bit ports)
[30:28] rw
PD7 Pad Driver Mode for Px.[31:28]
(not used for 16-bit ports)
r3, 7, 11,
0 Reserved
15, 19, Read as 0; should be written with 0.
23, 27, 31 Table 1: Pad driver mode register specification
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Driver strength and slew rate are controlled by the bit fields in the pad driver mode register Px_PDR,
independently of input/output and pull-up/pulldown control functionality as programmed in the Pn_IOCRx
register. One Px_PDR register is assigned to each port.
Depending on the assigned pad class, the 3-bit wide pad driver mode selection bit fields PDx in the pad driver
mode registers Px_PDR make it possible to select the port line functionality as shown in Table 2:
- Class A1 pins make it possible to select between medium and weak output drivers.
- Class A1+ and A2 pins make it possible to select between strong/medium/weak output drivers. In case
of strong driver type, the signal transition edge can be additionally selected as soft/slow (Class A1+) or
sharp/sharp-minus/medium/medium-minus/soft (Class A2).
For details on the register structure and bit configurations please refer to the TC1782 specification.
Pad Class PDx.2 PDx.1 PDx.0 Driver Strength
0 Medium driverA1 X X
1 Weak driver
0 X 0 Strong driver soft edge
0 X 1 Strong driver slow edge
A1+
1 X 0 Medium driver
1 X 1 Weak driver
0 0 0 Strong driver, sharp edge
0 0 1 Strong driver, medium edge
A2
0 1 0 Strong driver, soft edge
0 1 1 Strong driver, sharp-minus edge
1 0 X Medium driver selected
1 0
1 1 0 Strong driver, medium-minus edge
1 1 1 Weak driver selected
Table 2: Pad Driver Mode Selection
Please note that sometimes Class A1+ and A2 drivers share the same configuration bits, thus the driver and
slew rate settings are not anymory fully individual. For these cases Table 3 lists the resulting combinations of
settings.
For details on the driver class distribution per bit please refer to the TC1782 specification.
PDx.2 PDx.1 PDx.0 A2 Driver Strength A1+ Driver Strength
0 0 0 Strong sharp Strong soft
0 0 1 Strong medium Strong slow
0 1 0 Strong soft Strong soft
0 1 1 Strong sharp-minus Strong slow
1 0 0 Medium Medium
1 0 1 Medium Weak
1 1 0 Strong medium-minus Medium
1 1 1 Weak Weak
Table 3: Possible Driver Strength Combinations in a Mixed Pad Group (A1+ and A2)
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TC1782 Scalable Pads
Timing and Electromagnetic Emission
4 Specified timings
Rise/fall times are specified for the TC1782 operating conditions: TJ< 150°C and VDDP = 3.3 V ± 5%.
A junction temperature TJof 150°C corresponds to an ambient temperature of TA< 140°C. The rise/fall times
documented in chapter 5 have been characterized for ambient temperatures up to 140°C, thus fully covering
the specified operating range. In addition, worst and best case results including ± 5% variation of VDDP are
provided.
For details please refer to the TC1782 product specification.
Class Pad driver Load condition Max. specified value
A1 Weak 20 pF 90 ns
A1 Weak 150 pF 350 ns
A1 Weak 20000 pF 50000 ns
A1 Medium 50 pF 40 ns
A1 Medium 150 pF 110 ns
A1 Medium 20000 pF 15000 ns
A1+ Weak 20 pF 90 ns
A1+ Weak 150 pF 350 ns
A1+ Weak 20000 pF 50000 ns
A1+ Medium 50 pF 40 ns
A1+ Medium 150 pF 110 ns
A1+ Medium 20000 pF 15000 ns
A1+ Strong slow 50 pF 28 ns
A1+ Strong soft 50 pF 16 ns
A2 Weak 20 pF 90 ns
A2 Weak 150 pF 350 ns
A2 Weak 20000 pF 50000 ns
A2 Medium 50 pF 40 ns
A2 Medium 150 pF 110 ns
A2 Medium 20000 pF 15000 ns
A2 Strong soft 50 pF 16 ns
A2 Strong medium minus 50 pF 10 ns
A2 Strong medium 50 pF 5.5 ns
A2 Strong sharp minus 50 pF 4.4 ns
A2 Strong sharp 50 pF 3.3 ns
B Strong sharp 35 pF 2.5 ns *
B Strong sharp 50 pF 3.3 ns *
B Strong sharp 100 pF 6 ns *
* for I/O supply voltage VDDP ≥3.13V
Application Note 16 V1.0, 2010-01

AP32146
TC1782 Scalable Pads
Timing and Electromagnetic Emission
5 Measured timings
5.1 Measurement conditions and naming conventions
The test configuration listed in chapter 3 applies. Accordingly, all timings are measured at pins P1.13 (Class
A2), P5.1 (Class A1+) and P2.0 (Class A2).
The following parameters are varied for timing measurements to reflect the PVT (process, voltage,
temperature) variations anticipated during fabrication and operation:
•Pad supply voltage VDDP in 3 steps: 3.30V (nominal), 3.13V (-5%), 3.47V (+5%).
•Capacitive load according TC1782 specification in 8 steps for weak and medium drivers:
10pF, 15pF, 22pF, 33pF, 47pF, 150pF, 1500pF, 20000pF
•Capacitive load according TC1782 specification in 6 steps for strong-sharp drivers:
10pF, 15pF, 22pF, 33pF, 47pF, 100pF
•Capacitive load according TC1782 specification in 5 steps for all strong driver settings except strong-
sharp: 10pF, 15pF, 22pF, 33pF, 47pF
•Ambient emperature in 6 steps: -40°C, 0°C, +25°C, +40°C, +80°C, +125°C
•For rise/fall time values at other temperatures, a linear interpolation is performed.
•Electromagnetic emission is always measured at TA=25°C.
The pad driver is loaded with the respective capacitance by connecting a lumped SMD 0805 X7R capacitor to
the port pin. The port pin is driven by either a Class A1, Class A1+ or Class A2 pad driver.
Please note that the measurement probe capacitance of 3pF must be added to the nominal load capacitors.
Therefore, total capacitance values of 13pF up to 50pF are reached. Table 4 shows the reference between real
loads and numbers given in the result diagrams. For easy reading, in all result tables and diagrams, the load
capacitances are referring to the SMD capacitor values as 10, 15, 22, 33, 47pF.
SMD load Probe ca
p
acitance Resultin
g
p
h
y
sical ca
p
acitance
10
p
F 3
p
F13
p
F
15
p
F 3
p
F18
p
F
22
p
F 3
p
F25
p
F
33
p
F 3
p
F36
p
F
47
p
F 3
p
F 50
p
F
>50 pF 3 pF Respective load value +3 pF
(may be neglected for large values)
Table 4: Overview of capacitive loads used for timing measurements
Application Note 17 V1.0, 2010-01

AP32146
TC1782 Scalable Pads
Timing and Electromagnetic Emission
Figure 14: Voltage level references for timing measurement at VDDP=3.3V
The results given in Tables 6-8 and in the diagrams of sections 4.5 to 4.8 show the measured rising and falling
edge timings. The reference points are 10% and 90% as indicated in Figure 14.
Table 5 lists all parameter variations and test names for reference. These test names are used to indicate the
driver settings and load configurations used in sections 4.5 to 4.8 4. All measurements have been performed
for VDDP=3.30V at ambient temperatures TA=-40°C, 0°C, 25°C, 40°C, 80°C and 125°C. Rise and fall time
values for other temperatures are calculated by interpolation (70°C, 85°C, 110°C) and extrapolation (140°C).
Application Note 18 V1.0, 2010-01

AP32146
TC1782 Scalable Pads
Timing and Electromagnetic Emission
Application Note 19 V1.0, 2010-01
Test Name Driver strength Lumped load capacitance Class A1 Class A1+ Class A2
WEA-10pF Weak 10pF X X X
WEA-15pF Weak 15 pF X X X
WEA-22pF Weak 22 pF X X X
WEA-33pF Weak 33 pF X X X
WEA-47pF Weak 47 pF X X X
WEA-150pF Weak 150 pF X X X
WEA-1500pF Weak 1500 pF X X X
WEA-20nF Weak 20000 pF X X X
MED-10pF Medium 10pF X X X
MED-15pF Medium 15 pF X X X
MED-22pF Medium 22 pF X X X
MED-33pF Medium 33 pF X X X
MED-47pF Medium 47 pF X X X
MED-150pF Medium 150 pF X X X
MED-1500pF Medium 1500 pF X X X
MED-20nF Medium 20000 pF X X X
SSL-10pF Strong-slow 10pF X
SSL-15pF Strong-slow 15 pF X
SSL-22pF Strong-slow 22 pF X
SSL-33pF Strong-slow 33 pF X
SSL-47pF Strong-slow 47 pF X
SSO-10pF Strong-soft 10pF X X
SSO-15pF Strong-soft 15 pF X X
SSO-22pF Strong-soft 22 pF X X
SSO-33pF Strong-soft 33 pF X X
SSO-47pF Strong-soft 47 pF X X
SMM-10pF Strong-medium-minus 10pF X
SMM-15pF Strong-medium-minus 15 pF X
SMM-22pF Strong-medium-minus 22 pF X
SMM-33pF Strong-medium-minus 33 pF X
SMM-47pF Strong-medium-minus 47 pF X
SME-10pF Strong-medium 10pF X
SME-15pF Strong-medium 15 pF X
SME-22pF Strong-medium 22 pF X
SME-33pF Strong-medium 33 pF X
SME-47pF Strong-medium 47 pF X
SSM-10pF Strong-sharp-minus 10pF X
SSM-15pF Strong-sharp-minus 15 pF X
SSM-22pF Strong-sharp-minus 22 pF X
SSM-33pF Strong-sharp-minus 33 pF X
SSM-47pF Strong-sharp-minus 47 pF X
SSH-10pF Strong-sharp 10pF X
SSH-15pF Strong-sharp 15 pF X
SSH-22pF Strong-sharp 22 pF X
SSH-33pF Strong-sharp 33 pF X
SSH-47pF Strong-sharp 47 pF X
SSH-100pF Strong-sharp 100 pF X
Table 5: Abbreviations used in the timing result diagrams

AP32146
TC1782 Scalable Pads
Timing and Electromagnetic Emission
Application Note 20 V1.0, 2010-01
Sections 5.2 to 5.4 list the measured 10% / 90% rise and fall times of all driver, load and ambient temperature
conditions, while the I/O supply is kept at nominal value VDDP=3.30V. The last row in every table (section 5.2)
lists the slowest measured rise/fall times under worst case conditions (VDDP = 3.30V-5% = 3.13V; TA=140°C).
The related waveforms are presented in Annex A.
Sections 5.5 to 5.8 show the measured rise/fall times for different combinations of ambient temperature and
capacitive load.
5.2 Measured rise/fall times for Class A1 drivers
A1 WEAK CL=10pF CL=15pF CL=22pF CL=33pF CL=47pF
TA(°C) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns)
-40 30,93 38,55 39,85 46,46 41,53 48,01 51,34 55,26 67,00 66,70
0 34,41 42,60 44,46 51,10 45,94 52,67 56,36 60,70 73,23 72,86
+25 36,96 45,07 47,38 54,03 48,60 55,76 59,37 64,06 76,02 76,59
+40 38,21 47,44 49,25 56,27 50,47 57,84 61,30 66,55 78,74 79,08
+80 42,00 52,15 53,62 62,25 55,52 63,72 68,19 73,41 84,99 86,71
+125 46,82 55,23 59,41 67,77 61,54 70,31 75,29 79,50 94,29 95,64
+140 48,43 56,26 61,34 69,61 63,55 72,51 77,66 81,53 97,39 98,62
WORST CASE 49,63 62,09 62,09 71,87 64,26 73,99 79,27 86,19 99,90 100,95
SPEC 150
A1 WEAK CL=150pF CL=1500pF CL=20000pF
TA(°C) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns)
-40 156 129 1290 845 17800 11310
0 170 138 1390 911 18990 12030
[phone] 19120 12380
[phone] 19760 12840
[phone] 1030 20990 13680
[phone] 1110 22260 14890
[phone] 1137 22680 15290
WORST CASE 221 185 1763 1170 23310 15487
SPEC 550 65000
A1 MEDIUM CL=10pF CL=15pF CL=22pF CL=33pF CL=47pF
TA(°C) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns) tR(ns) tF(ns)
-40 10,50 11,80 13,53 14,11 13,39 14,51 16,37 16,73 21,61 20,17
0 11,21 12,81 14,51 15,42 14,83 16,01 18,11 18,43 23,41 21,91
+25 12,01 13,57 15,31 16,12 15,53 16,50 19,05 19,54 24,33 22,75
+40 12,49 14,30 15,87 16,87 16,32 17,25 19,47 19,91 25,05 23,68
+80 13,89 15,68 17,69 18,48 17,81 18,97 21,27 21,78 27,12 25,83
+125 15,29 17,29 19,53 20,41 19,37 20,79 23,58 24,12 29,44 28,26
+140 15,76 17,83 20,14 21,05 19,89 21,40 24,35 24,90 30,21 29,07
WORST CASE 16,72 18,57 20,51 21,64 20,64 22,11 25,67 25,96 31,02 29,98
SPEC
50
Table 6: Pad driver class A1 – measured rise and fall times (first part)