Infinite Pasternack PE11S100 Series User manual

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc.
User Manual
PE11S100X SERIES
Synthesizer
Pasternack
PO Box 16759, Irvine, CA 92623
Phone: [phone] or [phone]
Fax: [phone]
[e-mail] | [e-mail]

User Manual | PE11S100X Series Synthesizer
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Notices
© Pasternack 2013
No part of this manual may be reproduced in any form or by any means (including electronic storage and
retrieval or translation into a foreign language) without prior permission and written consent from Pasternack
as governed by United States and international copyright laws.
Manual Part Number
PE11S100X SERIES
Edition
Revision 1.1, May 2019
Printed in the USA Pasternack
17802 Fitch Irvine, CA 92614 USA
Trademark Acknowledgements
Windows is a U.S. registered trade- mark of Microsoft Corporation.
Warranty
The material contained in this document is provided "as is," and is subject to be changed, without notice,
in future editions. Further, to the maximum extent permitted by applicable law, Pasternack disclaims all
warranties, either expressed or implied, with regard to this manual and any information contained herein,
including but not limited to the implied warranties of merchantability and fitness for a particular purpose.
Pasternack shall not be liable for errors or incidental or consequential damages in connection with the
furnishing, use, or performance of this document or of any information contained herein. Should Pasternack
and the user have a separate written agreement with warranty terms covering the material in this document
that conflict with these terms, the warranty terms in the separate agreement shall control.
Technology Licenses
The hardware and/or software described in this document are furnished under a license and may be used
or copied only in accordance with the terms of such license.
Restricted Rights Legend
U.S. Government Restricted Rights. Software and technical data rights granted to the federal government
include only those rights customarily provided to end user customers. Pasternack provides this customary
commercial license in Software and technical data pursuant to FAR 12.211 (Technical Data) and 12.212
(Computer Software) and, for the Department of Defense, DFARS 252.227-7015 (Technical Data –
Commercial Items) and DFARS 227.7202-3 (Rights in Commercial Computer Software or Computer
Software Documentation).

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 3
Safety Notices
Personal Safety Considerations
This is a Safety Class I product (provided with a protective earthing ground incorporated in the power cord).
The mains plug shall only be inserted in a socket outlet provided with a protective earth contact. Any
interruption of the protective conductor, inside or outside the product, is likely to make the product
dangerous. Intentional interruption is prohibited. If this product is not used as specified, the protection
provided by the equipment could be impaired. This product must be used in a normal condition (in which
all means of protection are intact) only.
No operator serviceable parts inside. Refer servicing to qualified personnel. To prevent electrical shock, do
not remove covers. For continued protection against fire hazard, replace the line fuse(s) only with fuses of
the same type and rating (for example, normal blow, time delay, etc.). The use of other fuses or material is
prohibited.
General Safety Information
The following general safety precautions must be observed during all phases of operation of this product.
Failure to comply with these precautions or with specific warnings elsewhere in this manual or any manual
associated with this product violates safety standards of design, manufacture, and intended use of the
product. Pasternack assumes no liability for the customer’s failure to comply with these requirements.
BEFORE APPLYING POWER TO THIS PRODUCT OR MAKING ANY CONNECTIONS TO THIS
PRODUCT ensure that all instruments are connected to the protective (earth) ground. Any interruption of
the protective earth grounding will cause a potential shock hazard that could result in personal injury or
death.
● Use this device with the cables provided.
● Do not attempt to service this device. This device should be returned to Pasternack for any
service or repairs.
● Do not open the device.
WARNING
CAUTION

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User Environment
This instrument is designed for indoor use only.
Revision Control
Revision
Description of Changes
Date
1.0
Initial Creation
08/18/2011
1.1
Pasternack Updates
05/13/2019
Acronyms
PPL
Phase Lock Loop
SCPI
Standard Commands for Programmable Instrumentation

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 5
Contents
Notices ..........................................................................................................................................................2
Manual Part Number..............................................................................................................................................2
Edition ......................................................................................................................................................................2
Trademark Acknowledgements............................................................................................................................2
Warranty........................................................................................................................................................2
Technology Licenses.............................................................................................................................................2
Restricted Rights Legend......................................................................................................................................2
Safety Notices...............................................................................................................................................3
Personal Safety Considerations...........................................................................................................................3
General Safety Information...................................................................................................................................3
User Environment...................................................................................................................................................4
Revision Control............................................................................................................................................4
Acronyms ......................................................................................................................................................4
1.0 Applicable Products ................................................................................................................................8
2.0 General Description ................................................................................................................................8
3.0 Reference Input.......................................................................................................................................8
4.0 Basic Operation.......................................................................................................................................9
4.1 Initialization.......................................................................................................................................................9
4.2 Frequency Tuning............................................................................................................................................9
4.3 Frequency Hopping.........................................................................................................................................9
4.4 CW Sweeper Mode .......................................................................................................................................10
4.4.1 One-Way Sweeps.......................................................................................................................................10
4.4.2 Two-Way Sweeps.......................................................................................................................................11
4.4.3 Single Step Ramp Mode............................................................................................................................12
4.4.4 Ramp Busy..................................................................................................................................................12
4.4.5 Autosweep Mode........................................................................................................................................13
4.5 Charge Pump .................................................................................................................................................13
4.5.1 Charge Pump Gain.....................................................................................................................................13
4.5.2 Charge Pump Gain Trim............................................................................................................................13
4.5.3 Charge Pump Phase Offset......................................................................................................................13
4.5.4 Charge Pump Operation Near the Minimum & Maximum Output Frequency...................................14
4.6 Power On Reset (POR) ................................................................................................................................14
4.6.1 Soft Reset....................................................................................................................................................14
4.6.2 Power Down................................................................................................................................................14

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5.0 Serial Port .............................................................................................................................................14
5.1 Serial Port WRITE Operation.......................................................................................................................15
5.2 Main Serial Port READ Operation...............................................................................................................15
6.0 Advanced Operation .............................................................................................................................16
6.1 Cycle Slip Prevention (CSP) ........................................................................................................................16
6.2 PFD Jitter & Lock Detect Background........................................................................................................17
6.3 PFD Lock Detect............................................................................................................................................19
6.4 Lock Detect with Phase Offset.....................................................................................................................20
7.0 Register Map.........................................................................................................................................20
7.1 Reg 00h Chip ID (Read Only) Register......................................................................................................20
7.2 Reg 00h Strobe (Write Only) Register........................................................................................................21
7.3 Reg 01h Enable & Reset Register ..............................................................................................................21
7.4 Reg 02h Serial Data Out Force Register....................................................................................................21
7.5 Reg 03h Reserved.........................................................................................................................................22
7.6 Reg 04h Prescaler Duty Cycle Register.....................................................................................................22
7.7 Reg 05h Reserved.........................................................................................................................................22
7.8 Reg 06h Phase Freq Detector Delay Register..........................................................................................22
7.9 Reg 07h Charge Pump UP/DN Control Register......................................................................................22
7.10 Reg 08h Charge Pump Trim & Offset Register.......................................................................................22
7.11 Reg 09h Charge Pump EN Register.........................................................................................................23
7.12 Reg 0Ah Reserved......................................................................................................................................23
7.13 Reg 0Bh Reserved......................................................................................................................................23
7.14 Reg 0Ch Reserved......................................................................................................................................23
7.15 Reg 0Dh Reserved......................................................................................................................................23
7.16 Reg 0Eh Reserved......................................................................................................................................24
7.17 Reg 0Fh Integer Division Register............................................................................................................24
7.18 Reg 10h Fractional Division Register.......................................................................................................24
7.19 Reg 11h Speed Register............................................................................................................................24
7.20 Reg 12h Delta Sigma Modulator Register ...............................................................................................24
7.21 Reg 13h Reserved.......................................................................................................................................25
7.22 Reg 14h CW Sweep Control Register......................................................................................................25
7.23 Reg 15h CW Sweep Ramp Step Register...............................................................................................25
7.24 Reg 16h CW Sweep Ramp Step Number Register................................................................................26
7.25 Reg 17h CW Sweep Dwell Time Register...............................................................................................26
7.26 Reg 18h Reserved.......................................................................................................................................26

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7.27 Reg 19h Reserved.......................................................................................................................................26
7.28 Reg 1Ah Lock Detect Register ..................................................................................................................26
7.29 Reg 1Bh GPO Control Register.................................................................................................................27
7.30 Reg 1Ch Phase Detector CSP Register ..................................................................................................28
7.31 Reg 1Dh VCO Tune Port Control Register..............................................................................................28
7.32 Reg 1Eh Temperature Sensor Register...................................................................................................28
7.33 Reg 1Fh LD, VCO & Ramp Busy Read Only Register ..........................................................................29
7.34 Reg 20h Reserved.......................................................................................................................................29
7.35 Reg 21h Temperature Sensor Read Only Register ...............................................................................29
Resources...................................................................................................................................................30
Datasheets ............................................................................................................................................................30
Website..................................................................................................................................................................30
Contacts......................................................................................................................................................31
Customer Support & Sales .................................................................................................................................31

User Manual | PE11S100X Series Synthesizer
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1.0 Applicable Products
PE11S1001, PE11S1002
2.0 General Description
This operating guide applies to the PE11S100X synthesizer modules operating up to 20 GHz output
frequency. The purpose of this guide is to describe features common to all the synthesizer modules.
The PE11S100X synthesizer modules contain phase locked loops consisting of various Pasternack die.
Additionally, the voltage inputs are internally regulated with low dropout linear voltage regulators.
The PE11S100X synthesizer modules features frequency hopping and frequency sweep functions. The
built-in linear sweeper function performs frequency chirps with a wide variety of sweep times, polarities and
dwells, all with an external, automatic or software driven sweep trigger. The external trigger signal is sent
to the module via the GPIO3 pin.
3.0 Reference Input
The crystal reference input stage is shown in Figure 1. This is a common-emitter single-ended bipolar
buffer. Expected input is a 0 dBm sinusoid from a 50 Ohm source. The buffer input impedance is dominated
by a 25 Ohm shunt resistor in series with a 50 pF on-chip capacitor. The reference path phase noise floor
is approximately equivalent to -159 dBc/Hz. For best performance care should be taken to provide a crystal
reference source with equivalent or better phase noise floor.
Figure 1. REFIN Input

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 9
4.0 Basic Operation
4.1 Initialization
The PE11S100X synthesizer does not maintain register states after power down. After power is supplied
to the PE11S100X synthesizer modules, all registers should be loaded with the appropriate values. Default
values for these registers can be found in section 7.1 Register Map on page 22, with instructions for
performing the serial data write operations found in 5.2 Serial Port WRITE Operation on page 15.
4.2 Frequency Tuning
Where:
Nint is the integer division ratio, between 36 and 65531 in fractional mode
between 32 and 65535 in integer mode
Nfrac is the functional division ratio between 0 and 224-1
fREF is the frequency of the reference (fREFIN/R), where fREFIN is the reference
input frequency.
M is the prescaler coefficient for the particular synthesizer
As an example, for a synthesizer with M = 2 and fREF = 10 MHz, the output frequency of 4,600,000,001.19
Hz is achieved using Nint = 230 and Nfrac = 1. These are set by programming the 6-bit binary value of 230d
=00E6h = 0000 0000 1110 0110 into dsm_intg in Reg 0Fh. Similarlythe 24 bit binary value of 1d = 000001h
= 0000 0000 0000 0000 0000 0001 into dsm_frac in Reg 10 h.
In integer mode the synthesizer step size is fixed to M times phase frequency detection (PFD) the reference
frequency, fREF. Integermode typically has lower phase noise for a given reference frequency than fractional
mode. In integer mode the digital ΔΣ modulator is normally shut off. To run in integer mode set
dsm_integer_mode (Reg 12 h<3>) and clear dsm_rstb (Reg 01h<13>). Then program the integer portion
of the frequency, Nint, as explained by (EQ 1), ignoring the fractional part. From the above example,
operation in integer mode would result in a frequency of 4600 MHz.
4.3 Frequency Hopping
If the synthesizer is in fractional mode, a write to the fractional frequency register. Reg 10h will initiate the
frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 5).
If the integer frequency register, Reg 0Fh, is written when in fractional mode, the information will be buffered
and only executed when the fractional frequency register is written.
If the synthesizer is in integer mode, a write to the integer frequency register, Reg 0Fh, will initiate the
frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 5).
f
VCO
= f
REF
•
N
int
•
M +f
REF
•
N
frac
•
M
224
(EQ 1)

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4.4 CW Sweeper Mode
The internal PLL features a built-in frequency sweeper function, useful for test instrumentation, FMCW
sensors, automotive radars, and other applications.
Sweeper modes include:
a. Single-Step Ramp Mode
b. 1-Way Sweep Mode
c. 2-Way Sweep Mode (alternating positive and negative frequency ramps)
The sweep generator is enabled with ramp_enable in Reg 14 h<1>. The sweep function cycles
through a series of discrete frequency values, which may be:
a. Single-stepped by individual triggers if ramp_singlestep (Reg 14 h<6>) is set, or
b. Stepped by an automatic sequencer if ramp_singlestep (Reg 14 h<6>) is cleared
Triggering of sweeps, or of steps in single-step mode, may be configured to operate as follows:
a. Triggered from TTL input on GPIO3 if Reg 14 h<5> = 1, or
b. Triggered by setting ramp_trigg (Reg 14 h<2>), if ramp_trigg has previously been cleared, or
c. Triggered with an automatically-generated internal trigger, if ramp_repeat_en
(Reg 14 h<3>) is set.
The sweep will begin at the current frequency value of the synthesizer, denoted as f0. The frequency step
size for the ramp is set by ramp_step (Reg 15 h), with
Δfstep = ramp_step * fREF / 224
The total number of ramp steps taken in a single sweep is given by ramp_steps_number (Reg 16 h), and
the initial ramp direction is set to be increasing or decreasing in frequency by clearing or setting ramp_
startdir_dn (Reg 14 h<4>) respectively. Setting ramp_singledir (Reg 14h<7>) restricts the direction of the
sweep to the initial sweep direction only.
The final ramp frequency, ff, is given by ff = f0+ Δfstep * ramp_steps_number for increasing frequency ramps
and ff= f0- Δfstep * ramp_steps_number for decreasing-frequency ramps. Unless in single-step mode, the
sweeper timebase, TREF, is the period of the divided reference fREF at the phase detector. So in and the
total time to ramp from f0to ffis Tramp = TREF * ramp_steps_number.
The user should be aware that the synthesized ramp is subject to normal phase-locked-loop dynamics. If
the loop bandwidth in use is much wider than the rate of the steps, then the locking will be very fast and the
ramp will have a staircase shape. As the update rate approaches the loop bandwidth, the loop will not fully
settle before a new frequency step is received. In this case, the swept output will have a small lag and will
sweep in a near-continuous fashion.
4.4.1 One-Way Sweeps
One-way sweeps are selected by enabling ramp_singledir (Reg 14h<7>). At the end of the ramp time, Tramp,
the sweeper will dwell at the final frequency, ff, until a new trigger is received. The second trigger will hop
the synthesizer back to the initial frequency, f0. The third trigger will restart the sweep from f0.

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 11
So odd-numbered triggers will start a new ramp in the same direction as the initial ramp and even-
numbered triggers will hop the synthesizer from the current frequency to f0where it will wait for a trigger to
start a sweep. Note that the odd-numbered triggers should be timed appropriately to allow the VCO to settle
after the large frequency hop back to the start frequency.
The functions of the sweep parameters for one-way sweeps are shown graphically in Figure 2.
Figure 2. 1-Way Sweep Control
4.4.2 Two-Way Sweeps
If ramp_singledir (Reg 14 h<7>) is disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the
final frequency, ff, until a new trigger is received. This new trigger will reverse the current sequence, starting
from ff and stepping back to f0. Odd triggers will ramp in the same direction as the initial ramp, while even
triggers will ramp in the opposite direction.
The functions of the sweep parameters for two-way sweeps are shown graphically in Figure 3.

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Figure 3. 2-Way Sweep Control via Trigger
4.4.3 Single Step Ramp Mode
Single-step mode is selected by setting ramp_singlestep (Reg 14 h<6>). In this mode, a trigger is required
for each step of the ramp. Single-step mode will function with either one-way or two-way ramps. The
operation of single-step mode for a one-way ramp is shown graphically in Figure 4.
Figure 4. Single Step Ramp Mode
4.4.4 Ramp Busy
In all types of sweeps, ramp_busy will indicate an active sweep and will stay high between the first and nth
ramp step. The ramp_busy signal may be monitored one of two ways:

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 13
a) ramp_busy is readable via read-only register Reg 1Fh<5>, and
b) ramp_busy may also be monitored on GPIO2 (hardware pin 2) by setting Reg 1B h<3:0> = 8.
4.4.5 Autosweep Mode
The autosweep mode is similar to the two-way sweep shown in (figure) except that triggers are not required.
The autosweep mode is enabled by setting ramp_repeat_en (Reg 14 h<3>); once enabled the autosweep
initiates the first trigger, steps the number of times given by ramp_steps_number (Reg 16 h) at a rate of
one step per divided reference clock cycle. It then waits the dwell time of ramp_dwell_time (Reg 17 h)
periods of the divided reference clock, and then automatically triggers the ramp in the opposite direction.
The sweep process continues, alternating sweep directions, until disabled.
4.5 Charge Pump
The up and down charge pumps of the synthesizer can each be adjusted to trade between fractional mode
spurious levels and phase noise performance. Optimal values will vary across frequency and are best
determined empirically for a particular application.
4.5.1 Charge Pump Gain
Up and down charge pump gains are set by cp_UPcurrent_sel and cp_DNcurrent_sel respectively (Reg
07h). Normally the registers are set to the same value. Each of the UP and DN charge pumps consist of 5-
bit charge pumps with lsb of 125 μA. The current gain of the pump, in Amps/radian, is equal to the gain
setting of this register divided by 2π.
For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to ’01000’ h the output current of each
pump will be 1 mA and the gain Kp = 1 mA/2π radians, or 159 μA/rad.
Optimum phase noise performance is generally obtained using low gain at lower VCO frequencies and high
gain at higher VCO frequencies.
4.5.2 Charge Pump Gain Trim
In most applications Gain Trim is not used. However it is available for special applications.
Each of the UP and DN pumps may be trimmed separately to more precise values to improve current
source matching of the UP and DN values, or to allow finer control of pump gain.
The pump trim controls are 3-bits, binary weighted for UP and DN, in cp_UPtrim_sel and cp_DNtrim_sel
respectively (Reg 08h). LSB weight is 14.7 μA, 000h = 0 trim, 001h = 14.7 μA added trim, 111 h = 102.9
μA.
4.5.3 Charge Pump Phase Offset
Either of the UP or DN charge pumps may have a DC leakage or “offset” added. The leakage forces the
phase detector to operate with a phase offset between the reference and the divided VCO inputs. It is
recommended to operate with a phase offset when using fractional mode to reduce non-linear effects from
the UP and DN pump mismatch. Phase noise in fractional mode is strongly affected by charge pump offset.
In addition, reference spurs in both integer and fractional mode are affected by the offset.

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DC leakage or “offset” may be added to the UP or DN pumps using cp_UPoffset_sel and cp_DNoffset_sel
(Reg 08h). These are 4 bit registers with 28.7 μA LSB. Maximum offset is 430 μA.
As an example, if the main pump gain was set at 1 mA, an offset of 373 μA would represent a phase offset
of about (392/1000)*360 = 133 degrees
4.5.4 Charge Pump Operation Near the Minimum & Maximum Output Frequency
It should be noted that the charge pump is a non-ideal device. Operation of the module tuned to values
near the minimum or maximum output frequency results in degradation of the phase noise performance.
When operating near the minimum or maximum frequencies, it is recommended to operate the PE11S100X
synthesizer modules with a DC leakage that mirrors the direction of frequency offset from center frequency.
For example, if the PE11S100X synthesizer modules operates from 5 to 10 GHz, with a center frequency
of 7.5 GHz, and the desired frequency of operation is 5.5 GHz, it is recommended to operate with a DC
leakage in the down direction. The converse is also true. If operating the module near its maximum
frequency, then a DC leakage in the UP direction is recommended. The appropriate leakage value is
application dependent and it is left to the user to determine the appropriate setting based on the application
requirements.
4.6 Power On Reset (POR)
Normally all logic cells in the internal PLL are reset when the device digital power supply, Vd1,
is applied. This is referred to as Power On Reset, or just POR. POR normally takes about 500
us after the Vd1 supply exceeds 1.6 V, guaranteed to be reset in 1 ms. Once the Vd1 supply
exceeds 1.6 V, the POR will not reset the digital again unless the supply drops below 800 mV.
4.6.1 Soft Reset
The SPI registers may also be soft reset by an SPI write to strobe global_swrst_regs (Reg 00h<0>).
All other digital items, including the fractional modulator, may be reset with an SPI write to strobe global_
swrst_dig (Reg 00h<1>).
4.6.2 Power Down
The internal PLL chip may be powered down by writing a zero to Reg 01h. In power down state, VD1 will
draw less than 1 mA. Note that a signal will still be present at the output (frequency may be anywhere in
the VCO tune range). It should be noted that Reg 01h is the Enable and Reset Register which controls 16
separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the
functions may be enabled when in operation. Hence power up of the chip requires a selective write to Reg
01h bits. An easy way to return the chip to its prior state after a power down is to first read Reg 01h and
save the state, then write a zero to Reg 01h for reset and then simply rewrite the previous value to restore
the chip to the desired operating mode.
5.0 Serial Port
The serial port is designed to operate on 3.3 V logic signals. At no time should levels above 3.6 V be applied
to these pins.
Typical serial port operation can be run with SCK at speeds up to 50 MHz.

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5.1 Serial Port WRITE Operation
Table 1. Timing Characteristics
Parameter Conditions Min Typ Max Units
t
1
SEN to SCK Setup Time
8
nsec
t
2
SDI to SCK Setup Time
10
nsec
t
3
SDI to SCK Hold Time
10
nsec
t
4
SCK High Duration
8
nsec
t
5
SCK Low Duration
8
nsec
t
6
SEN High Duration
640
nsec
A typical WRITE cycle is shown in Figure 5.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low initiates the
Write cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave reads the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f. Slave reads the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCK.
h. The 32nd falling edge of SCK completes the cycle.
Figure 5. Serial Port Timing Diagram - Write Serial Port WRITE Operation
5.2 Main Serial Port READ Operation
The synthesizer uses the multi-purpose pin, LD, for both Lock Detect and Serial Data Out (SDO) functions.
The registers lkd_to_sdo_automux_en (Reg 1Ah<12>) and lkd_to_sdo_always (Reg 1Ah<13>) determine
how the Data Output pin is muxed with the Lock Detect function. If both of the registers are cleared, then

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the pin is exclusively SDO. If automux is enabled, the pin switches to SDO when the RD function is sensed
on the 1st rising edge of SCK. If lkd_to_sdo_always is set, then the pin LD is dedicated for Lock Detect
only, and it is not possible to read from the synthesizer.
A typical READ cycle is shown in Figure 6.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed by
a rising edge SCK
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI high initiates the READ
cycle (RD)
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave reads the address bits on the next six rising edges of SCK (2-7).
e. Slave places the 24 data bits on the next 24 rising edges of SCK (8-31), MSB first.
f. Host reads the data bits on the next 24 falling edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCK.
h. The 32nd falling edge of SCK completes the cycle
Figure 6. Serial Port Timing Diagram – READ
6.0 Advanced Operation
6.1 Cycle Slip Prevention (CSP)
When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD
varies rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with
phase up to ±2π, the gain of conventional PFDs will cycle from high gain, when the phase difference
approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0
radians. This phenomena is known as cycle slipping. Cycle slipping causes the pull-in rate during the
locking phase to vary cyclically as shown in the red curve in Figure 7. Cycle slipping increases the time to
lock to a value far greater than that predicted by normal small signal Laplace analysis.

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The synthesizer features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during
acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as
the frequency difference is near zero. CSP allows significantly faster lock times as shown in Figure 7. The
use of the CSP feature is enabled with pfds_rstb (Reg 01h<15>). The CSP feature may be optimized for a
given set of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting
pfds_sat_deltaN (Reg 1C h<3:0>).
Figure 7. Cycle Slip Prevention (CSP)
6.2 PFD Jitter & Lock Detect Background
In normal phase locked operation, the divided VCO signal arrives at the phase detector in phase with the
divided crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase
of the VCO signal and the reference signal vary in time due to the phase noise of the crystal and VCO
oscillators, the loop bandwidth used and the presence of fractional modulation or not. The total integrated
noise on the VCO path normally dominates the variations in the two arrival times at the phase detector if
fractional modulation is turned off.
If we wish to detect if the VCO is in lock or not, we need to distinguish between normal phase jitter when in
lock and phase jitter when not in lock.
First, we need to understand what the jitter of the synthesizer is, measured at the phase detector in integer
or fractional modes.
The standard deviation of the arrival time of the VCO signal, or the jitter, in integer mode may be estimated
with a simple approximation if we assume that the locked VCO has a constant phase noise, Ф2 (fo), at offsets
less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. The simple locked
VCO phase noise approximation is shown on the left of Figure 8.
Figure 8. Graphical Representation of Locked VCO Phase Noise in the Frequency & Time Domains

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With this simplification the single sideband integrated VCO phase noise, Ф2, in rads2 at the phase detector
is given by
where
is the single sideband phase noise in rads2/Hz inside the loop bandwidth, B is the 3-dB corner
frequency of the closed loop PLL, and N is the division ratio of the prescaler.
The rms phase jitter of the VCO in rads, Ф, results from the power sum of the two sidebands:
Since the simple integral of (EQ 3) is just a product of constants, we can easily do the integral in the log
domain.
For example if the VCO phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth
is 100 kHz, and the division ratio N=100, then the integrated single sideband phase noise at the phase
detector in dB is given by
equivalently Ф= 10-82/20 = 56 urads rms or 3.2 milli-degrees rms.
While the phase noise reduces by a factor of 20logN after division to the reference, the jitter is a constant.
The rms jitter from the phase noise is then given by Tjpn = Tref Ф / 2π
In this example if the reference was 50 MHz, Tref = 20 nsec, and hence Tjpn = 178 femtoseconds.
A normal 3 sigma peak-to-peak variation in the arrival time therefore would be ±3 √ 2 Tjpn = 0.756 ps
If the synthesizer was in fractional mode, the fractional modulation of the VCO divider will dominate the
jitter. The exact standard deviation of the divided VCO signal will vary based upon the modulator chosen,
however a typical modulator will vary by about ±3 VCO periods, ±4 VCO periods, worst case.
If, for example, a nominal VCO at 5 GHz is divided by 100 to equal the reference at 50 MHz, then the worst
case division ratios will vary by 100±4. Hence the peak variation in the arrival times caused by ΔΣ
modulation of the fractional synthesizer at the reference will be:
In this example, . If we note that the distribution of the delta sigma
modulation is approximately gaussian, we could approximate TjΔΣpk as a 3 sigma jitter, and hence we could
estimate the rms jitter of the ΔΣ modulator as about 1/3 of TjΔΣpk or about 266 ps in this example.
Hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the VCO
would be given by the rms sum, where:
Ф
2
= ( Ф
2
( f
o
) Bπ) / N
2
SSB 2
Ф =
√
2Ф
2SSB
TjΔ∑pk= ±TVCO· (Nmax- Nmin) / 2
Ф2(fo)
SSB
(EQ 2)
(EQ 3)
Ф
2
dB = 10log (Ф
2
(f
o
)Bπ ⁄ N
2
) = -100 + 50 + 5 - 40 = -85 dBrads, or
(EQ 4)
TjΔ∑pk = ±200 ps(104-96)/2 = ±800 ps.

© 2019 Infinite Electronics, Inc. Pasternack is a registered trademark of Infinite Electronics, Inc. 19
In this example the jitter contribution of the phase noise calculated previously would add only 0.764psec
more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional
modulation.
Bottom line, we have to expect about ±0.8 ns of normal variation in the phase detector arrival times when
in fractional mode. In addition, lower VCO frequencies with high reference frequencies will have much larger
variations. For example, a 1 GHz VCO operating at near the minimum nominal divider ratio of 36, would,
according to (EQ 4), exhibit about ±4 ns of peak variation at the phase detector, under normal operation.
The lock detect circuit must not confuse this modulation as being out of lock.
6.3 PFD Lock Detect
pfd_lkd_en (Reg 01h<11>) enables the lock detect functions of the Internal PLL.
The Lock Detect circuit in the Internal PLL places a one shot window around the reference. The one shot
window may be generated by either an analog one shot circuit or a digital one shot based upon an internal
ring oscillator timer. Clearing lkd_ringosc_mono_select (Reg 1A h<14>) will result in a nominal ±10 ns
‘analog’ window of fixed length, as shown in Figure 3. Setting lkd_ringosc_mono_select will result in a
variable length ’digital’ widow.
The digital one shot window is controlled by lkd_ringosc_cfg (Reg 1A h<16:15>). The resulting lock detect
window period is then generated by the number of ring oscillator periods defined in lkd_monost_duration
Reg 1A h<18:17>. The lock detect ring oscillator may be observed on the GPO2 port by setting ringosc_
testmode (Reg 1A h<19>) and configuring the gpo_sel<3:0> = 0111 in Reg 1B h. Lock detect does not
function when this test mode is enabled.
lkd_wincnt_max (Reg 1A h<9:0>) defines the number of consecutive counts of the VCO that must land
inside the lock detect window to declare lock. If for example we set lkd_wincnt_max = 1000 , then the VCO
arrival would have to occur inside the selected lock widow 1000 times in a row to be declared locked. When
locked the Lock Detect flag ro_lock_detect (Reg 1Fh<0>) will be set. A single occurrence outside of the
window will result in clearing the Lock Detect flag, ro_lock_detect.
The Lock Detect flag ro_lock_detect (Reg 1Fh<0>) is a read only register, readable from the serial port.
The Lock Detect flag is also output to the LD pin according to lkd_to_sdo_always (Reg 1A h<13>) and
lkd_to_sdo_automux_en (Reg 1A h<12>), both in Table 28. Setting lkd_to_sdo_always will always display
the Lock Detect flag on LD. Clearing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display
the Lock Detect flag on LD except when a serial port read is requested, in which case the pin reverts
temporarily to the Serial Data Out pin, and returns to the lock detect function after the read is completed.
Tj=
√ T
2+
jpn
(TjΔ∑pk)
2
3
(EQ 5)

User Manual | PE11S100X Series Synthesizer
20 pasternack.com
Figure 9. Normal Lock Detect Window
6.4 Lock Detect with Phase Offset
When operating in fractional mode the linearity of the charge pump and phase detector are more critical
than in integer mode. The phase detector linearity is worse when operated with zero phase offset. Hence
in fractional mode it is necessary to offset the phase of the reference and the VCO at the phase detector.
In such a case, for example with an offset delay, as shown in Figure 10, the mean phase of the VCO will
always occur after the reference. The lock detect circuit window can be made more selective with a fixed
offset delay by setting lkd_win_asym_enable and lkd_win_asym_up_select (Reg 1A h<11>). Similarly the
offset can be in advance of the reference by clearing lkd_win_asym_up_select while leaving
lkd_win_asym_enable Reg 19 h<10> set. lkd_win_asym_enable is Reg 1A h<10>, lkd_win_asym_up_
select is Reg 1A h<11>.
Figure 10. Delayed Lock Detect Window
7.0 Register Map
7.1 Reg 00h Chip ID (Read Only) Register
Bit Type Name Default Description
[23:0]
Ro
Chip ID
581502h
Chip ID