Intel STEL-2176 User manual

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STEL-2176
User Manual
STel-MAN-97709
STEL-2176
Digital Mod/Demod ASIC
16/64/256 QAM Receiver
with FEC
QPSK/16 QAM Transmitter
with FEC
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STEL-2176User Manual
TRADEMARKS
Stanford Telecomand STELare registered trademarks of Stanford Telecommunications, Incorporated.

User Manual STEL-2176
FOREWORD
The Telecom Component Products Division of Stanford Telecommunications, Inc., is pleased to provide its
customers with this copy of the STEL 2176 User Manual.
This User Manual contains product information for the STEL 2176 and is being provided to assist our customers in
understanding the advantages to be gained by integrating both the receiver and transmitter functions as an integral
portion of their cable modem chip.
Recipients of this User Manual should note that the content contained here-in is subject to change. The content of
this User Manual will be updated to reflect the latest technical data, without notice to the recipients of this
document.

STEL-2176 User Manual
ERRATA for STEL-2176
Supported Modes of Operation:
Downstream
FEC 16 QAM 64 QAM 256 QAM
Annex A X X
Annex B X X
Annex C X X
Upstream
STD BPSK QPSK 16 QAM
MCNS X X
DAVIC X X

User Manual iSTEL-2176
TABLE OF CONTENTS
PARAGRAPH PAGE
KEY FEATURES..................................................................................................................................... 1
RECEIVER........................................................................................................................................... 1
TRANSMITTER................................................................................................................................... 1
INTRODUCTION .................................................................................................................................. 2
RECEIVER OVERVIEW........................................................................................................................ 2
TRANSMITTER OVERVIEW................................................................................................................ 2
MECHANICAL SPECIFICATIONS ........................................................................................................ 3
208-PIN SQFP PACKAGE..................................................................................................................... 3
ELECTRICAL SPECIFICATIONS........................................................................................................ 8
RECEIVER ............................................................................................................................................. 10
OVERVIEW......................................................................................................................................... 10
FUNCTIONAL BLOCKS ...................................................................................................................... 11
ADC.............................................................................................................................................. 11
Microcontroller Interface................................................................................................................. 11
Master Receive Clock Generator...................................................................................................... 12
QAM Demodulator Blocks.............................................................................................................. 13
FEC Decoder Blocks ....................................................................................................................... 14
RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS .................................................................... 20
PROGRAMMING THE 2176 RECEIVE FUNCTIONS ............................................................................. 20
REGISTER DESCRIPTIONS.................................................................................................................. 20
Bank 0 - Universal Registers (Group 1)............................................................................................. 20
Bank 0 - QAM Demodulator Registers Universal Registers (Group 2) ................................................ 22
Bank 1 - FEC Registers (Group 3)..................................................................................................... 30
TIMING................................................................................................................................................. 35
NO GAP, PARALLEL MODE ............................................................................................................... 35
NO GAP, SERIAL MODE..................................................................................................................... 35
GAPS, PARALLEL MODE.................................................................................................................... 35
GAPS, SERIAL MODE ......................................................................................................................... 35
TRANSMITTER..................................................................................................................................... 39
INTRODUCTION ................................................................................................................................39
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS ............................................................................. 39
DATA PATH DESCRIPTION ............................................................................................................... 39
Bit SYNC Block .............................................................................................................................. 39
Bit Encoder Block ........................................................................................................................... 41
Symbol Mapper Block..................................................................................................................... 45
Nyquist FIR Filter........................................................................................................................... 50
Interpolating Filter ......................................................................................................................... 50
Modulator ..................................................................................................................................... 51
10-Bit DAC..................................................................................................................................... 52

STEL-2176 ii User Manual
TABLE OF CONTENTS
PARAGRAPH PAGE
CONTROL UNIT DESCRIPTION.......................................................................................................... 52
Bus Interface Unit ........................................................................................................................... 52
Master Transmit Clock Generator .................................................................................................... 52
Clock Generator ............................................................................................................................. 53
NCO.............................................................................................................................................. 53
TRANSMIT REGISTER DESCRIPTIONS................................................................................................ 54
Programming the 2176 Transmit and Receive Functions.................................................................... 54
Block 2, Upstream Registers (Group 4) ............................................................................................. 54
TIMING DIAGRAMS ............................................................................................................................ 57
BURST TIMING EXAMPLES ................................................................................................................. 65
RECOMMENDED INTERFACE CIRCUITS ............................................................................................ 70

User Manual iii STEL-2176
LIST OF FIGURES
FIGURE PAGE
1 Reference A/D Wiring............................................................................................... 7
2 Example Output Load Schematic................................................................................ 7
3 STEL-2176 Receiver Block Diagram ............................................................................ 11
4 Master Receive Clock Generator................................................................................. 12
5 QAM Demodulator Blocks......................................................................................... 13
6 ITU-T (J.83) Annex A FEC Subsystem ......................................................................... 14
7 16 QAM Constellation ............................................................................................... 15
8 64 QAM Constellation ............................................................................................... 15
9 256 QAM Constellation (DAVIC)................................................................................ 15
10 256 QAM Constellation (DVB/IEEE 802.14) ................................................................ 15
11 Demapper................................................................................................................. 15
12 De-Interleaver........................................................................................................... 16
13 ITU-T (J.83) Annex B FEC Subsystem.......................................................................... 16
14 Trellis Coded Demodulator........................................................................................ 17
15 64 QAM Mapping ..................................................................................................... 17
16 256 QAM Mapping.................................................................................................... 18
17 Derandomizer........................................................................................................... 19
18 De-Interleaver........................................................................................................... 19
19. Downstream Output Timing (Parallel Data Output) .................................................... 36
20. Downstream Output Timing (Serial Output)............................................................... 36
21. Downstream Output Timing (Parallel Data Output) .................................................... 37
22. Downstream Output Timing (Parallel Data Output) .................................................... 38
23. De-Interleaver External SRAM Timing........................................................................ 38
24 STEL-2176 Transmitter Block Diagram........................................................................ 40
25 Bit Encoder Functional Diagram................................................................................. 42
26 Scrambler Block Diagram........................................................................................... 43
27 DAVIC Scrambler...................................................................................................... 43
28 Mapping Block Functional Diagram ........................................................................... 45
29 BPSK Constellation.................................................................................................... 47
30 QPSK Constellation ................................................................................................... 47
31 Natural Mapping Constellation.................................................................................. 48
32 Gray Coded Constellation.......................................................................................... 49
33 Left Coded Constellation ........................................................................................... 49
34 DAVIC Coded Constellation ...................................................................................... 49
35 Right Coded Constellation ......................................................................................... 49
36 Nyquist FIR Filter...................................................................................................... 50
37 Interpolation Filter Block Diagram.............................................................................. 51
38. Master Clock Generation ........................................................................................... 53

STEL-2176 iv User Manual
LIST OF TABLES
TABLE PAGE
1 STEL-2176 Pin Assignments ....................................................................................... 3
2 Absolute Maximum Ratings ....................................................................................... 8
3 Recommended Operating Conditions ......................................................................... 8
4 ADC Performance Specifications ................................................................................ 9
5 DC Characteristics ..................................................................................................... 9
6 Read/Write Register Set............................................................................................. 20
7 Write Only Registers:................................................................................................. 20
8 Group 2, Sub-Group 'A' Read/Write Registers............................................................. 22
9 Sub-Group 'A' Read-Only Registers ............................................................................ 22
10 SNR to ErrPwr Conversion......................................................................................... 23
11 Group 2, Sub-Group 'B' Read/Write Registers ............................................................. 24
12 Group 2, Sub-Group 'B' Read-Only Registers............................................................... 24
13 Group 2, Sub-Group 'C' Read/Write Registers............................................................. 26
14 Group 2, Sub-Group 'C' Read-Only Registers............................................................... 26
15 Group 2, Sub-Group 'D' Read/Write Registers............................................................. 26
16 Group 2, Sub-Group 'D' Read-Only Registers .............................................................. 27
17 Group 2, Sub-Group 'E' Read/Write Registers ............................................................. 28
18 Group 2, Sub-Group 'E' Read-Only Registers............................................................... 28
19 Group 2, Sub-Group 'F' Read/Write Registers ............................................................. 29
20 Group 2, Sub-Group 'F' Read-Only Registers ............................................................... 30
21 Group 3, Sub-Group 'A' Read/Write Registers............................................................. 30
22 Group 3, Sub-Group 'B' Read-Only Registers............................................................... 31
23 Group 3, Sub-Group 'C' Read/Write Registers............................................................. 31
24 Group 3, Sub-Group 'C' Read-Only Registers............................................................... 31
25 Group 3, Sub-Group 'D' Read/Write Registers............................................................. 32
26 Group 3, Sub-Group 'D' Read-Only Registers .............................................................. 32
27 Group 3, Sub-Group 'E' Read/Write Registers ............................................................. 33
28 Group 3, Sub-Group 'E' Read-Only Registers............................................................... 33
29 Group 3, Sub-Group 'F' Read/Write Registers ............................................................. 34
30 Group 3, Sub-Group 'G' Read/Write Registers............................................................. 34
31 Group 3, Sub-Group 'G' Read-Only Registers .............................................................. 34
32 Transmit Features...................................................................................................... 40
33 Data Latching Options ............................................................................................... 41
34 BIT Encoding Data Path Options................................................................................. 42
35 Scrambler Parameters ................................................................................................ 43
36 Sample Scramble Register Values................................................................................ 43
37 Reed-Solomon Encoder Parameters............................................................................. 44
38 Bit Mapping Options ................................................................................................. 45
39 Differential Encoder Control....................................................................................... 46
40 QPSK Differential Encoding and Phase Shift................................................................ 46
41 Symbol Mapping Selections........................................................................................ 48
42 Symbol Mapping ....................................................................................................... 48
43 FIR Filter Configuration Options ................................................................................ 50

User Manual vSTEL-2176
LIST OF TABLES
TABLE PAGE
44 FIR Filter Coefficient Storage...................................................................................... 50
45 Interpolation Filter Bypass Control............................................................................. 51
46 Interpolation Filter Signal Level Control ..................................................................... 51
47 Signal Inversion Control ............................................................................................ 52
48 FCW Selection........................................................................................................... 54
49 Addresses of the STEL-2176 Register Groups .............................................................. 54
50 Transmit Block 2 Register Data Fields......................................................................... 55
51 Clock Timing AC Characteristics................................................................................ 57
52 Pulse Width AC Characteristics.................................................................................. 58
53 Bit Clock Synchronization AC Characteristics.............................................................. 59
54 Input Data and Clock AC Characteristics .................................................................... 60
55 Write Timing AC Characteristics ................................................................................ 61
56 Read Timing AC Characteristics................................................................................. 62
57 NCO Loading AC Characteristics ............................................................................... 63
58 Digital Output Timing AC Characteristics................................................................... 64
59 TXDATAENI to TXDATAENO Timing AC Characteristics .......................................... 65

Introduction
STEL-2176 1User Manual
KEY FEATURES
RECEIVER
n10-bit A/D on chip
n16/64/256 QAM demodulation
nSelectable ITU-T (J.83), Annex A/Annex B
forward error correction (FEC)
nMCNS, IEEE 802.14 (preliminary),
DAVIC/DVB compliant
nParallel or serial output data with or
without gaps
nViterbi decoder for Annex B
nSelectable Reed-Solomon decoder for
Annex A and Annex B
nProgrammable De-Interleaver
nProgrammable De-Randomizer
nMPEG-2 Framing
nProgrammable control registers for
maximum flexibility
nFIFO for optional removal of inter-frame
gaps
nAutomatic frequency control (±200 kHz)
nHighly integrated receiver functions
nUp to 50 MHz IF input
nUses inexpensive Crystal in the 25 MHz
range
nAdaptive Channel Equalizer (ACE) to
compensate for channel distortion
nSelectable Nyquist filter
nFast acquisition
TRANSMITTER
nPatented (U.S. Patent #5,412,352)
Complete BPSK/QPSK/16QAM modulator
nComplete upstream modulator
solution—serial data in, RF signal out
nProgrammable over a wide range of data
rates
nNumerically Controlled Oscillator (NCO)
modulator provides fine frequency
resolution
nCarrier frequencies programmable from 5
to 65 MHz
nUses inexpensive crystal in 25 MHz range
nOperates in continuous and burst modes
nDifferential Encoder, Programmable
Scrambler, and Programmable Reed-
Solomon FEC Encoder
nProgrammable 64-tap FIR filter for signal
shaping before modulation
n10-bit DAC on chip
nCompatible with DAVIC, IEEE 802.14
(preliminary), Intelsat IESS-308, MCNS
Standards
nSupports low data rates for voice
applications and high data rates for
wideband applications