Intel STEL-2176 User manual

R
STEL-2176
User Manual
STel-MAN-97709
STEL-2176
Digital Mod/Demod ASIC
16/64/256 QAM Receiver
with FEC
QPSK/16 QAM Transmitter
with FEC
查询STEL-2176供应商

STEL-2176User Manual
TRADEMARKS
Stanford Telecomand STELare registered trademarks of Stanford Telecommunications, Incorporated.

User Manual STEL-2176
FOREWORD
The Telecom Component Products Division of Stanford Telecommunications, Inc., is pleased to provide its
customers with this copy of the STEL 2176 User Manual.
This User Manual contains product information for the STEL 2176 and is being provided to assist our customers in
understanding the advantages to be gained by integrating both the receiver and transmitter functions as an integral
portion of their cable modem chip.
Recipients of this User Manual should note that the content contained here-in is subject to change. The content of
this User Manual will be updated to reflect the latest technical data, without notice to the recipients of this
document.

STEL-2176 User Manual
ERRATA for STEL-2176
Supported Modes of Operation:
Downstream
FEC 16 QAM 64 QAM 256 QAM
Annex A X X
Annex B X X
Annex C X X
Upstream
STD BPSK QPSK 16 QAM
MCNS X X
DAVIC X X

User Manual iSTEL-2176
TABLE OF CONTENTS
PARAGRAPH PAGE
KEY FEATURES..................................................................................................................................... 1
RECEIVER........................................................................................................................................... 1
TRANSMITTER................................................................................................................................... 1
INTRODUCTION .................................................................................................................................. 2
RECEIVER OVERVIEW........................................................................................................................ 2
TRANSMITTER OVERVIEW................................................................................................................ 2
MECHANICAL SPECIFICATIONS ........................................................................................................ 3
208-PIN SQFP PACKAGE..................................................................................................................... 3
ELECTRICAL SPECIFICATIONS........................................................................................................ 8
RECEIVER ............................................................................................................................................. 10
OVERVIEW......................................................................................................................................... 10
FUNCTIONAL BLOCKS ...................................................................................................................... 11
ADC.............................................................................................................................................. 11
Microcontroller Interface................................................................................................................. 11
Master Receive Clock Generator...................................................................................................... 12
QAM Demodulator Blocks.............................................................................................................. 13
FEC Decoder Blocks ....................................................................................................................... 14
RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS .................................................................... 20
PROGRAMMING THE 2176 RECEIVE FUNCTIONS ............................................................................. 20
REGISTER DESCRIPTIONS.................................................................................................................. 20
Bank 0 - Universal Registers (Group 1)............................................................................................. 20
Bank 0 - QAM Demodulator Registers Universal Registers (Group 2) ................................................ 22
Bank 1 - FEC Registers (Group 3)..................................................................................................... 30
TIMING................................................................................................................................................. 35
NO GAP, PARALLEL MODE ............................................................................................................... 35
NO GAP, SERIAL MODE..................................................................................................................... 35
GAPS, PARALLEL MODE.................................................................................................................... 35
GAPS, SERIAL MODE ......................................................................................................................... 35
TRANSMITTER..................................................................................................................................... 39
INTRODUCTION ................................................................................................................................39
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS ............................................................................. 39
DATA PATH DESCRIPTION ............................................................................................................... 39
Bit SYNC Block .............................................................................................................................. 39
Bit Encoder Block ........................................................................................................................... 41
Symbol Mapper Block..................................................................................................................... 45
Nyquist FIR Filter........................................................................................................................... 50
Interpolating Filter ......................................................................................................................... 50
Modulator ..................................................................................................................................... 51
10-Bit DAC..................................................................................................................................... 52

STEL-2176 ii User Manual
TABLE OF CONTENTS
PARAGRAPH PAGE
CONTROL UNIT DESCRIPTION.......................................................................................................... 52
Bus Interface Unit ........................................................................................................................... 52
Master Transmit Clock Generator .................................................................................................... 52
Clock Generator ............................................................................................................................. 53
NCO.............................................................................................................................................. 53
TRANSMIT REGISTER DESCRIPTIONS................................................................................................ 54
Programming the 2176 Transmit and Receive Functions.................................................................... 54
Block 2, Upstream Registers (Group 4) ............................................................................................. 54
TIMING DIAGRAMS ............................................................................................................................ 57
BURST TIMING EXAMPLES ................................................................................................................. 65
RECOMMENDED INTERFACE CIRCUITS ............................................................................................ 70

User Manual iii STEL-2176
LIST OF FIGURES
FIGURE PAGE
1 Reference A/D Wiring............................................................................................... 7
2 Example Output Load Schematic................................................................................ 7
3 STEL-2176 Receiver Block Diagram ............................................................................ 11
4 Master Receive Clock Generator................................................................................. 12
5 QAM Demodulator Blocks......................................................................................... 13
6 ITU-T (J.83) Annex A FEC Subsystem ......................................................................... 14
7 16 QAM Constellation ............................................................................................... 15
8 64 QAM Constellation ............................................................................................... 15
9 256 QAM Constellation (DAVIC)................................................................................ 15
10 256 QAM Constellation (DVB/IEEE 802.14) ................................................................ 15
11 Demapper................................................................................................................. 15
12 De-Interleaver........................................................................................................... 16
13 ITU-T (J.83) Annex B FEC Subsystem.......................................................................... 16
14 Trellis Coded Demodulator........................................................................................ 17
15 64 QAM Mapping ..................................................................................................... 17
16 256 QAM Mapping.................................................................................................... 18
17 Derandomizer........................................................................................................... 19
18 De-Interleaver........................................................................................................... 19
19. Downstream Output Timing (Parallel Data Output) .................................................... 36
20. Downstream Output Timing (Serial Output)............................................................... 36
21. Downstream Output Timing (Parallel Data Output) .................................................... 37
22. Downstream Output Timing (Parallel Data Output) .................................................... 38
23. De-Interleaver External SRAM Timing........................................................................ 38
24 STEL-2176 Transmitter Block Diagram........................................................................ 40
25 Bit Encoder Functional Diagram................................................................................. 42
26 Scrambler Block Diagram........................................................................................... 43
27 DAVIC Scrambler...................................................................................................... 43
28 Mapping Block Functional Diagram ........................................................................... 45
29 BPSK Constellation.................................................................................................... 47
30 QPSK Constellation ................................................................................................... 47
31 Natural Mapping Constellation.................................................................................. 48
32 Gray Coded Constellation.......................................................................................... 49
33 Left Coded Constellation ........................................................................................... 49
34 DAVIC Coded Constellation ...................................................................................... 49
35 Right Coded Constellation ......................................................................................... 49
36 Nyquist FIR Filter...................................................................................................... 50
37 Interpolation Filter Block Diagram.............................................................................. 51
38. Master Clock Generation ........................................................................................... 53

STEL-2176 iv User Manual
LIST OF TABLES
TABLE PAGE
1 STEL-2176 Pin Assignments ....................................................................................... 3
2 Absolute Maximum Ratings ....................................................................................... 8
3 Recommended Operating Conditions ......................................................................... 8
4 ADC Performance Specifications ................................................................................ 9
5 DC Characteristics ..................................................................................................... 9
6 Read/Write Register Set............................................................................................. 20
7 Write Only Registers:................................................................................................. 20
8 Group 2, Sub-Group 'A' Read/Write Registers............................................................. 22
9 Sub-Group 'A' Read-Only Registers ............................................................................ 22
10 SNR to ErrPwr Conversion......................................................................................... 23
11 Group 2, Sub-Group 'B' Read/Write Registers ............................................................. 24
12 Group 2, Sub-Group 'B' Read-Only Registers............................................................... 24
13 Group 2, Sub-Group 'C' Read/Write Registers............................................................. 26
14 Group 2, Sub-Group 'C' Read-Only Registers............................................................... 26
15 Group 2, Sub-Group 'D' Read/Write Registers............................................................. 26
16 Group 2, Sub-Group 'D' Read-Only Registers .............................................................. 27
17 Group 2, Sub-Group 'E' Read/Write Registers ............................................................. 28
18 Group 2, Sub-Group 'E' Read-Only Registers............................................................... 28
19 Group 2, Sub-Group 'F' Read/Write Registers ............................................................. 29
20 Group 2, Sub-Group 'F' Read-Only Registers ............................................................... 30
21 Group 3, Sub-Group 'A' Read/Write Registers............................................................. 30
22 Group 3, Sub-Group 'B' Read-Only Registers............................................................... 31
23 Group 3, Sub-Group 'C' Read/Write Registers............................................................. 31
24 Group 3, Sub-Group 'C' Read-Only Registers............................................................... 31
25 Group 3, Sub-Group 'D' Read/Write Registers............................................................. 32
26 Group 3, Sub-Group 'D' Read-Only Registers .............................................................. 32
27 Group 3, Sub-Group 'E' Read/Write Registers ............................................................. 33
28 Group 3, Sub-Group 'E' Read-Only Registers............................................................... 33
29 Group 3, Sub-Group 'F' Read/Write Registers ............................................................. 34
30 Group 3, Sub-Group 'G' Read/Write Registers............................................................. 34
31 Group 3, Sub-Group 'G' Read-Only Registers .............................................................. 34
32 Transmit Features...................................................................................................... 40
33 Data Latching Options ............................................................................................... 41
34 BIT Encoding Data Path Options................................................................................. 42
35 Scrambler Parameters ................................................................................................ 43
36 Sample Scramble Register Values................................................................................ 43
37 Reed-Solomon Encoder Parameters............................................................................. 44
38 Bit Mapping Options ................................................................................................. 45
39 Differential Encoder Control....................................................................................... 46
40 QPSK Differential Encoding and Phase Shift................................................................ 46
41 Symbol Mapping Selections........................................................................................ 48
42 Symbol Mapping ....................................................................................................... 48
43 FIR Filter Configuration Options ................................................................................ 50

User Manual vSTEL-2176
LIST OF TABLES
TABLE PAGE
44 FIR Filter Coefficient Storage...................................................................................... 50
45 Interpolation Filter Bypass Control............................................................................. 51
46 Interpolation Filter Signal Level Control ..................................................................... 51
47 Signal Inversion Control ............................................................................................ 52
48 FCW Selection........................................................................................................... 54
49 Addresses of the STEL-2176 Register Groups .............................................................. 54
50 Transmit Block 2 Register Data Fields......................................................................... 55
51 Clock Timing AC Characteristics................................................................................ 57
52 Pulse Width AC Characteristics.................................................................................. 58
53 Bit Clock Synchronization AC Characteristics.............................................................. 59
54 Input Data and Clock AC Characteristics .................................................................... 60
55 Write Timing AC Characteristics ................................................................................ 61
56 Read Timing AC Characteristics................................................................................. 62
57 NCO Loading AC Characteristics ............................................................................... 63
58 Digital Output Timing AC Characteristics................................................................... 64
59 TXDATAENI to TXDATAENO Timing AC Characteristics .......................................... 65

Introduction
STEL-2176 1User Manual
KEY FEATURES
RECEIVER
n10-bit A/D on chip
n16/64/256 QAM demodulation
nSelectable ITU-T (J.83), Annex A/Annex B
forward error correction (FEC)
nMCNS, IEEE 802.14 (preliminary),
DAVIC/DVB compliant
nParallel or serial output data with or
without gaps
nViterbi decoder for Annex B
nSelectable Reed-Solomon decoder for
Annex A and Annex B
nProgrammable De-Interleaver
nProgrammable De-Randomizer
nMPEG-2 Framing
nProgrammable control registers for
maximum flexibility
nFIFO for optional removal of inter-frame
gaps
nAutomatic frequency control (±200 kHz)
nHighly integrated receiver functions
nUp to 50 MHz IF input
nUses inexpensive Crystal in the 25 MHz
range
nAdaptive Channel Equalizer (ACE) to
compensate for channel distortion
nSelectable Nyquist filter
nFast acquisition
TRANSMITTER
nPatented (U.S. Patent #5,412,352)
Complete BPSK/QPSK/16QAM modulator
nComplete upstream modulator
solution—serial data in, RF signal out
nProgrammable over a wide range of data
rates
nNumerically Controlled Oscillator (NCO)
modulator provides fine frequency
resolution
nCarrier frequencies programmable from 5
to 65 MHz
nUses inexpensive crystal in 25 MHz range
nOperates in continuous and burst modes
nDifferential Encoder, Programmable
Scrambler, and Programmable Reed-
Solomon FEC Encoder
nProgrammable 64-tap FIR filter for signal
shaping before modulation
n10-bit DAC on chip
nCompatible with DAVIC, IEEE 802.14
(preliminary), Intelsat IESS-308, MCNS
Standards
nSupports low data rates for voice
applications and high data rates for
wideband applications

STEL-2176 2User Manual
INTRODUCTION
The STEL-2176 is a complete subscriber-side cable
modem chip that integrates both receiver and
transmitter functions. It is offered in CMOS .35 micron
geometry operating at 3.3 Volts with integrated DAC
and ADC. Its programmable register set offers a flexible
solution to meet current and evolving standards.
RECEIVER OVERVIEW
A 10-bit A/D converts the analog input signal. The
analog input signal may be up to 50ÊMHz. For MCNS
and DAVIC standards 44 MHz and 36 MHz are the two
typical IF frequencies used. For 44ÊMHz the
corresponding bandwidth is 6 MHz; for 36ÊMHz the
corresponding bandwidth is 8 MHz. Sampling of the
input may be set for 25 MHz for the 6ÊMHz bandwidth
or 29 MHz for the 8 MHz bandwidth.
The downstream receiver offers 16/64/256 QAM
demodulation for Annex A, associated with DAVIC, or
Annex B, associated with MCNS. It also offers a variety
of choices for the data and clock outputs: frames with
or without gaps and parallel or serial data.
The incoming signal is sampled. The timing recovery
circuit determines the epoch of each symbol. Automatic
frequency and gain control circuitry correct the
frequency and amplitude of the signal, and a Digital
Down Converter (DDC) brings the alias band
associated with sampling down to zero. A Nyquist filter
eliminates inter-symbol interference, and an Adaptive
Channel Equalizer (ACE) corrects for channel distortion
while fine tuning the signal. A demapper transforms
the modulated signal back into symbols and a De-
Interleaver puts the data bits back into the original
order, while Trellis and Reed-Solomon decoders handle
error correction.
For Annex A, a Reed-Solomon decoder decodes and
corrects every 204 bytes in 188 bytes. For Annex B, there
is a Viterbi decoder and a 128, 122 (code word length,
information) 7-bit Reed-Solomon decoder. A de-
randomizer is used to unscramble the data stream.
Format of the receiver output is MPEG-2 frames.
TRANSMITTER OVERVIEW
The transmitter is highly integrated and flexible. It
receives serial data, randomizes the data, performs
Forward Error Correction (FEC) and differential
encoding, maps the data to a constellation before
modulation, and outputs an analog RF signal.
It includes a 10-bit DAC and is capable of operating at
data rates up to 20 Mbps in QPSK mode and 40ÊMbps in
16QAM mode.
The transmitter uses a digital FIR filter to optimally
shape the spectrum of the modulating data prior to
modulation. Signal level scaling is provided after the
FIR filter to allow maximum arithmetic dynamic range.
The transmitter side offers QPSK and 16QAM
modulation with frequencies from 5 to 65 MHz. It can
operate in continuous or burst mode. And it can
operate with very short gaps between bursts less than
four symbols.
All digital interfaces support 3.3 volt and 5 volt logic.

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User Manual 3STEL-2176
MECHANICAL SPECIFICATIONS
208-PIN SQFP PACKAGE
Dimensions are in millimeters.
TPG53310.c-7/29/97
Table 1. STEL-2176 Pin Assignments
Pin No. Pin Name Pin Type Pin Description
1 VSS Ground
2 VDD Power Dedicated to crystal oscillator at pins 3 & 4
3 RXOSCIN Input Receiver oscillator input
4 RXOSCOUT Output Receiver oscillator output
5 VSS Ground Dedicated to crystal oscillator at pins 3 & 4
6 VDD Power Dedicated to digital section of receive clock multiplier
7 VDDA Power (Analog) Dedicated to analog section of receive clock multiplier
8 RXMULTEN Input Enable receive clock multiplier
9 VSSA Ground
(Analog) Dedicated to receive clock multiplier
10 VSS Ground Dedicated to receive clock multiplier
11 RXMULTCLK Output Receive clock multiplier output; enabled by pin 58
12 VDD Power
13 ADCDATASEL[2] Input ADC/DAC bypass mode select; 111=normal operation
14 ADCDATASEL[1] Input ADC/DAC bypass mode select; 110=bypass ADC
15 ADCDATASEL[0] Input ADC/DAC bypass mode select; 101=bypass DAC
16 VSS Ground
17 ADDATA[9] Bi-directional Bypass/test ADC/DAC

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STEL-2176 4User Manual
Pin No. Pin Name Pin Type Pin Description
18 ADDATA[8] Bi-directional Bypass/test ADC/DAC
19 ADDATA[7] Bi-directional Bypass/test ADC/DAC
20 ADDATA[6] Bi-directional Bypass/test ADC/DAC
21 ADDATA[5] Bi-directional Bypass/test ADC/DAC
22 VDD Power
23 ADDATA[4] Bi-directional Bypass/test ADC/DAC
24 ADDATA[3] Bi-directional Bypass/test ADC/DAC
25 ADDATA[2] Bi-directional Bypass/test ADC/DAC
26 ADDATA[1] Bi-directional Bypass/test ADC/DAC
27 ADDATA[0] Bi-directional Bypass/test ADC/DAC
28 VSS Ground
29 RXAGCOUTB Output AGC output B
30 RXAGCOUTA Output AGC output A
31 VDD5 Power 3.3V or 5V for AGC pins 29 & 30
32 V3OP Input Must set high if pin 31 is 3.3V or low if pin 31 is 5V
33 VSS Ground
34 IC Internal connection - leave open
35 SO Output SPI data out
36 VDD Power
37 SI Input SPI data in
38 SCK Input SPI clock
39 VSS Ground
40 ADDR[7] Input Control/Status register parallel address bus
41 ADDR[6] Input Control/Status register parallel address bus
42 ADDR[5] Input Control/Status register parallel address bus
43 ADDR[4] Input Control/Status register parallel address bus
44 VDD Power
45 ADDR[3] Input Control/Status register parallel address bus
46 ADDR[2] Input Control/Status register parallel address bus
47 ADDR[1] Input Control/Status register parallel address bus
48 ADDR[0] Input Control/Status register parallel address bus
49 VSS Ground
50 INTSEL[1] Input Serial/parallel inter. sel.: 00=parallel, 01=SPI (serial)
51 INTSEL[0] Input Serial/parallel interface select: 10=reserved, 11=res.
52 VDD Power
53 VSS Ground
54
CS
Input Control/Status register chip select (active low)
55
WRB
Input Control/Status register read/write (low=write)
56
DSB
Input Control/Status register data strobe signal (active low)
57 VDD Power
58 ENCLKOUT Input Enables output pins 11 & 102
59 VSS Ground
60 DATA[7] Bi-directional Control/Status register parallel data in/out
61 DATA[6] Bi-directional Control/Status register parallel data in/out
62 DATA[5] Bi-directional Control/Status register parallel data in/out
63 DATA[4] Bi-directional Control/Status register parallel data in/out
64 VDD Power
65 DATA[3] Bi-directional Control/Status register parallel data in/out
66 DATA[2] Bi-directional Control/Status register parallel data in/out
67 DATA[1] Bi-directional Control/Status register parallel data in/out
68 DATA[0] Bi-directional Control/Status register parallel data in/out
69 VSS Ground
70 RXRESCLK Output FEC test clock output (8 times RX symbol rate)
71 VDD Power
72 RXTSTDOUT[9] Output Test mux output
73 RXTSTDOUT[8] Output Test mux output
74 RXTSTDOUT[7] Output Test mux output
75 RXTSTDOUT[6] Output Test mux output

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Pin No. Pin Name Pin Type Pin Description
76 VSS Ground
77 RXTSTDOUT[5] Output Test mux output
78 RXTSTDOUT[4] Output Test mux output
79 RXTSTDOUT[3] Output Test mux output
80 RXTSTDOUT[2] Output Test mux output
81 VDD Power
82 RXTSTDOUT[1] Output Test mux output
83 RXTSTDOUT[0] Output Test mux output
84 RXTSTCLK Output Test mux output clock
85 VSS Ground
86 VDD Power Dedicated to digital portion of DAC
87 VDDA Power (analog) Dedicated to analog portion of DAC
88 DACOUTP Analog output Output of DAC. Terminate in 37.5 ohms to ground(See Figure 2)
89 DACOUTN Analog output Comp. output of DAC. Terminate in 37.5 ohms to ground(See
Figure 2)
90 VSSA Power (analog) Dedicated to analog portion of DAC
91 VSS Ground Dedicated to digital portion of DAC
92 VDD Power Dedicated to crystal oscillator at pins 93 & 94
93 TXOSCIN Input TX oscillator input
94 TXOSCOUT Output TX oscillator output
95 VSS Ground Dedicated to crystal oscillator at pins 93 & 94
96 VDD Power Dedicated to digital section of transmit clock PLL
97 VDDA Power (analog) Dedicated to analog section of transmit clock PLL
98 TXPLLEN Input Enable transmit clock PLL
99 VSSA Ground (analo
g
) Dedicated to analog section of transmit clock PLL
100 TXBYPCLK Input High speed transmit bypass clock
101 VDD Power Dedicated to digital section of transmit clock PLL
102 TXPLLCLK Output Transmit clock PLL output; enabled by pin 58
103 VSS Ground Dedicated to digital section of transmit clock PLL
104 VDD Power
105 VSS Ground
106 TXRSTB Input Transmit reset (active low)
107 VDD Power
108 TXTSDATA Input Transmit data input
109 TXDATAENI Input Transmit data enable input
110 TXTCLK Input Transmit tclk
111 VSS Ground
112 TXFCWSEL[1] Input Transmit frequency control word (FCW) select
113 TXFCWSEL[0] Input Transmit frequency control word (FCW) select
114 VDD Power
115 TXCLKEN Input Transmit clock enable
116 TXDIFFEN Input Transmit differential encoder enable
117 TXRDSLEN Input Transmit Reed-Solomon enable
118 TXSCRMEN Input Transmit scrambler enable
119 VSS Ground
120 TXCKSUM Output Transmit Reed-Solomon check sum
121 TXACLK Output Transmit auxiliary clock output
122 TXDATAENO Output Transmit data enable output
123 VDD Power
124 TXBITCLK Output Transmit bit clock
125 TXSYMPLS Output Transmit symbol pulse output
126 TXNCOLD Input Transmit NCO load
127 VDD5 Power Input buffer bias. Set to 3.3V or 5V dep. on max. input V.
voltage.
128 RXRSTB Input Receiver reset (active low)
129 VSS Ground
130 RXPDATAOUT[7] Output Receive parallel output data
131 RXPDATAOUT[6] Output Receive parallel output data
132 RXPDATAOUT[5] Output Receive parallel output data

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Pin No. Pin Name Pin Type Pin Description
133 RXPDATAOUT[4] Output Receive parallel output data
134 VDD Power
135 RXPDATAOUT[3] Output Receive parallel output data
136 RXPDATAOUT[2] Output Receive parallel output data
137 RXPDATAOUT[1] Output Receive parallel output data
138 RXPDATAOUT[0] Output Rec. par. output data or serial data if in serial mode
139 VSS Ground
140 RXOUTCLK Output Receive output data clock
141 VDD Power
142 RXACQFLAG Output Receive demod. acquisition flag
143 RXACQFAIL Output Receive demod. acquisition failure flag
144 RXDECDFLG Output Receive FEC decodable flag
145 FRAMESYNC Output Receive output frame sync flag
146 VSS Ground
147 SRAMADDR[15] Output De-Interleaver optional external SRAM address
148 SRAMADDR[14] Output De-Interleaver optional external SRAM address
149 SRAMADDR[13] Output De-Interleaver optional external SRAM address
150 SRAMADDR[12] Output De-Interleaver optional external SRAM address
151 VDD Power
152 SRAMADDR[11] Output De-Interleaver optional external SRAM address
153 SRAMADDR[10] Output De-Interleaver optional external SRAM address
154 SRAMADDR[9] Output De-Interleaver optional external SRAM address
155 SRAMADDR[8] Output De-Interleaver optional external SRAM address
156 VSS Ground
157 VDD Power
158 VSS Ground
159 SRAMADDR[7] Output De-Interleaver optional external SRAM address
160 SRAMADDR[6] Output De-Interleaver optional external SRAM address
161 SRAMADDR[5] Output De-Interleaver optional external SRAM address
162 SRAMADDR[4] Output De-Interleaver optional external SRAM address
163 VDD Power
164 SRAMADDR[3] Output De-Interleaver optional external SRAM address
165 SRAMADDR[2] Output De-Interleaver optional external SRAM address
166 SRAMADDR[1] Output De-Interleaver optional external SRAM address
167 SRAMADDR[0] Output De-Interleaver optional external SRAM address
168 VSS Ground
169 SRAMDATA[7] Bi-Directional De-Interleaver optional external SRAM data bus
170 SRAMDATA[6] Bi-Directional De-Interleaver optional external SRAM data bus
171 SRAMDATA[5] Bi-Directional De-Interleaver optional external SRAM data bus
172 SRAMDATA[4] Bi-Directional De-Interleaver optional external SRAM data bus
173 VDD Power
174 SRAMDATA[3] Bi-Directional De-Interleaver optional external SRAM data bus
175 SRAMDATA[2] Bi-Directional De-Interleaver optional external SRAM data bus
176 SRAMDATA[1] Bi-Directional De-Interleaver optional external SRAM data bus
177 SRAMDATA[0] Bi-Directional De-Interleaver optional external SRAM data bus
178 VSS Ground
179 SRAMWEB Output De-Interleaver SRAM write enable (active low)
180 SRAMCSB Output De-Interleaver SRAM chip select (active low)
181 SRAMOEB Output De-Interleaver SRAM output enable (active low)
182 VDD Power
183 RXIENBLE Input FEC test input I clock
184 RXQENBLE Input FEC test input Q clock
185 VSS Ground
186 RXBYPCLK Bi-directional Receiver bypass clock input; output reserved
187 VDD Power
188 VSSA Ground (analo
g
) Dedicated to analog section of ADC (See Figure 1)
189 VDDA Power (analog) Dedicated to analog section of ADC(See Figure 1)
190 VCMA Analog output From ADC (See Figure 1)
191 VDD Power Dedicated to digital section of ADC(See Figure 1)

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User Manual 7STEL-2176
Pin No. Pin Name Pin Type Pin Description
192 VREFN Analog output From ADC(See Figure 1)
193 VSSA Ground (analo
g
) Dedicated to analog section of ADC(See Figure 1)
194 VSS Ground Dedicated to digital section of ADC (See Figure 1)
195 VDDA Power (analog) Dedicated to analog section of ADC (See Figure 1)
196 VDDA Power (analog) Dedicated to analog section of ADC(See Figure 1)
197 ADCINP Analog input ADC input(See Figure 1)
198 ADCINN Analog input Complementary ADC input(See Figure 1)
199 VSSA Ground (analo
g
) Dedicated to analog section of ADC (See Figure 1)
200 VSSA Ground (analo
g
) Dedicated to analog section of ADC(See Figure 1)
201 VDD Power Dedicated to digital section of ADC(See Figure 1)
202 VDDA Power (analog) Dedicated to analog section of ADC(See Figure 1)
203 VREFP Analog output From ADC(See Figure 1)
204 VSS Ground Dedicated to digital section of ADC(See Figure 1)
205 VCMB Analog output From ADC(See Figure 1)
206 VSSA Ground (analo
g
) Dedicated to analog section of ADC(See Figure 1)
207 VDDA Power (analog) Dedicated to analog section of ADC(See Figure 1)
208 VDD Power
STEL-2176
Analog In (P)Analog In (N)
0.1
µF 0.1 µF 0.1 µF 0.1 µF
Digital GND
(VSS)
Analog GND
(VSSA)
Digital Supply
(VDD)
0.1
µF 0.1 µF 0.1 µF 0.1 µF
0.1
µF
Figure 1. Reference A/D Wiring
X
T1-6TKK81
0.1 µF
50
50
50
load
0.1 µF
Mini-
Circuits
1:1
DACOUTP
DACOUTN
AV
SS
AV
SS
Note 1: Normally some application dependent alias filtering and
amplitude control appear at this point in the circuit
WCP 53807.c-12/5/97
50 line Note 1
0.1 µF
Figure 2. Example Output Load Schematic

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STEL-2176 8User Manual
ELECTRICAL SPECIFICATIONS
The STEL-2176 electrical characteristics are provided by Table 2 through Table 4.
WARNING
Stresses greater than those shown in Table 2 may cause permanent damage to the STEL-2176.
Exposure to these conditions for extended periods may also affect the STEL-2176 reliability.
Table 2. Absolute Maximum Ratings
Symbol Parameter Range Units Note 1
Tstg Storage Temperature Ð40 to +125 °C
VDDmax Supply voltage on VDD Ð0.3 to +4.6 volts
AVDDmax Supply voltage on AVDD Ð0.3 to +4.6 volts
5VDDmax Supply voltage on 5VDD Ð0.3 to +7.0 volts Note 2
AVSS Analog supply return for AVDD ±10% of VDD volts
VI(max) Input voltage Ð0.3 to 5VDD+0.3 volts
IiDC input current ±30 mA
PDiss (max) Power dissipation 1500 mW
Note:
All voltages are referenced to VSS.
5VDD must be greater than or equal to VSS. This rule can be violated for a maximum of 100 msec
during power up.
Table 3. Recommended Operating Conditions
Symbol Parameter Range Units Note 1
AVDD Supply Voltage +3.3 ±10% Volts
5VDD Supply Voltage +5.0 ±10% Volts Note 2
VDD Supply Voltage +3.3 ±10% Volts
CLOAD DAC Load Capacitance ≤20 pF
RLOAD DAC Load Resistance ≤30K ohms
Recommended DAC Load 37.5 ohms
VLOAD DAC Output Voltage ≤1.25 Volts
TaOperating Temperature (Ambient) Ð40 to +85 °C Note 3
Note:
1. All voltages with respect to VSS and assume AVss = Vss
2. If interface lo
g
ic is to be driven b
y
VDD then connect the 5VDD
p
in to the VDD su
pp
l
y
and set
pin 32 to correct value.
3. Duty Cycle Derating is required from +70°to +85°C.

Intro
d
uction
User Manual 9STEL-2176
Table 4. ADC Performance Specifications
Parameter Min Nom Max Units
Sampling Frequency 50 MHz
Resolution 10 bits
Input Differential Signal Range -0.75 +0.75 Volts
Analog Input Bandwidth 60 MHz
Signal to Distortion Ratio 10 MHz
signal over 25 MHz BW
54 dB
Input Common Mode 1.4 1.5 1.6 Volts
Table 5. DC Characteristics
(VDD = 3.3 V ±10%, VSS = 0 V, Ta= -40°to 85°C)
Symbol Parameter Min. Nom. Max. Units Conditions
IVDDQ Supply Current, Quiescent 1.0 mA Static, no clock
IVDD Supply Current, Operational, VDD 1.9 mA/MHz
I5VDD Supply Current, Operational, 5VDD 0.2 mA
IAVDD Supply Current, Operational, AVDD 12.0 mA
VIHCLK Clock High Level Input Voltage 2.0 volts CLK, Logic '1'
VILCLK Clock Low Level Input Voltage 0.8 volts CLK, Logic '0'
VIH High Level Input Voltage 2.0 volts Other inputs, Logic '1'
VIL Low Level Input Voltage 0.8 volts Other inputs, Logic '0'
IIH High Level Input Current 10 µAV
IN = 5VDD
IIL Low Level Input Current Ð10 µAV
IN = VSS
VOH(min) High Level Output Voltage 2.4 3.0 VDD volts IO= Ð2.0 mA
VOL(max) Low Level Output Voltage 0.2 0.4 volts IO= +2.0 mA
IOS Output Short Circuit CurrentÊ 40 mA VOUT = VDD,
VDDÊ=Êmax
CIN Input Capacitance 2 pF All inputs
COUT Output Capacitance 4 10 pF All outputs
IOFS Output Full Scale DAC Current 16 19 22 mA Single output
VODAC Compliance Voltage
(Differential) ±0.96 Volts Based on 50 ohms load resistance to ground.
RODAC Output Resistance1N/A
CODAC Output Capacitance 4 8 pF
NOTES:
1. Current source to ground output.

Receiver Description
STEL-2176 10 User Manual
RECEIVER
OVERVIEW
The STEL-2176 is a complete subscriber-side cable
modem ASIC which integrates both the downstream
receiver and upstream transmitter functions. The
receiver includes a high performance 10-bit Analog-to-
Digital Converter (ADC) with a direct Intermediate
Frequency (IF) interface. The receiver also includes a
QAM demodulator and both ITU-T (J.83) Annex A and
Annex B Forward Error Correction (FEC). The
upstream transmitter includes a BPSK/QPSK/16QAM
modulator with highly flexible FEC and scrambling,
and a 10-bit low spurious digital to analog converter
(DAC) for direct synthesis of an upstream 5 to 65 MHz
signal. Both the receiver and transmitter are highly
flexible and programmable; the STEL-2176 Digital
Mod/Demod ASIC offers a solution to meet current
and evolving standards.
The input to the STEL-2176 receiver is an analog IF
signal of up to 50 MHz. Typically, the IF signal has 44
MHz center frequency with a 6 MHz bandwidth for
NTSC based systems, or a 36 MHz center frequency
with an 8 MHz bandwidth for PAL based systems. In
typical applications, the input signal is sampled by the
ADC at approximately 25 MHz for the 44 MHz IF, or at
approximately 29 MHz for the 36 MHz IF
This type of sub-sampling technique works by
intentionally undersampling the carrier frequency so
that aliased signal appears at a lower frequency. The
sampling rate is still high enough to capture all of the
modulation bandwidth without distortion. In the case
of a 44 MHz IF and a 25 MHz clock, the resulting digital
signal is centered at 6 MHz. In the case of a 36 MHz IF
and 29 MHz clock, the resulting digital signal is
centered at 7 MHz. For more information on sub-
sampling techniques, please see Stanford Telecom
Application Note A-117.
The digital samples from the ADC are downconverted
to baseband I and Q signals in the Digital Down
Converter (DDC) block. Since the RF tuner sections of a
cable modem may have large frequency errors, an
Automatic Frequency Control (AFC) block is used in
the STEL-2176 for coarse tuning of the DDC. This
allows rapid acquisition of the input signal even with
frequency errors of ±200 kHz. Fine tuning of the DDC is
done using a carrier Phase-Lock Loop (PLL).
An Automatic Gain Control (AGC) function provides
two output signals to adjust the RF and IF analog gain
stages of circuitry external to the STEL-2176, so that the
ADC input is in the optimal range. The two outputs can
be programmed to create a sequential AGC system
which maximizes RF gain for improved receiver noise
figure. The two AGC outputs and the external gain
adjust blocks work together to maximize ADC
performance, but when large adjacent channels are
present, the power of the desired signal may change. A
second digital AGC tracks and adjusts the level of the
desired signal after the adjacent channel energy is
removed by filtering.
Following the DDC, a square root raised cosine Nyquist
filter eliminates adjacent channel signals, and performs
matched filtering to eliminate intersymbol interference.
The filter excess bandwidth or alpha is programmable
from 0.12 to 0.20. The Timing Recovery block finds the
exact location in the center of each symbol using a
special low-jitter discriminator. These values are fed to
the Adaptive Channel Equalizer.
An Adaptive Channel Equalizer (ACE) compensates for
any multipath distortion on the input signal introduced
in the channel. The equalizer uses one sample per
symbol (T spaced taps). The output of the equalizer is
baseband I and Q signals with carrier frequency and
phase errors, symbol timing errors, gain errors, and
multipath effects removed.
The Demapper takes the baseband I and Q signals
representing the QAM symbols, and translates each
symbol back into a series of binary values based on one
of the selectable constellation maps.
Following the Demapper is the Forward Error
Correction (FEC) system. This programmable system
supports both the ITU-T (J.83) Annex A (see page 14)
and Annex B (see page 16) standards. In general, both
FEC systems employ Reed Solomon Decoders, Frame
Sync circuits that determine the FEC code block
boundaries, and a De-Interleaver. Interleaving is used
in the FEC standards to improve performance when the
channel contains bursty noise. Since the transmitter
Interleaver spreads the data over a large time, when the
receiver performs the matched operation to the
Interleaver in order to bring the data back into the
correct time sequence, any burst errors appear to be
spread out in time. This helps makes these errors

Receiver Description
User Manual 11 STEL-2176
correctable by the FEC. The STEL-2176 internal memory
can support all MCNS Interleaver configurations. For
deeper interleaving, a direct interface to external
memory is provided.
The output of the receiver is typically arranged as
MPEG-2 frames, although the MPEG-2 framing can be
by-passed for ATM applications. The output can be 8-
bit parallel with a byte clock or serial with a bit clock.
The data can be output in a smooth fashion without
inter-frame gaps or with the pauses in output data
caused by the FEC system passed through to the output
(see Receiver Timing discussion).
1st IF Output
A
~25 MHz
ADC
10 bits/
Sample
Interpolator
Fo=44/36 MHz
BW= 6/8 MHz
4Samples/Symbol
~25 MHz XO
Micro Controller Interface
AFC
AGC
DDC Nyquist
(0.12 to 0.2)
Clock
Recovery
Clock
Synthesizer
Channel
Equalizer
De-mapper
Viterbi
Diff. Decoder
Frame Sync
A
Micro Controller ( SPI, Parallel)
Programmable Adaptive
(20 taps)
44 MHz
36 MHz
Deinterleaver
Reed-Solomon
Decoder
(204,188 and
128,122)
External RAM
WCP 52861.c-5/07/97
Figure 3. STEL-2176 Receiver Block Diagram
FUNCTIONAL BLOCKS
ADC
The ADC uses differential analog signal inputs
ADCINP and ADCINN. Differential coupling to the
ADC is important to prevent common mode noise from
the digital sections of the ASIC from coupling into the
input. The recommended input signal level is ±0.75V.
The input is sampled by the ADC, and the samples are
converted into 10-bit digital values. The sampling rate
is typically 25 MHz for an input of 44 MHz ±3 MHz
with a symbol rate of about 5 MHz (i.e., the MCNS
standard) or 29 MHz for an input of 36 MHz ±4 MHz
with a symbol rate of about 7 MHz (i.e., the DAVIC and
DVB standards). The sampling rate is controlled the
choice of crystal connected between RXOSCIN and
RXOSCOUT or by the clock frequency applied to
RXOSCIN. The sample rate must be slightly more than
4 samples per symbol. The sample clock generated by
the crystal/receive clock oscillator or applied to
RXOSCIN must be a low phase noise signal. For this
reason, dedicated power and ground connections for
the receive oscillator and input buffer are adjacent to
the RXOSCIN and RXOSCOUT pins.
Microcontroller Interface
The microcontroller interface provides access to the
internal programmable Universal, Downstream
(Receive), and Upstream (Transmit) registers (see page
20) via a parallel or a SPI interface. The interface used is
selected by the interface select lines (INTSEL[1-0]).