ISSI IS31AP2121 User manual

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 1
Rev. C, 10/20/2015
2×25W STEREO / 1×50W MONO DIGITAL AUDIO AMPLIFIER
WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE October 2015
GENERAL DESCRIPTION
The IS31AP2121 is a digital audio amplifier capable of
driving 25W (BTL) each to a pair of 8Ωspeakers and
50W (PBTL) to a 4Ωspeaker operating at 24V supply
without external heat-sink or fan. The IS31AP2121 is
also capable of driving 4Ω, 12W (SE)×2 + 8Ω, 25W
(BTL)×1 at 24V supply for 2.1CH application.
The IS31AP2121 can provide advanced audio
processing functions, such as volume control, 20 EQ
bands, audio mixing, 3D surround sound and Dynamic
Range Control (DRC). These are fully programmable
via a simple I2C control interface. Robust protection
circuits are provided to protect the IS31AP2121 from
damage due to accidental erroneous operating
condition. The full digital circuit design of IS31AP2121
is more tolerant to noise and PVT (Process, Voltage,
and Temperature) variation than the analog Class-AB
or Class-D audio amplifier counterpart implemented by
analog circuit design. IS31AP2121 is pop free during
instantaneous power on/off or mute/shut down
switching because of its robust built-in anti-pop circuit.
APPLICATIONS
TV audio
Boom-box, CD and DVD receiver, docking system
Powered speaker
Wireless audio
FEATURES
16/18/20/24-bits input with I2S, Left-alignment and
Right-alignment data format
PSNR & DR (A-weighting)
Loudspeaker: 104dB (PSNR), 110dB (DR) @24V
Multiple sampling frequencies (FS)
- 32kHz / 44.1kHz / 48kHz and
- 64kHz / 88.2kHz / 96kHz and
- 128kHz / 176.4kHz / 192kHz
System clock = 64x, 128x, 192x, 256x, 384x,
512x, 576x, 768x, 1024x Fs
- 64x~1024x FSfor 32kHz / 44.1kHz / 48kHz
- 64x~512x FSfor 64kHz / 88.2kHz / 96kHz
- 64x~256x FSfor 128kHz / 176.4kHz / 192kHz
Supply voltage
- 3.3V for digital circuit
- 10V~26V for speaker driver
Supports 2.0CH/2.1CH/Mono configuration
Loudspeaker output power for at 24V
- 10W ×2CH into 8Ω@0.16% THD+N for stereo
- 15W ×2CH into 8Ω@0.19% THD+N for stereo
- 25W ×2CH into 8Ω@0.3% THD+N for stereo
Sound processing including:
- 20 bands parametric speaker EQ
- Volume control (+24dB ~ -103dB, 0.125dB/step),
- Dynamic range control (DRC)
- Dual band dynamic range control
- Power clipping
- 3D surround sound
- Channel mixing
- Noise gate with hysteresis window
- Bass/Treble tone control
- Bass management crossover filter
- DC-blocking high-pass filter
Anti-pop design
Short circuit and over-temperature protection
Supports I2C control without MCLK
I2C control interface with selectable device
address
Support BCLK system
Support hardware and software reset
Internal PLL
LV Under-voltage shutdown and HV Under-voltage
detection
Power saving mode

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 2
Rev. C, 10/20/2015
TYPICAL APPLICATION CIRCUIT
Figure 1 Typical Application Circuit (For Stereo)
BEAD
470pF
BEAD
10
10
470pF
OUTLA
OUTLB
OUTRA
OUTRB
DVDD
OUTLA
SDA
IS31AP2121
0.1 F
4.7k
VDD
OUTRB
DGND
SCL
4.7k
VDD
RSTB
PDB
1M1M
Micro
Controller
1 F 1 F
ERRORB
MCLK
BCLK
LRCIN
SDATA
VCCLA
VCCLB
GNDL
VCC
0.1 F470 F
VCCRA
VCCRB
GNDR
VCC
0.1 F 0.1 F
0.1 F
OUTRA
OUTLB
PBTL
1nF
1nF
Speaker
4
15 H
6A
BEAD
470pF
BEAD
10
10
470pF
15 H
6A
220nF
100nF
100nF
*Note 4
*Note 4
*Note 2
1
23
24
25
19
14
15
21
20
22 36
39
2
3,44
47
48
35
34,41
37
38
46
13,27
9,28
8
Digital
Audio
Source
470 F
Figure 2 Typical Application Circuit (For Mono)
Pin Logic 0 1
PDB Power Down Normal
RSTB Reset Normal
PBTL Stereo Mono

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 3
Rev. C, 10/20/2015
Figure 3 Typical Application Circuit (For 2.1CH) (Note 5)
Pin Logic 0 1
PDB Power Down Normal
RSTB Reset Normal
PBTL X X
Note 1: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 7A.
Note 2: These capacitors should be placed as close to speaker jack as possible, and their values should be determined according to EMI test
results.
Note 3: The snubber circuit can be removed while the VCC ≤20V.
Note 4: When concerning about short-circuit protection or performance, it is suggested using the choke with its IDC larger than 14A.
Note 5: 2.1CH configuration, it programs by I2C via register address 0x11, D4 bit SEM.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 4
Rev. C, 10/20/2015
PIN CONFIGURATION
Package Pin Configuration (Top View)
eLQFP-48
1
2
3
4
5
6
7
8
NC
VCCLA
OUTLA
9
10
11
12
VCCLB
NC
NC
PBTL
DGND
NC
NC
DVDD
NC
NC
NC
34
33
32
31
30
29
28
27
26
25
17 18 19 20 21 22 23 24 13 14 15 16
PDB
BCLK
SDATA
48 47 46 45 44 43 42 41 40 39 38 37
OUTLB NC GNDL
GNDL
NC
NC
CLK_OUT
NC
SCL
NC
LRCIN
DVDD
SDA
ERRORB
NC
NC
NC
DGND
NC
RSTB
OUTRA VCCLB NC VCCRB GNDR GNDR NC
MCLK
VCCRB
VCCRA
OUTRB36
35

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 5
Rev. C, 10/20/2015
PIN DESCRIPTION
No. Pin Description Characteristics
1 OUTLA Left channel output A.
2 VCCLA Left channel supply A.
3,44 VCCLB Left channel supply B.
4~6,10~12 NC Not connected.
7 CLK_OUT
PLL ratio setting pin during power up, this pin
is monitored on the rising edge of reset. PMF
register will be default set at 1 or 4 times PLL
ratio.
Low: PMF [3:0]=[0000], 1 time of PLL ratio to
avoid system MCLK over flow. High: PMF
[3:0]=[0100], 4 times of PLL ratio.
This pin could be clock output pin also during
normal operating if EN_CLK_OUT register bit
is enabled.
TTL output buffer, internal pull low with
an 80kΩresistor.
8 PBTL
Stereo/mono configuration pin (Low: Stereo;
High: Mono).
9,28 DGND Digital ground.
13,27 DVDD Digital power.
14 ERRORB
ERRORB pin is a dual function pin. One is
I2C address setting during power up. The
other one is error status report (low active). It
sets by register of A_SEL_FAULT at address
0x13 D6 to enable it.
This pin is monitored on the rising edge
of reset. A value of Low (15kΩpull
down) sets the I2C device address to
0x30 and a value of High (15kΩpull up)
sets it to 0x31.
15 MCLK Master clock input. Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩresistor.
16~18,26 NC Not connected.
19 PDB Power down, low active. Schmitt trigger TTL input buffer, internal
pull High with a 330kΩresistor.
20 LRCIN Left/Right clock input (FS). Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩresistor.
21 BCLK Bit clock input (64FS). Schmitt trigger TTL input buffer, internal
pull Low with an 80kΩresistor.
22 SDATA I2S serial audio data input. Schmitt trigger TTL input buffer
23 SDA I2C serial data. Schmitt trigger TTL input buffer
24 SCL I2C serial clock input. Schmitt trigger TTL input buffer
25 RSTB Reset, low active. Schmitt trigger TTL input buffer, internal
pull High with a 330kΩresistor.
29~33,40 NC Not connected.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 6
Rev. C, 10/20/2015
PIN DESCRIPTION (CONTINUE)
No. Pin Description Characteristics
34,41 VCCRB Right channel supply B.
35 VCCRA Right channel supply A.
36 OUTRB Right channel output B.
37,38 GNDR Right channel ground.
39 OUTRA Right channel output A.
42,43,45 NC Not connected.
46 OUTLB Left channel output B.
47,48 GNDL Left channel ground.
Thermal Pad Connect to DGND.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 7
Rev. C, 10/20/2015
ORDERING INFORMATION
Industrial Range: 0°C to +70°C
Order Part No. Package QTY
IS31AP2121-LQLS1 e-LQFP-48, Lead-free 250/Tray
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IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 8
Rev. C, 10/20/2015
ABSOLUTE MAXIMUM RATINGS
Supply for driver stage (VCCR, VCCL), VCC -0.3V ~ +30V
Supply for digital circuit (DVDD), VDD -0.3V ~ +3.6V
Input voltage (SDA,SCL,RSTB,PDB,ERRORB,MCLK,
BCLK,LRCIN,SDATA,PBTL), VIN -0.3V ~ +3.6V
Thermal resistance, θJA 27.4°C/W
Junction temperature range, TJ 0°C ~ 150°C
Storage temperature range, TSTG -65°C ~ +150°C
ESD (HBM)
ESD (CDM)
±2kV
±500V
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Condition Min. Typ. Max. Unit
VCC Supply for driver stage to VCCR/L 10 26 V
VDD Supply for digital circuit 3.15 3.45 V
TJJunction operating temperature 0 125 °C
TAAmbient operating temperature 0 70 °C
DC ELECTRICAL CHARACTERISTICS
TA=25°C, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
IPDH VCC supply current during power down VCC = 24V 10 200 µA
IPDL DVDD supply current during power
down VDD = 3.3V, PBTL=Low 13 20 µA
ICCH Quiescent current for VCC (50%/50%
PWM duty) VCC = 24V 37 mA
ICCL Quiescent current for DVDD (Un-mute) VDD = 3.3V, PBTL=Low 70 mA
VUVH Under-voltage disabled (For DVDD) 2.8 V
VUVL Under-voltage enabled (For DVDD) 2.7 V
RDS(ON)
Static drain-to-source on-state resistor,
PMOS VCC =24V, ID= 500mA
260
mΩ
Static drain-to-source on-state resistor,
NMOS 230
ISC L/R channel over-current protection VCC =24V, ID=500mA
(Note 1)
7 A
Mono channel over-current protection 14
TS
Junction temperature for driver
shutdown 158 °C
Temperature hysteresis for recovery
from shutdown 33 °C

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 9
Rev. C, 10/20/2015
DC ELECTRICAL CHARACTERISTICS (CONTINUE)
TA=25°C, unless otherwise noted.
Symbol Parameter Condition Min. Typ. Max. Unit
Logic Electrical Characteristics
VIH High level input voltage VDD =3.3V 2.0 V
VIL Low level input voltage VDD =3.3V 0.8 V
VOH High level output voltage VDD =3.3V 2.4 V
VOL Low level output voltage VDD =3.3V 0.4 V
CIN Input capacitance 6.4 pF
Note 1: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly connected with external LC filters. Please
refer to the application circuit example for recommended LC filter configuration.
AC ELECTRICAL CHARACTERISTICS
TA=25°C, VCC=24V, VDD = 3.3V, fS= 48kHz, RL=8Ωwith passive LC lowpass filter (L= 15µH, RDC= 63mΩ,
C=220nF), input is 1kHz sinewave, volume is 0dB unless otherwise specified.
Symbol Parameter Condition Min. Typ. Max. Unit
PORMS output power (Note 2)
THD+N=0.16%, VCC=24V, +8dB
volume 10
W
THD+N=0.25%, VCC=24V, +8dB
volume 20
THD+N=1%, VCC=12V, +8dB volume 7.5
THD+N=10%, VCC=12V, +8dB volume 9
PBTL Mode, VCC=24V, RL=4Ω,
THD+N=0.16%, +8dB volume 40
PBTL Mode, VCC=12V, RL=4Ω,
THD+N=1%, +8dB volume 15
PBTL Mode, VCC=12V, RL=4Ω,
THD+N=10%, +8dB volume 18
2.1CH Mode, VCC=24V, RL=4Ω,
THD+N=0.14%, +8dB volume 5
2.1CH Mode, VCC=24V, RL=4Ω,
THD+N=0.16%, +8dB volume 10
2.1CH Mode, VCC=12V, RL=4Ω,
THD+N=1%, +8dB volume 3.7
2.1CH Mode, VCC=12V, RL=4Ω,
THD+N=10%, +8dB volume 4.5
THD+N Total harmonic distortion +
noise
VCC=24V, PO = 7.5W 0.15 %
VCC=12V, Po = 2.5W 0.16
VNO Output noise 20Hz ~ 20kHz (Note 3) 120 µV
SNR Signal-to-noise ratio +8dB volume, input level is -9dB
(Note 3) 104 dB
DR Dynamic range +8dB volume, input level is -68dB
(Note 3) 110 dB
PSRR Power supply ripple rejection VRIPPLE = 1VRMS at 1kHz -71 dB
Channel separation 1W @1kHz -81 dB

IS31AP2121
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Rev. C, 10/20/2015
I2C DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)
Symbol Parameter Standard Mode Fast Mode Unit
Min. Max. Min. Max.
fSCL Serial-Clock frequency 0 100 0 400 kHz
tBUF Bus free time between a STOP and a START
condition 4.7 1.3 μs
tHD, STA Hold time (repeated) START condition 4.0 0.6 μs
tSU, STA Repeated START condition setup time 4.7 0.6 μs
tSU, STO STOP condition setup time 4.0 0.6 μs
tHD, DAT Data hold time 0 3.45 0 0.9 μs
tSU, DAT Data setup time 250 100 ns
tLOW SCL clock low period 4.7 1.3 μs
tHIGH SCL clock high period 4.0 0.6 μs
tRRise time of both SDA and SCL signals,
receiving 1000 20+0.1Cb300 ns
tFFall time of both SDA and SCL signals,
receiving 300 20+0.1Cb300 ns
CbCapacitive load for each bus line 400 400 pF
VNL Noise margin at the low level for each
connected device (including hysteresis) 0.1VDD 0.1VDD V
VNH Noise margin at the high level for each
connected device (including hysteresis) 0.2VDD 0.2VDD V
I2S DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)
Symbol Parameter Condition Min. Typ. Max. Unit
tLR LRCIN period (1/FS) 10.41 31.25 μs
tBL BCLK rising edge to LRCIN edge 50 ns
tLB LRCIN edge to BCLK rising edge 50 ns
tBCC BCLK period (1/64FS) 162.76 488.3 ns
tBCH BCLK pulse width high 81.38 244 ns
tBCL CBLK pulse width low 81.38 244 ns
tDS SDATA set up time 50 ns
tDH SDATA hold time 50 ns
Note 2: Thermal dissipation is limited by package type and PCB design. The external heat-sink or system cooling method should be adopted
for maximum power output.
Note 3: Measured with A-weighting filter.
Note 4: Guaranteed by design.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 11
Rev. C, 10/20/2015
Figure 4 I2C Timing
Figure 5 I2S
Figure 6 Left-Alignment
Figure 7 Right-Alignment
Figure 8 System Clock Timing

IS31AP2121
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Rev. C, 10/20/2015
Figure 9 Timing Relationship (Using I2S format as an example)

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Rev. C, 10/20/2015
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10 R
L = 8
V
CC = 24V
Strereo
P O = 10W
P O = 5W
P O = 0.5W
P O = 1W
P O = 0.25W
Figure 10 THD+N vs. Frequency
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
0.006
R L = 4
V
CC = 24V
PBTL Mode
P O = 5W
P O = 1W
P O = 2W
Figure 12 THD+N vs. Frequency
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10 R
L = 4
V
CC = 24V
2.1CH Mode
P O = 5W
P O = 1W
P O = 2.5W
Figure 14 THD+N vs. Frequency
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10 R
L = 8
V
CC = 12V
Strereo
P O = 0.5W
P O = 5W
P O = 2.5W
Figure 11 THD+N vs. Frequency
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
R L = 4
V
CC = 12V
PBTL Mode
0.006
P O = 1W
P O = 2W
P O = 5W
Figure 13 THD+N vs. Frequency
Frequency(Hz)
THD+N(%)
20 50 100 200 500 1k 2k 5k 20k
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10 R
L = 4
V
CC = 12V
2.1CH Mode
P O = 2.5W
P O = 0.5W
P O = 1W
Figure 15 THD+N vs. Frequency

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Rev. C, 10/20/2015
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
1m 505m 10m 50m 100m 500m 1 2 5 10 20
V CC = 24V
R
L = 8
Strero
10kHz
1kHz
20Hz
Figure 16 THD+N vs. Output Power
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
5010m 50m 100m 500m 1 2 5 10 20 100
10kHz
20Hz
1kHz
V CC = 24V
R
L = 4
PBTL Mode
Figure 18 THD+N vs. Output Power
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
5010m 50m 100m 500m 1 2 5 10 20
R L = 4
2.1CH Mode
f = 1kHz
V CC = 12V
V CC = 24V
V CC = 18V
Figure 20 THD+N vs. Output Power
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
5010m 50m 100m 500m 1 2 5 10 20
VCC = 12V
RL= 8
Strero
20Hz
1kHz
10kHz
Figure 17 THD+N vs. Output Power
THD+N(%)
Output Power(W)
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
5010m 50m 100m 500m 1 2 5 10 20
V CC = 12V
R
L = 4
PBTL Mode
1kHz
10kHz
20Hz
Figure 19 THD+N vs. Output Power
dBr
20 20k50 100 200 500 1k 2k 5k 10k
Frequency(Hz)
-2
+2
-1.5
1
-0.5
+0
+0.5
+1
+1.5
V CC = 24V
R
L = 8
P
O = 1W
Stereo
Figure 21 Frequency Response

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Rev. C, 10/20/2015
Crosstalk(dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency(H z)
-120
+0
-100
-80
-60
-40
-20
V CC = 24V
R
L = 8
Stereo
Left to Right
Right to Left
Figure 22 Cross-Talk
dB
V
Frequency(H z)
2k 20k4k 6k 8k 10k 12k 14k 16k 18k0k
-140
-120
-100
-80
-60
-40
-20
+0
+20
V CC = 24V
R
L = 8
Stereo
Figure 24 Spectrum at -60dB Signal Input Level
Output Power(W)
Efficiency(%)
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45 50
R L = 8
Stereo
V CC =24V
V CC =18V
V CC =15V
V CC =8V V
CC =12V
Figure 26 Efficiency vs. Output Power (Power Saving Mode)
Crosstalk(dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency(H z)
-120
+0
-100
-80
-60
-40
-20
V CC = 12V
R
L = 8
Stereo
Left to Right
Right to Left
Figure 23 Cross-Talk
dBV
Frequency(H z)
2k 20k4k 6k 8k 10k 12k 14k 16k 18k0k
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
+10
+20
VCC = 24V
RL= 8
Stereo
Figure 25 Spectrum at Peak SNR at -1dB Signal Input
Output Power(W)
Supply Voltage(V)
0
5
10
15
20
25
30
35
40
45
10 12 14 16 18 20 22 24 26
R L = 8
BTL Mode
THD+N = 10%
THD+N = 1%
Figure 27 Output Power vs. Supply Voltage
Note: Dashed lines represent thermally limited region.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 16
Rev. C, 10/20/2015
Output Power(W)
Supply Voltage(V)
10 12 14 16 18 20 22 24 26
0
10
20
30
40
50
60
R L = 4
PBTL Mode
THD+N = 1%
THD+N = 10%
Figure 28 Output Power vs. Supply Voltage
Note: Dashed lines represent thermally limited region.
Output Power(W)
Supply Voltage(V)
10 12 14 16 18 20 22 24
0
2
4
6
8
10
12
14
16
18
20
22
24
R L = 4
2.1CH Mode
THD+N = 1%
THD+N = 10%
Figure 29 Output Power vs. Supply Voltage
Note: Dashed lines represent thermally limited region.

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 17
Rev. C, 10/20/2015
FUNCTIONAL BLOCK DIAGRAM

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 18
Rev. C, 10/20/2015
APPLICATIONS INFORMATION
IS31AP2121 has a built-in PLL internally, the default
volume is muted. IS31AP2121 will activate while the
de-mute command via I2C is programmed.
OPERATION MODES
Without I2C Control
The default settings, Bass, Treble, EQ, Volume,
DRC, PLL, Subwoofer Bandwidth, …, and Sub-
woofer gain are applied to register table content
when using IS31AP2121 without I2C control. The
more information about default settings, please refer
to the highlighted column of register table section.
With I2C Control
When using I2C control, user can program suitable
parameters into IS31AP2121 for their specific
applications. Please refer to the register table
section to get the more detail.
INTERNAL PLL
IS31AP2121 has a built-in PLL internally. The
MCLK/FSratio will be fixed at 1024x, 512x, or 256x
with a sample frequency of 48kHz, 96kHz, or
192kHz respectively. A carrier clock frequency is the
frequency divided by 128 of master clock.
Table 1 MCLK/FSRatio
FSMCLK Frequency
48kHz 49.152MHz
44.1kHz 45.158MHz
32kHz 32.768MHz
RESET
When the RSTB pin is lowered, IS31AP2121 will
clear the stored data and reset the register table to
default values. IS31AP2121 will exit reset state at
the 256th MCLK cycle after the RSTB pin is raised to
high.
POWER DOWN CONTROL
IS31AP2121 has a built-in volume fade-in/fade-out
design for power down and mute function. The
relative power down timing diagrams for
loudspeakers are shown below.
Figure 30 Power Down Timing Diagrams With Mute
Figure 31 Power Down Timing Diagrams
The volume level will be decreased to -dB in
several LRCIN cycles. Once the fade-out procedure
is finished, IS31AP2121 will turn off the power
stages, stop clock signals (MCLK, BCLK) from
feeding into digital circuit and turn off the current of
the internal analog circuits. After PDB pin is pulled
low, IS31AP2121 needs up to 256 LRCIN clocks to
finish the above works before entering power down
state. Users can’t program IS31AP2121 during
power down state, but all the settings of register
table will still be kept except that DVDD is removed.
If the PD function is disabled in the midway of the
fade-out procedure, IS31AP2121 will also execute
the fade-in procedure. In addition, IS31AP2121 will
establish the analog circuits’ bias current and feed
the clock signals (MCLK, BCLK) into digital circuits.
Then, IS31AP2121 will return to its normal operation
without power down.
SELF-PROTECTION CIRCUITS
IS31AP2121 has built-in protection circuits including
thermal, short-circuit and under-voltage detection
circuits.
Thermal Protection
When the internal junction temperature is higher
than 158°C, power stages will be turned off and
IS31AP2121 will return to normal operation once the
PDB PDB
PDB
PDB
-103dB
-103dB

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 19
Rev. C, 10/20/2015
temperature drops to 125°C. The temperature
values may vary around 10%.
Short-Circuit Protection
The short-circuit protection circuit protects the output
stage when the wires connected to loudspeakers are
shorted to each other or GND/VDD. For normal 24V
operations, the current flowing through the power
stage will be less than 7A for stereo configuration or
less than 14A for mono configuration. Otherwise, the
short-circuit detectors may pull the ERRORB pin to
DGND, disabling the output stages. When the over-
temperature or short-circuit condition occurs, the
open-drain ERRORB pin will be pulled low and
latched into ERROR state.
Once the over-temperature or short-circuit condition
is removed, IS31AP2121 will exit ERROR state
when one of the following conditions is met: (1)
RSTB pin is pulled low. (2) PDB pin is pulled low. (3)
Master mute is enabled through the I2C interface.
Under-voltage Protection
Once the VDD voltage is lower than 2.7V,
IS31AP2121 will turn off its loudspeaker power
stages and cease the operation of digital processing
circuits. When VDD becomes larger than 2.8V,
IS31AP2121 will return to normal operation.
ANTI-POP DESIGN
IS31AP2121 will generate appropriate control
signals to suppress pop sounds during initial power
on/off, power down/up, mute, and volume level
changes.
3D SURROUND SOUND
IS31AP2121 provides the virtual surround sound
technology with greater separation and depth voice
quality for stereo signals.
I2C CHIP SELECT
ERRORB is an input pin during power. It can be
pulled High (15kΩpull up) or Low (15kΩpull down).
Low indicates an I2C address of 0x30, and high an
address of 0x31.
OUTPUT CONFIGURATION
The bit 4 [SEM] of address 0X11 and PBTL pin
defines the configuration mode. IS31AP2121 can be
configured to stereo, mono via PBTL pin (the bit 4
[SEM] of address 0X11 default is low). 2.1CH output
mode configuration, user can via I2C to program it
from the bit 4 [SEM] of address 0X11. Table 2
provides a reference of available configuration.
Table 2 Output Configurations
[SEM] PBTL Configuration Mode
0 0 Stereo
0 1 Mono
1 x 2.1CH
Figure 32 Output Configurations

IS31AP2121
Integrated Silicon Solution, Inc. – www.issi.com 20
Rev. C, 10/20/2015
POWER ON SEQUENCE
Hereunder is IS31AP2121’s power on sequence. Give a de-mute command via I2C when the whole system is
stable.
t1VCC
VDD
MCLK
BCLK
LRCIN
RSTB
PDB
I2C
OUT
t2
t8
t3
t4 t5
t7t6
t9 t10
t13 t14
t12 t5
t11 t3
I2C Active
De-mute
Power-On Normal
Operation
Normal
Operation
PDB=L
Figure 33 Power On Sequence
Table 2 Power On Sequence
Symbol Condition Min. Max. Unit
t1 0 - ms
t2 0 - ms
t3 10 - ms
t4 0 - ms
t5 10 - ms
t6 10 - ms
t7 0 - ms
t8 200 - ms
t9 20 - ms
t10 - 0.1 ms
t11 25 - ms
t12 25 - ms
t13 - 22 ms
t14 - 0.1 ms
POWER OFF SEQUENCE
Hereunder is IS31AP2121’s power off sequence.
VCC
VDD
MCLK
BCLK
LRCIN
RSTB
PDB
I2C
OUT
Don’t Care
t4
t5
t3
t2
t1
Figure 34 Power Off Sequence