ITCI Brasov CoBra Guide

HARDWARE AND SOFTWARE SCIENTIFIC RESEARCH
AND TECHNOLOGICAL ENGINEERING INSTITUTE
HARDWARE DEPARTMENT
COBRA
HARDWARE
DESCRIPTION
BRAŞOV
1988
1

EDITORIAL MANAGERS:
Dr. eng. Dan Roman
Dr. Emil M ntean
COVER DESIGN:
designer Livi Derveştean
The COBRA microcomputer as designed and built by the follo ing team:
eng. Vasile Prodan, eng. Sorin Finichi , eng. Bernd Hansgeorg Wagner,
math. Marcel Arefia, math. Mircea Pop, eng. Mircea Ung r,
arch. Alexandr Antal.
This material has been edited by: eng. Vasile Prodan,
eng. Mircea Ung r.
Coordinator: Dr. Eng. Gheorghe Toacşe
2

C O N T E N T S
1. Functional description of CoBra microcomputer . . . . . . . . 4
1.1 Block diagram . . . . . . . . . . . . . . . . 4
1.2 Central Processing Unit . . . . . . . . . . . . . . 5
1.3 Memory . . . . . . . . . . . . . . . . . . 8
1.4 Video controller . . . . . . . . . . . . . . . . 11
2. Microcomputer interfaces . . . . . . . . . . . . . . 16
3. Keyboard . . . . . . . . . . . . . . . . . . . 19
4. Po er supply . . . . . . . . . . . . . . . . . . 22
5. Parts list - floppy disk interface . . . . . . . . . . . . 26
6. Parts list - CoBra microcomputer . . . . . . . . . . . . 27
7. Parts list - keyboard . . . . . . . . . . . . . . . 32
8. Parts list - po er supply . . . . . . . . . . . . . . 33
Connectors - pin description . . . . . . . . . . . . . 35
9. Appendix 1 --- Schematics - CoBra microcomputer . . . . . . . 39
10. Appendix 2 --- Schematics - Floppy disk interface . . . . . . . 55
11. Appendix 3 --- Component placement on circuit boards . . . . . . 59
12. Appendix 4 --- RGB interface for the 002 color monitor . . . . . . 65
3

1. FUNCTIONAL DESCRIPTION OF COBRA MICROCOMPUTER
1.1 BLOCK DIAGRAM
The CoBra microcomputer is built around the 8-bit microprocessor Z80A,
on three circuit boards. The microcomputer block diagram is sho n in Fig.1.
Fig. 1 – CoBra microcomputer block diagram
On the mainboard there are:
— the central processing unit block ith the Z80A μP and address/control
bus amplifiers/separators.
— the memory block consisting of a configuration/selection circuit, a 48
KB DRAM circuit and a 2-16 KB EPROM circuit.
— the video controller consisting of 16 KB DRAM video memory, memory
access priority controller (memory access prioritizer), generators for video
synchronization signals and composite color signals, video memory control
signals generator, and the system clock generator.
— interface block, built around a parallel programmable interface i8255.
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— RS-232 interface for use ith a printer or another computer.
— external memory (magnetic tape) interface.
— audio interface.
— keyboard interface (6x8 key matrix).
— 8 bit input port for general use or used as a Kempsto -compatible
joystick interface.
The conventional keyboard is built on a separate board, as an extended
6x8 key matrix plus ZX SPECTRUM+ compatible compound keys.
The floppy disk interface is built on a third board around the i8272A
Floppy Disk Controller circuit assisted by the Z80-CTC counter/timer circuit.
1.2 CENTRAL PROCESSING UNIT
The central processing unit is built ith the 8-bit microprocessor Z80A.
Z80A is a MOS-LSI integrated circuit in a 40-pin DIP package, having 3 buses:
— the data bus;
— the address bus;
— the control bus.
The data bus D0—D7 is a three-state input/output bus, used for
exchanging information ith the memory and the I/O interface circuits.
Z80A falls ithin the 8-bit microprocessor category, having the capability
to process 8 bits of information simultaneously on its data bus.
The 16-bit address bus is used to address the memory or the I/O devices
during the information exchanges.
Having 16 bits for the address bus, Z80A can address 64 KB of memory
and an additional 64 KB space dedicated to the I/O devices.
The control bus offers the signals required for monitoring the data
transfer to/from microprocessor.
The microprocessor can perform different tasks:
— reads data from memory;
— rites data to memory;
— reads data from I/O devices;
— rites data to I/O devices;
— performs arithmetic operations on data.
Z80A executes a range of 158 types of instructions. In the CoBra
microcomputer, the microprocessor clock signal has a 3.5 MHz frequency.
Pin description:
A0-A15 — the address bus;
— three-state logic outputs, active in “1” logic level;
— can address up to 64 KB memory and I/O devices;
— in the case of I/O, the 8 less significant address bits are used to
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select up to 256 input devices or 256 output devices;
— during the dynamic memory refresh cycle, the contents of the
I and R registers sho s up on the address bus, the 7 less
significant bits of the self-incrementing R register being used as a
refresh address.
D0-D7 — the data bus;
— three-state inputs/outputs, active in “1” logic level.
M1 — machine cycle one;
— output, active in “0” logic level;
— together ith MREQ, indicates that the current machine cycle is the
opcode fetch cycle of an instruction execution;
— M1 and IORQ both active indicate the execution of an interrupt
cycle.
MREQ — memory access request;
— three-state output, active in “0” logic level;
— indicates that the address bus holds a valid address for a memory
read of memory rite.
IORQ — I/O ports access request;
— three-state output, active in “0” logic level;
— indicates that the lo er half of the address bus holds a valid I/O
address for an I/O read or rite operation;
— together ith M1, indicates that an interrupt response vector can
be placed on the data bus.
RD — read;
— three-state output, active in “0” logic level;
— indicates that the CPU ants to read data from memory or an I/O
device.
WR — rite;
— three-state output, active in “0” logic level;
— indicates that the CPU data bus holds valid data to be stored at the
addressed memory or I/O location.
RFSH — refresh;
— output, active in “0” logic level;
— together ith MREQ, indicates that the lo er seven bits of the
system’s address bus can be used as a refresh address to the
system’s dynamic memories.
HALT — halt state;
— output, active in “0” logic level;
— indicates that the CPU has executed a HALT instruction and is
aiting for either a non-maskable or a maskable interrupt ( ith the
mask enabled) before operation can resume. During HALT, the CPU
executes NOPs to maintain memory refresh.
WAIT — ait;
— input, active in “0” logic level;
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— indicates to the CPU that the addressed memory or I/O devices are
not ready for a data transfer;
— the CPU continues to enter a WAIT state as long as this signal is
active ithout refreshing the dynamic memory. Extended WAIT
periods can prevent the CPU from properly refreshing dynamic
memory.
INT — interrupt request;
— input, active in “0” logic level;
— interrupt request is generated by I/O devices. The CPU honors a
request at the end of the current instruction if the internal
soft are-controlled interrupt enable flip-flop (IFF) is enabled and
BUSRQ is not active. INT is normally ired-OR and requires an
external pull-up for these applications.
NMI — non-maskable interrupt;
— input, negative edge-triggered;
— NMI has a higher priority than INT. NMI is al ays recognized at the
end of the current instruction, independent of the status of the
interrupt enable flip-flop, and automatically forces the CPU to
restart at location 0066H.
RESET — CPU reset;
— input, active in “0” logic level;
— initializes the CPU as follo s: it resets the interrupt enable flip-flop,
clears the PC and registers I and R, and sets the interrupt status to
Mode 0. During reset time, the address and data bus go to a
high-impedance state, and all control output signals go to the
inactive state; dynamic memory refresh signals are not
generated. Note that RESET must be active for a minimum of
three full clock cycles before the reset operation is complete.
BUSRQ — bus request;
— input, active in “0” logic level;
— bus request has a higher priority than NMI and is al ays recognized
at the end of the current machine cycle. BUSRQ forces the CPU
address bus, data bus, and control signals MREQ, IORQ, RD, and
WR to go to a high-impedance state so that other devices can
control these lines. BUSRQ is normally ired-OR and requires an
external pull-up for these applications. Extended BUSREQ periods
due to extensive DMA operations can prevent the CPU from
properly refreshing dynamic RAMs.
BUSACK — bus ackno ledge;
— output, active in “0” logic level;
— indicates to the requesting device that the CPU address bus, data
bus, and control signals MREQ, IORQ, RD, and WR have entered
their high-impedance states. The external circuitry can no control
these lines;
— as long as it is active, dynamic memory refresh signals are not
generated.
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1.3 MEMORY
The Z80 microprocessor can directly access any location in a 64 KB
memory block.
In order to have a maximum flexibility for applications, the CoBra
microcomputer is bundled ith the maximum RAM memory that can be
accessed by the microprocessor, i.e. 64 KB. At po er-up, the RAM memory has a
random contents. Therefore the existence of a non-volatile memory is needed,
one that ouldn't lose its contents at po er-off (EPROM). The CoBra computer
can be equipped ith 2 to 16 KB of such a memory, the standard version
having 2 KB.
In this memory there are recorded po er-up specific programs, such as
hard are tests, a test image used for adjusting the black & hite or color
monitor, computer configuration user selection indicating the source of the
operating system to be loaded:
— BASIC interpreter – Sinclair ZX-Spectrum compatible, ith a
monitor program for ork in assembler and ith printing routines
specific for RS-232 serial interface printers;
— Sinclair ZX-Spectrum BASIC interpreter, unmodified, for
applications that verify the genuineness of the existing ROM;
— operating system specialized in assembler ork, ith editor,
assembler, disassembler, copier (ex. OPUS);
— any other user-designed interpreter. (ex. FORTH);
— CP/M compatible floppy disk operating system.
Spectrum-type operating system can be loaded from 16 KB EPROM
memories, from magnetic tape or disk.
The CP/M operating system can only be loaded from disk, its operation
involving the existence of the floppy disk.
On one hand, the Sinclair-Spectrum compatibility requires that the RAM
memory bet een addresses 4000H and 5AFFH contain the information used by
the video controller to display a 256x192 pixel image on the monitor, on the
other hand running the CP/M operating system becomes impossible if the video
memory sho s up in the middle of the transient program area (TPA).
In order to solve this problem created by the dual nature of the
computer, a memory configuration and selection circuit as created that
satisfies the conditions imposed by these three configurations. This circuit is
made of t o D-type flip-flops (U36), a BCD-to-decimal decoder (U56) and gates,
being presented in the block diagram in Fig.2.
The main advantage of this circuit is that it allo s s itching the memory
configuration ith a jump any here in the 64 KB space of the ne
configuration, even if the memory area containing the s itching routine
dissapears as a result of the s itching.
8

Fig. 2 - Memory configuration and selection circuit - block diagram
Its operation makes use of the fact that the R register is 7-bit
incremented after each instruction fetch cycle and appears entirely (8-bit) on
the address bus lines A0—A7, the moment of its appearance being signaled by
the RFSH signal.
A change of bit 7 of the R register by the instruction LD R,A is sho n on
the address bus (BA7) only after the next instruction code as already fetched.
This instruction can be a single-byte jump instruction, such as RST or
JP (HL), hich can achieve the jump of the program counter to any address
ithin the 64 KB memory space. The memory configuration s itching
sequence:
LD R,A ; JP (HL)
is detailed in Fig.3.
The t o flip-flops (U36) are forced to “1” at po er-up, by a circuit made
of C15, D02, R09, D03.
9

Fig. 3 - Memory configuration s itching sequence
The diode D02 makes sure the microprocessor exits the reset state a fe
miliseconds before the NPOR signal turns off. During this time the
microprocessor executes the first instructions here bit 7 of the R register is
set to “1”, hich makes sure the flip-flop U36/5 is maintained at “1” after NPOR
turns off. This is the temporary startup configuration, here the memory map
allo s the microprocessor to access the BOOT EPROM U89, the 16k BASIC EPROM,
the video memory and the 16k DRAM (BANK #0). In this startup configuration,
the RESET button is not to be used, because the contents of the R register
ould be erased, hich leads to a random memory configuration. The user can
choose the configuration anted by pressing one of the follo ing keys:
— B for BASIC interpreter resident in EPROM;
— C for BASIC or other operating system resident on magnetic tape;
— W to check the contact bet een the EPROM memories and their
sockets. The contents of EPROMs are verified byte by byte against
the recording on the magnetic tape. In case of error, the defective
EPROM chip is indicated by flashing the corresponding color in the
test image (0-7);
— D to load the operating system from floppy disk.
After selecting the source of the operating system to be loaded from the
keyboard, the RAM area bet een 8000H and FFFFH is set up accordingly, bit 6 of
the output port FEH is set to 0 or 1 according to the configuration chosen
(BASIC or CP/M respectively) and bit 7 of the R register is brought back to “0”.
The memory configuration ill change after the microprocessor fetched the
code for the JP (HL) instruction from the old configuration.
The map of the memory in these 3 configurations is sho n in Fig. 4.
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Multiplexers U41 and U58 take care of changing the ro and column
address for the 48k DRAM memory (U62-69, U43-U50, U24-U31). In order to
increase speed of operation in CP/M, half of the video DRAM (BANK #1) is
replaced by half of DRAM BANK #0, other ise the execution of BDOS calls ould
be slo ed do n by ait states from the memory access prioritizer. This
memory replacement is achieved by the gates at U52/12, U52/8, U35/3.
Under the BASIC configuration, U54/11 synthesizes the Read Only signal
for DRAM BANK #0, the gate U17/11 allo s access for SPECTRUM-specific 20ms
interrupts, and the asyncronous input U36/1 locks the state of memory
configuration flip-flops regardless of any change in bit 7 of the R register.
1.4 THE VIDEO CONTROLLER
The video image is organized in memory as follo s:
— a 6kB area, called “serial video information area”, hich specifies the
type of every pixel of the screen, as follo s:
if the corresponding bit is 0 then the pixel ill have the color of
“paper”, and if the bit is 1 then the pixel ill have the color of
“ink” for that particular character. The address of this 6kB area
is 4000H for BASIC configuration and C000H for the other t o
configurations;
— a 768 bytes area, called “color attribute area”, hich specifies the
color of “ink” and the color of “paper”, for each character, specifies if
that character should be flashing and if it should have increased
brightness. The address of this area is 5800H for BASIC configuration
and D800H for the other t o configurations.
The block diagram of the video controller is sho n in Fig.5.
11
Fig. 4 - Memory map for the
three configurations

Fig. 5 - Video controller - block diagram
Starting from the 14 MHz clock built ith a quartz oscillator ith gates
(U57), through a division by 2 the dot clock frequency SCLK is obtained - used
for serialization - ith a frequency of 7 MHz, at U61. This signal is further
divided by 8 through the Johnson counter made ith U60 (7495), in order to
generate the character frequency. Gate U40/6 along ith U57/8 ensure the
counter is self-triggered. The main advantage of this 4-bit divider by 8 is that
the outputs' transitions occur one at a time, so at any given moment only one
output changes its state. Through a simple decoding using gates, more signals
are generated - control signals for DRAM 16k BANK #1, control signals for the
serialization registers, the color attributes and the strobe for the data
separation and storage register.
The timing of these signals and also the dual access to the video
memory are both sho n in Fig.6.
On one hand the video controller is accessing the video memory at fixed
time intervals in order to read the serial video information and color attributes,
on the other hand the CPU is accessing the video memory in order to change
the image, the color attributes, the system variables or to store code or data.
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Fig. 6 - The timing of command signals
In order to easier calculate the address of any pixel as ell as the
address of the associated color attribute, e divide the 256x192 px image (or
32x24 characters) as follo s:
— horizontally — 8 adjoined pixels, 8-bit encoded (B7—B0) make up
one character;
— the image contains 32 characters, 5-bit encoded:
C4, C3, C2, C1, C0;
— vertically — 8 sequential TV lines, 3-bit encoded L2, L1, L0,
make up one character;
— 8 character ro s, 3-bit encoded R2, R1, R0 make
up one third of the image;
— the image contains 3 thirds, 2-bit encoded T1, T0,
the “11” combination not being used.
The address of the byte containing bit B of character C, line L, ro R and
third T can be found using formula (1), and the address of the associated color
attribute can be found using formula (2) here:
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X=0 —> BASIC configuration
X=1 —> startup or CP/M configuration
A15 A14|A13 A12 A11 A10 A9 A8 A7| A6 A5 A4 A3 A2 A1 A0
X 1 | 0 T1 T0 L2 L1 L0 R2| R1 R0 C4 C3 C2 C1 C0 (1)
| +--------+ +--------+ +--------+ +----------------+
| T L | R C
| |
X 1 | 0 1 1 0 T1 T0 R2| R1 R0 C4 C3 C2 C1 C0 (2)
+----+ +--------+ +----------------+
T R C
In these formulas e notice the sameness of the A0—A6 address bytes
corresponding to the dynamic memory line address, hich allo s the video
controller to access the memory for the t o separate readings in page mode,
RAS CAS CAS.
The multiplexing of the video addresses is done in t o steps: circuits
U03, U20, U22, U39 do the multiplexing for RAS-CAS microprocessor and RAS-CAS
video controller, and circuit U51 along ith gate U19/8 do the address change
for the t o CAS CAS page-mode accesses of the video controller.
The access of the CPU to DRAM BANK #1 (video) is less prioritized than
the access of the video controller, and is controlled by the memory access
prioritizer made ith U02/5 and U02/9. The access request is signaled by
activating the NCS1 line hich in turn activates NWAIT through the asyncronous
input U02/1. Possible moments of activation for the access request are marked
on the CLK diagram of the CPU clock signal in Fig.6 having beside them the
number of ait states inserted by the memory access prioritizer in each case.
The activation of the video memory access signal VMA leads to activating the
RAS, CAS, WE signals; in case of reading, the byte requested is sampled and
stored in the separation and storage register i8212 (U76) — the moment
marked as (1) in Fig.6. On the positive edge of the QC signal, NWAIT is
deactivated, the microprocessor still maintaining the data read from memory
on the data bus, by means of the DS selection signals of the i8212 circuit.
The access of the video controller to DRAM BANK #1 video is done once
every 1.1µs, this ay also ensuring the memory refresh.
At moment (2) in Fig.6, the data byte is loaded in the video &
serialization register (U78, U82, U83), the role of U83 being that of delaying the
serial data by t o SCLK periods before it reaches the select input of the U80
multiplexer.
At moment (3), the color attribute byte is loaded into the color attribute
register (U77 and U81).
At moment (4) the video information (serialized) reaches the QB output
(U83/12). The time difference bet een moments (3) and (4) can be
compensated by the gate U88/3 along ith C36.
The color of ink or paper selected by U80 is once again multiplexed ith
the border color, by U85.
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Gate U87/8 turns off the electron beam in the monitor during the
horizontal-retrace. The outputs of U85 are normalized in order to yield the
intensity signal, and separated through U86 to yield the R, G, B, I and sync
signals for the color monitor. U88/11 along ith T1 generates the B/W
composite video signal.
The oscillator made of U88/6, U88/8 is controlled by the FD7 signal,
together ith gate U88/3 achieving the FLASH function. Resistor R43 ensures
the blinking oscillator is in sync ith the TV vertical sync signal. Its value must
be chosen so that the oscillator flips during any TV line except the 192 ones
that are visible.
The diode gates that synthesize the BD6N signal, along ith R73, achieve
the BRIGHT function, at the same time suppressing it for color black.
Circuits U12 and U13 and gates U16, U14 make up a divider by 56. The
outputs of this divider are being used as character address for the video
controller and are the basis for horizontal sync and retrace signals. The
associated signal timings are sho n in Fig.7.
Fig. 7 - The timings for TV line signals
Circuits U32, U33, U15/9 and gates U37, U34 make up a divider by 312,
their outputs being used as a TV line address, character ro address and
screen third address on one hand, and on the other hand they are the basis for
generating the NBRD and NVS vertical sync signals.
The associated timings are sho n in Fig.8.
15

Fig. 8 - Timings for TV frame signals
2. MICROCOMPUTER INTERFACES
Gates U54/6, U54/8 synthesize reading and riting signals from/to I/O
ports. These signals are required for INTEL family interface circuits. The
mainboard uses a programmable peripheral interface (i8255) hich has three
input/output ports and a control port as follo s:
port A — input port, address 254 (FEH);
port B — input port, address 31 (1FH);
port C — output port, address 254 (FEH);
control port, address 223 (DFH), value 146 (92H).
∘ Bytes 0—5 of port A are used for reading the columns from the keyboard
matrix.
∘ Bit A6 is used for reading data from the external memory on magnetic
tape. The audio signal from tape is limited by R98, D10, D9 and formatted by
U92 (op. amp.).
∘ Bit A7 is used as serial input, protected by R94 and D05. It can be used as
RS-232 serial input hen driven by a serial data reception routine (driver).
Input bits of port B can have a general use as an 8-bit parallel port at
address 223 (DFH), ith protocol signals PA5 for input and PC5 for output.
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∘Bits 0—4 of port B can be used as Kempston-compatible Joystick interface.
Resistors R99:106 ensure a “0” reading in stand-by, resistor R107 ensure a
“1” level through one of the joystick contacts.
∘Bits 0—2 of port C are used for storing the BORDER color.
∘Bit 3 serves as output for tape recording. Resistors R97, R98 and diodes
D06, D07 ensure an optimum level for the majority of tape recorders.
∘Bit 4 is used as audio output. The i8255 circuit can directly drive a
telephone speaker through C45, speaker mounted in the microcomputer's case.
Bit 5 is a general use output bit. Can be used as a protocol line for port ∘B.
Bit 6 is an output line. It indicates the configuration selected at startup. In∘
a particular configuration it can be used as a general use bit.
Bit 7 is a serial output. It is separated and inverted by ∘U87/11, the level
being adapted by T2 to be RS-232C compatible. It is used as a serial data
transmission bit to a printer or another computer, using an emission routine.
The floppy disk interface is built on a separate board using the dedicated
floppy disk controller circuit i8272.
To be able to use the features of Mode 2 Interrupts of the microprocessor,
the interrupts generated by i8272 are passed through the counter/timer
channels circuit Z80-CTC (U01). This circuit has four counters of hich counters
0 to 2 are cascaded. By programming, channel 0 CTC generates one interrupt
for each byte to be transferred bet een i8272 and microprocessor; channels 1
and 2 cascaded generate an interrupt at the end of the sector also generating
the Terminate Count (TC) signal for i8272. In this hard are configuration,
i8272 can be programmed to ork ithout direct memory access, simplifying
the interface very much.
The floppy disk interface block diagram is sho n in Fig.9.
The clock signal generated by the 16 MHz quartz oscillator is divided by 2 or by
4 depending on the position of the s itches SD0-3 and is used as a clock for
i8272. Remarkable is this original configuration here i8272 - by means of the
selection signals US0, US1 - selects its o n 8 or 4 MHz clock frequency for ork
ith 8” or 5¼” floppy drives. This configuration allo s the use of 2 floppy drives
simultaneously regardless of their sizes, ithout having to intervene by means
of soft are to s itch the clock frequency to the floppy disk controller.
The circuit made ith U04/9 and U03/4 performs the multiplexing for
READY signals coming from floppy drives.
The double decoder circuit U05 generates SELECT signals for floppy
drives, as ell as HEAD LOAD signals for the reading/ riting heads of the drives.
Signals HL0-3 (HEAD LOAD) can also be used as MOTOR ON signals for 5¼”
floppy drives hich have this input line.
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Fig. 9 - Floppy disk interface block diagram
In order to reduce the symbol crossover interference at rite operations,
a circuit made ith U18, U12 is used, that ensures precompensation for data to
be ritten.
Gates U16, U03, U06, U10 take care of multiplexing and level translation
for command signals of the floppy drives.
Gates U16, U15, U14/6, U14/8 and counter U08 generate the rite clock
signal WCK and clock signal CK depending on the selected simple or double
(MFM) density.
Circuits U13, U07, U14/12, U09 make up a phase locked loop circuit
(digital PLL) that is used to synthesize the data indo RDW signal (Read Data
Windo ) starting from the transitions of data received from the selected floppy
drive. If input U07/13 is in “1” logic level, U13 along ith U07 make up a regular
divider-by-16 circuit. The positive edge of the USD signal from the floppy drive
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triggers a sampling of the current count of this divider. If the sample is 0, the
frequency generated by the 16-divider is considered to be synchronous ith
data arriving from the floppy drive and the counter keeps counting. If the
sample is not zero, a positive or negative jump by 1 or 2 is made in the
counting sequence, according to the shift that as detected, so that the
number in the 16-divider is brought closer to the correct synchronousness
value. The 71488 PROM is programmed as follo s:
Address Co te ts Shift Address Co te ts
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
01
01
02
03
03
04
05
06
0B
0C
0D
0E
0F
0F
00
01
0
-1
-1
-1
-2
-2
-2
-2
+2
+2
+2
+2
+2
+1
+1
+1
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
00
Circuit U09/6 performs a division by 2 on the output signal coming from
the 16-divider, so that the RDW signal (data indo ) is generated from the clock
signal CK through a division by 32 ith a compensation of the shift occuring
bet een RDW and the data read from the floppy disk.
3. KEYBOARD
The keyboard consists of 58 keys, of hich 48 are organized as an 8x6
matrix, and the other 10 are used for generating some commands that on a
standard ZX SPECTRUM are generated by simultaneously pressing CAPS SHIFT
and another key.
The detection of a key press is done as follo s: hen interrogating the
keyboard, the keyboard lines are connected to the higher 8 microprocessor
address lines (A8—A15) separately through diodes D11—D18. During a keyboard
reading cycle, these lines are sequentially brought to a “0” logical level, one by
one, one at a time hile the other 7 are in a “1” logical level. If a key is
pressed, by the electrical contact made in that particular matrix node, the “0”
level is propagated through the column (k0—k6) corresponding to the key that
as pressed, all the ay to the PA input port of the i8255 circuit.
The keyboard schematics are sho n in Fig.10 and Fig.11.
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Fig. 10 - Keyboard schematic
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