LSI L64777 User manual

L64777
DVB QAM Modulator
Order Number I14031.A
Technical Manual
June 2000

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000121-01, First Edition, June 2000.
This document describes revision A of the LSI Logic Corporation L64777 DVB
QAM Modulator and will remain the official reference source for all revisions of
this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, G10, and the G10 logo design, are trademarks or
registered trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.

Preface iii
Preface
This book is the primary reference and technical manual for the L64777
DVB QAM Modulator. It contains a complete functional description for the
L64777 and includes complete physical and electrical specifications for
the L64777.
Audience
This document assumes that you have some familiarity with digital video
broadcasting, QAM modulators, and related support devices. The people
who benefit from this book are:
•Engineers and managers who are evaluating the modulator for
possible use in a system
•Engineers who are designing the modulator into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Introduction, introduces the L64777 DVB QAM
Modulator.
•Chapter 2, Modulator Architecture, describes the functional
components of the L64777.
•Chapter 3, Interfaces, describes the L64777 interfaces.
•Chapter 4, Register Descriptions, describes the registers used to
configure and monitor the L64777.
•Chapter 5, Signals, presents the signal definitions for the L64777.

iv Preface
•Chapter 6, Specifications, presents the electrical and timing
specifications for the L64777. It also presents the pinout and
packaging information.
•Appendix A, Programming the L64777 in Serial Host Interface
Mode, discusses how to program the L64777 internal registers and
data tables in serial host interface mode.
•Appendix B, PLL Divider Settings and L64724/34 Connection,
lists the PLL divider settings for typical applications. It also describes
the L64777 connection to the L64724.
•Appendix C, Monitoring Device Internal Signals, describes how to
program test register (14) for monitoring of device internal signals.
Related Publications
Digital Broadcasting Systems for Television Sound and Data Services:
Framing Structure, Channel Coding and Modulation Cable Systems
ETS 300 429, September 1996.
Generic Coding of Moving Pictures and Associated Audio ,
ISO/IEC 13818-1, MPEG2 Systems, November 1994.
G10
®
-p CW900100 10-Bit Direct Digital Synthesis Digital-to-Analog
Converter, Preliminary Datasheet , LSI Logic, September 1998.
L64724 Satellite Receiver Technical Manual, LSI Logic, April 2000, order
number I14030.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Contents v
Contents
Chapter 1 Introduction
1.1 Overview 1-1
1.2 Operating Environment 1-2
Chapter 2 Modulator Architecture
2.1 Introduction 2-2
2.2 PLL Modes 2-4
2.2.1 PLL Mode 1 2-4
2.2.2 PLL Mode 2 2-5
2.3 I/O 2-6
2.3.1 Input 2-6
2.3.2 Output Signals 2-6
2.3.3 Control Interface 2-8
2.3.4 Serial Microprocessor Interface 2-10
2.4 Input Synchronization 2-10
2.4.1 Sync Acquisition Phase 2-13
2.4.2 Sync Tracking Phase 2-14
2.5 FIFO Clock Conversion 2-16
2.6 Sync/EF Reinsertion Unit 2-17
2.6.1 Sync Insertion Mode 2-18
2.6.2 Error Flag Insertion 2-18
2.6.3 Energy Dispersal (Scrambler) Unit 2-18
2.7 Reed-Solomon Encoder 2-20
2.7.1 Forward Error Correction (FEC) 2-21
2.7.2 Error Handling and Correction 2-22
2.8 Convolutional Interleaver 2-23
2.9 Bytes to M-tuples Converter 2-24
2.10 Differential Encoder and QAM Mapping 2-26
2.11 Square Root Nyquist Filter 2-27

vi Contents
2.11.1 Filter Setup Procedure 2-29
2.11.2 Example 2-30
2.11.3 Default Filter Characteristics 2-34
2.12 Global Control and PLL Module 2-34
2.12.1 Numerically Controlled Oscillator (NCO) 2-35
2.12.2 Acquisition Phase Using the Frequency
Measurement Unit 2-36
2.12.3 Autoacquisition Mode 2-38
2.12.4 Regulation Phase 2-39
2.13 Interpolator 2-39
2.14 Serial Microprocessor Interface 2-40
2.15 Test Unit 2-41
Chapter 3 Interfaces
3.1 Transport Interface 3-1
3.1.1 Synchronization 3-1
3.1.2 Synchronization Methods 3-2
3.1.3 Transport Error Indicator Handling 3-2
3.2 Serial Control Interface 3-2
3.3 Analog Output Interface 3-3
3.4 Digital Output Interface 3-6
Chapter 4 Register Descriptions
4.1 Group 2 General-Purpose Registers 4-1
4.1.1 Register 0 4-4
4.1.2 Register 1 4-4
4.1.3 Register 2 4-5
4.1.4 Register 3 4-5
4.1.5 Register 4 4-6
4.1.6 Register 5 4-6
4.1.7 Register 6 4-7
4.1.8 Registers 7 and 8 4-8
4.1.9 Registers 9 and 10 4-8
4.1.10 Register 11 4-9
4.2 NCO-Related Registers 4-10
4.2.1 Register 12 4-10
4.2.2 Register 13 4-11

Contents vii
4.2.3 Register 14 4-12
4.2.4 Register 15 4-13
4.2.5 Registers 16, 17, and 18 4-13
4.2.6 Registers 19 and 20 4-13
4.2.7 Registers 21 and 22 4-14
4.2.8 Registers 23 and 24 4-14
4.2.9 Register 25 4-14
4.2.10 Registers 26, 27, and 28 4-14
4.2.11 Registers 29, 30, and 31 4-15
4.2.12 Registers 32, 33, and 34 4-15
4.2.13 Registers 35, 36, and 37 4-15
4.2.14 Registers 38 and 39 4-16
4.2.15 Register 40 4-16
4.2.16 Register 41 4-16
4.2.17 Register 42 4-17
4.2.18 Register 43 4-17
Chapter 5 Signals
5.1 Overview 5-1
5.2 MPEG Transport Stream Multiplexer Signals 5-3
5.3 Status Information Signals 5-4
5.4 Test Signals 5-5
5.5 Control Signals 5-6
5.6 External PLL Signals 5-6
5.7 Analog QAM Signals 5-7
5.8 Serial Microprocessor Interface Signals 5-8
Chapter 6 Specifications
6.1 AC/DC Specifications 6-1
6.1.1 Electrical Ratings 6-1
6.1.2 AC Timing Diagrams for L64777 6-3
6.2 Pin Descriptions and Lists 6-5
6.2.1 L64777 Electrical Pin Descriptions 6-5
6.2.2 Numerical Pin List for the L64777 6-8
6.2.3 Alphabetic Pin List for the L64777 6-9
6.3 Package Pinout 6-10

viii Contents
Appendix A Programming the L64777 in Serial Host Interface Mode
A.1 Serial Bus Protocol Overview A-1
A.2 Programming the Slave Address Using the Serial
Bus Interface A-4
A.3 Write Cycle Using the Serial Bus Interface A-4
A.4 Read Cycle Using the Serial Bus Interface A-5
A.5 Limitations A-7
Appendix B PLL Divider Settings and L64724/34 Connection
B.1 Overview B-1
B.2 PLL Driver Settings for Typical Applications B-2
B.3 Connecting the L64777 to the LSI Logic L64724 B-3
Appendix C Monitoring Device Internal Signals
Customer Feedback
Figures 1.1 L64777 Operating Environment 1-2
2.1 ETS 300 429-Compliant Modulation Operation 2-2
2.2 Data Path 2-3
2.3 Phase and Frequency Detection with an External VCO 2-5
2.4 Analog I/Q Output Interface Diagram 2-7
2.5 Required Relation of ICLK and DIN/DVALIDIN 2-9
2.6 FIFO Clock Conversion 2-12
2.7 Sync Acquisition Phase 2-13
2.8 Sync Tracking Phase 2-14
2.9 FIFO Pointer Concept 2-16
2.10 Transport Error Flag Insertion 2-18
2.11 Scrambler Basic Serial Architecture 2-19
2.12 Shift Register Initialization Sequence 2-19
2.13 Code Word Structure 2-21
2.14 Forward Error Correction Data Path 2-22
2.15 Interleaver Block Diagram 2-23
2.16 Symbol Cutting From Bytes 2-25

Contents ix
2.17 Byte to Symbol Conversion 2-25
2.18 Differential Encoder and QAM Mapping 2-26
2.19 Pulse Shaper Structure 2-27
2.20 Output Scaling by Arithmetic Shift Right 2-29
2.21 Square-Root Raised Cosine Filter 2-34
2.22 NCO Loop Diagram 2-36
2.23 Frequency Acquisition Loop Overview 2-38
2.24 Serial Bus Base Address 2-40
3.1 Analog I/Q Output Interface Diagram 3-4
3.2 I And Q DAC Filter Diagrams 3-5
5.1 Logic Symbol for the L64777 5-2
6.1 TS Input Timing 6-3
6.2 L64777 RESET Timing Diagram 6-3
6.3 L64777 Bus 3-state Delay Timing 6-4
6.4 Package 120-Pin PQFP Pinout 6-10
6.5 120-Pin PQFP (PE) Mechanical Drawing 6-11
A.1 Quick Overview of the Serial Bus A-2
A.2 Serial Bus Write/Read Cycle A-3
A.3 General Call Structure A-4
A.4 Burst Write to Slave (Master-Transmitter, Slave-Receiver) A-5
A.5 Single Read from Slave A-7
B.1 CATV Block Diagram B-1
B.2 Signals between the L64724 and L64777 B-3
Tables 2.1 Allocation of Coefficient-Bits for Phase 0 2-30
2.2 Default Nyquist Filter Coefficients 2-32
4.1 Group 2 Bit Allocation 4-2
4.2 Reset Values for Register Fields 4-17
6.1 L64777 Absolute Maximum Ratings 6-2
6.2 L64777 Recommended Operating Conditions 6-2
6.3 L64777 DC Characteristics 6-2
6.4 L64777 Preliminary Timing Parameters 6-4
6.5 L64777 Pin Description Summary 6-5
6.6 L64777 Numerical Pin List 6-8
6.7 L64777 Alphabetical Pin List 6-9
B.1 Typical Settings of CNT_I and CNT_O B-2

x Contents

L64777 DVB QAM Modulator Technical Manual 1-1
Chapter 1
Introduction
This chapter provides an introduction to the L64777. It consists of the
following sections:
•Section 1.1, “Overview,” page 1-1
•Section 1.2, “Operating Environment,” page 1-2
1.1 Overview
The L64777 chip implements a QAM modulator that is digital video
broadcasting (DVB)-compliant, as described in document ETS 300 429.
The input is an MPEG-2 system layer-compliant transport stream either
in parallel byte-wide or serial format. The chip contains digital signal
processing functions, digital-to-analog converters, and sampling clock
circuitry that generates a quadrature amplitude modulation (QAM)-
modulated output signal in baseband. Users can configure the device by
means of its serial interface.
The L64777 chip design is based on the existing LSI Logic L64767
device and includes the following major enhancements:
•Two internal digital-to-analog converters generate in-phase and
quadrature (I and Q) baseband signals.
•An on-chip voltage-controlled oscillator improves the symbol rate
PLL to support most frequently used application ranges.
•A serial interface replaces the eight-bit microprocessor interface.
•A digital numerically controlled oscillator (NCO) and interpolation
mode support operation with the L64724 device.

1-2 Introduction
1.2 Operating Environment
The modulator is intended to follow either an MPEG transport stream
source (for example, a transport multiplexer) or a satellite receiver, such
as the LSI Logic L64724 (see Figure 1.1). It processes MPEG-2 system-
compliant frames at the input.
You can program the sync word and block length, and the chip can
reinsert the sync information. The device handles the MPEG-specific
transport-packet error indication (TEI) bit internally.
Figure 1.1 L64777 Operating Environment
The features of the L64777 include:
•DVB standard ETS 300 429-compliant modulation operation
•Highly integrated global synchronization and clock control
•On-chip VCO to support symbol rates up to 10 Msymbols/s
•Digital NCO and interpolation mode to support operation with the
L64724
•Four-fold Nyquist filter oversampling
•Maskable interrupts for all error conditions
•Individual module bypass configuration modes
•I and Q baseband outputs both in digital and analog formats
•I2C-compatible serial interface for control, setup, and monitoring of
various chip parameters
•User-controllable input synchronization schemes
•16, 32, 64, 128, and 256 QAM modes
•Reed-Solomon encoder
MPEG Transport MUX
QPSK Satellite Receiver L64777
QAM Cable
Network
RF
Modulator
Transmission Network
Mixer
MPEG Transport
Stream (Digital)
Analog QAM
Modulated I and Q
Components

Operating Environment 1-3
•Frame sync byte reinsertion
•Input jitter handling and Reed-Solomon gap insertion by a 128-word
circular FIFO buffer
•IEEE 1149.1 JTAG interface for testing
•Up to 10 Mbytes/s parallel data input
•Up to 60 Mbits/s serial data input
•Up to 11.25 Mbaud operation in NCO mode of operation
•Easy interface to most input sources
•85 ˚C ambient operation without special cooling devices
•Unconstrained serial mode to allow modulation of non-MPEG data
stream

1-4 Introduction

L64777 DVB QAM Modulator Technical Manual 2-1
Chapter 2
Modulator Architecture
This chapter briefly introduces the standard modulator chain and the
architecture the device uses to implement the chain. This chapter
consists of the following sections:
•Section 2.1, “Introduction,” page 2-2
•Section 2.2, “PLL Modes,” page 2-4
•Section 2.3, “I/O,” page 2-6
•Section 2.4, “Input Synchronization,” page 2-10
•Section 2.5, “FIFO Clock Conversion,” page 2-16
•Section 2.6, “Sync/EF Reinsertion Unit,” page 2-17
•Section 2.7, “Reed-Solomon Encoder,” page 2-20
•Section 2.8, “Convolutional Interleaver,” page 2-23
•Section 2.9, “Bytes to M-tuples Converter,” page 2-24
•Section 2.10, “Differential Encoder and QAM Mapping,” page 2-26
•Section 2.11, “Square Root Nyquist Filter,” page 2-27
•Section 2.12, “Global Control and PLL Module,” page 2-34
•Section 2.13, “Interpolator,” page 2-39
•Section 2.14, “Serial Microprocessor Interface,” page 2-40
•Section 2.15, “Test Unit,” page 2-41

2-2 Modulator Architecture
2.1 Introduction
The L64777 implements the modulator processing chain defined in
ETS 300 429. This processing chain is illustrated in Figure 2.1.
Figure 2.1 ETS 300 429-Compliant Modulation Operation
Figure 2.2 is a block diagram of the L64777 architecture. The input clock
drives only the input synchronizing stage. The OCLK, which is four times
the QAM symbol rate, is the base of all residual processing.
A numerically controlled oscillator (NCO) module allows the L64777 to
interface with LSI Logic L64724. In this case, the chip must receive the
L64724 PCLK clock; thus, the byte_clock output from L64724 must be
applied to ICLK. This assumes the PCLK has generated the byte clock.
Energy
Dispersal
RS
(204,188)
Encoder
Convol.
Interleaver QAM Mapping
Byte to
m-tuple
conversion
Differential
Encoder
I
Q
Square
Root
Nyquist
Filter

Introduction 2-3
Figure 2.2 Data Path
88
RS
(204,188)
Encoder Convol.
Interleaver & QAM
Mapping
Byte to
m-tuple
Global Control and Synchronization - Start/Stop Signals Generation
ICLK
Serial Microprocessor Interface
OCLK
1
Data Square
Root
Nyquist
Filter
Circular I
Q
Diff.
Encoder
Input
Sync Energy
Dispersal
8
SCAN chain
JTAG Test
RAMbist
Sync &
FIFO Error flag
Reinsertion
Stage
Buffer
Symbol Clock
Generation PLL
(incl. VCO and
Phase and Freq.
Comp.)
SCL SDA
OCLK
Inter-
polator*
PCLK
NCO*
DAC
DAC
I
Q
* Only used in PLL Mode 2
10
divided ICLK & freq compare
128
88 8
10
10
10
m
Q
I
Word

2-4 Modulator Architecture
The QAM mapping supports 16, 32, 64, 128, and 256 QAM. The input
to the device is an MPEG-2 compliant transport stream; its output
consists of baseband QAM signals in I and Q.
2.2 PLL Modes
Connecting the L64777 to a satellite receiver and the LSI Logic satellite
decoder chip set requires the PLL circuits to lock the input and output
clocks. Two modes can achieve this:
•Mode 1 uses the phase/frequency detector and the dividers of
L64777 to accept an external VCO.
•Mode 2 connects the PCLK output of L64724 or L64734 to the
L64777 PCLK clock input, and connects the byte clock output to the
ICLK input of the L64777. This is also called the Numerically
Controlled Oscillator (NCO) mode of operation. This mode is
dedicated to the connection of the L64724 (see Appendix B, PLL
Divider Settings and L64724/34 Connection).
Set the PLL_MODE[1:0] pins to the values shown on page 5-6. Do not
change it during operation.
2.2.1 PLL Mode 1
Figure 2.3 shows the phase and frequency detection for an external
voltage-controlled oscillator (VCO) loop. Choose between frequency and
phase detection through the microprocessor interface.

PLL Modes 2-5
Figure 2.3 Phase and Frequency Detection with an External VCO
Prescalers (CNT_I) and a divider (CNT_O) in the feedback loop of the
PLL generate the internal operating clock (OCLK). Program the 15-bit
prescalers through the microprocessor interface, selecting values for
CNT_I and CNT_O that minimize CNT_O and reach the required ratio.
2.2.2 PLL Mode 2
In Mode 2, the PCLK input provides an external clock. The L64777 uses
the internal NCO to lock to the transport byte clock, provided at ICLK.
The chip generates an OCLK internally. Select PCLK to be at least twice
the frequency of the internal OCLK. Appendix B, PLL Divider Settings
and L64724/34 Connection, describes the connection between the
L64777 and the L64724 in Mode 2 operation.
Consecutive sync blocks can have any gap length between them. Thus,
the L64777 can convert an input block to a block with a gap for RS
insertion, as long as the size of the 128-byte circular input buffer is
sufficient to insert RS gaps and to cope with possible PLL jitter. For an
encoder with 16-parity RS insertion, the L64777 selects the size of the
circular input buffer with sufficient margin.
When operating on public synchronous networks (such as the
synchronous digital hierarchy, SDH, or plesiochronous digital hierarchy,
PDH), the system designer must consider possible jitter on the input
network. The design of the L64777 permits short-term deviations of
input-to-output frequency of ±56 bytes before a FIFO overrun condition
occurs. This is sufficient for operations on SDH or PDH networks.
OCLK
ICLK
+Z −current
Load
Value
Load
Value CNT_O
CNT_I Frequency Detect
Phase Detect
FREQ_PHASE_COMP (From Microprocessor)
2
2
From VCO
To VCO
PLL_CS
%2 %2

2-6 Modulator Architecture
On ATM networks, you must prebuffer input data to get a continuous
frame rate at the chip input. If high input jitter occurs over an ATM without
a prebuffer, the whole PLL regulation of the input-to-output frame rate
fails. You must design the size of the prebuffer according to the maximum
jitter expected over the asynchronous transfer mode (ATM) network.
2.3 I/O
The following subsections describe the input and output of the L64777.
2.3.1 Input
The QAM Modulator accepts serial input data at a maximum 54 MHz
clock frequency on the ICLK pin. In Byte-Parallel Input mode (Parallel
mode), the maximum frequency on ICLK is 10 MHz. DVALIDIN
distinguishes between valid and invalid input data on DIN[7:0]. ERRORIN
marks incorrect packets in the transport header, in case a preceding
device passes erroneous information. The input error flag is transferred
into the TRANSPORT_ERROR_INDICATOR bit of MPEG transport
packets. Either the FSTARTIN pulse or the SYNC_BYTE detection (0x47
for MPEG transport packets) establishes input synchronization.
The FSTARTIN pulse marks the first bit, the most significant bit of an
MPEG SYNC_BYTE in Serial Input mode (Serial mode), or the
SYNC_BYTE in Parallel mode. The FSTARTIN pulse synchronizes the
process of forming bytes from bits in Serial mode. If no such
synchronization signal is applied, the input synchronizer searches for the
programmed SYNC_BYTE occurring in the programmed sync length. In
Parallel mode, the L64777 assumes the byte boundaries are correct and
compares the SYNC_BYTE in parallel to the incoming bytes. A flywheel
circuit stabilizes the synchronization to a SYNC_BYTE, while
synchronization by external pulses feeds directly into the internal control
circuits (see Section 2.4, “Input Synchronization,” page 2-10).
2.3.2 Output Signals
The L64777 outputs the I and Q components of its signal on two
separate analog output interfaces (see Figure 2.4). The output interface
contains two internal 10-bit digital-to-analog converters.