LSI EB402 User manual

®
l14020.A
EB402 Evaluation Board
USER’S GUIDE
July 2001

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB15-000143-01, First Edition (July 2001)
This document describes Revision 1 and Revision 2 of the LSI Logic Corporation
EB402 Evaluation Board and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and ZSP are trademarks or registered trademarks of
LSI Logic Corporation. Solaris is a trademark of Sun Microsystems, Inc. Windows
95, Windows 98, Windows 2000, and Windows NT are registered trademarks of
Microsoft Corporation. All other brand and product names may be trademarks of
their respective companies.
GL
To receive product literature, visit us at http://www.lsilogic.com. and
http://www.zsp.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html

Preface iii
Preface
This document is the primary reference and user’s guide for Revision 1
and Revision 2 of the EB402 Evaluation Board. Unless otherwise noted,
references to the EB402 apply to Revision 1 and Revision 2 printed
circuit boards (PCBs). LSI Logic incorporated the following changes in
Revision 2 of the EB402 Evaluation Board:
•Added + 9 VDC power to SPORT0 and SPORT1 to increase serial
port versatility.
•Added Macraigor JTAG Interface (J5 reserved on Revision 1).
•Added Diode CR1 to PCB to accommodate Macraigor JTAG Interface.
The EB402 is the evaluation board for LSI402ZX Digital Signal
Processors (DSPs). In this manual, the EB402 Evaluation Board is
referred to as the EB402.
Audience
This document assumes that you are familiar with DSPs and related
support devices. The people who benefit from this book are:
•Engineers and managers who are evaluating the LSI402ZX DSP for
possible use in a system.
•Engineers who are designing the LSI402ZX DSP into a system.

iv Preface
Organization
This document has the following chapters:
•Chapter 1, Introduction, provides an overview of the EB402 and
describes its features.
•Chapter 2, Installation, explains how to install EB402 hardware and
verify its functionality with an RS-232-based or a JTAG-based emulator.
•Chapter 3, Hardware Overview, describes the LSI402ZX DSP signals,
the EB402 external interfaces, and the on-board memory configuration.
•Chapter 4, Operation, explains the EB402 operating modes.
•Chapter 5, Board Layout and Jumper Settings, shows the physical
layout of the EB402, lists jumpers and their default settings, and
provides the pinouts for the PCB interface connectors.
•Appendix A, Schematics, contains the schematics for the EB402
and the BD-EBM-CODEC-1 Codec Daughterboard.
•Appendix B, Bill of Materials, lists the materials used in the EB402
and the BD-EBM-CODEC-1 Codec Daughterboard.
Related Publications
The following documents provide supplemental information:
LSI402ZX Digital Signal Processor User’s Guide, LSI Logic Corporation,
Order No. R14021.B.
ZSP Digital Signal Processor Architecture Technical Manual, LSI Logic
Corporation, Order No. l14036.A.
EB402 Evaluation Board Getting Started, LSI Logic Corporation, Order
No. R14019.A.
ZSP SDK Software Development Kit User’s Guide, LSI Logic
Corporation, Order No. R14013.A.

Preface v
Embedded ZSP Development Guide and associated documents for
MULTI version 3.5, Green Hills Software.
ZSP web site, www.zsp.com.
If you would like further information about components that are not
LSI Logic products, refer to the manufacturers’ information.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Courier typeface (Courier) is used for source code. Courier typeface is
also used for information that is displayed on a terminal monitor.

vi Preface

Contents vii
Contents
Chapter 1 Introduction
1.1 Product Features 1-1
1.2 Operating Modes 1-2
1.2.1 JTAG Mode 1-2
1.2.2 RS-232 Mode 1-3
1.2.3 Stand-Alone Mode 1-3
1.3 Block Diagram 1-4
1.4 Packing List 1-5
1.5 Related Components 1-5
Chapter 2 Installation
2.1 Board Layout 2-1
2.2 Preparing to Install the Evaluation Board 2-2
2.3 Installing the Evaluation Board 2-3
2.4 Power-Up Sequence 2-5
Chapter 3 Hardware Overview
3.1 Clock and Control Signals 3-3
3.1.1 CLKIN (Master Clock Input) 3-3
3.1.2 CLKOUT (DSP Clock Output) 3-3
3.1.3 PLLBYPASS (PLL Bypass) 3-4
3.1.4 PLLSEL[3:0] (PLL Multiplier Select) 3-4
3.1.5 RSTN (Device Reset) 3-5
3.1.6 IBOOT (Memory Map Select) 3-6
3.1.7 INT[4:0] (External Hardware Interrupts), NMI
(Nonmaskable Interrupt) 3-6
3.1.8 HALT (Halt Processor Clock) 3-7
3.2 PIO[7:0] (Programmable I/Os) 3-7

viii Contents
3.2.1 Controlling the Codecs 3-8
3.2.2 Controlling the HPI Mode 3-9
3.2.3 Controlling the External Expansion Interface (EEI) 3-9
3.2.4 Controlling Test and Debug Configurations 3-9
3.3 External Interfaces 3-10
3.3.1 JTAG Interfaces 3-11
3.3.2 RS-232 Interface 3-13
3.3.3 BD-EBM-CODEC-1 Daughterboard 3-14
3.3.4 Host Processor Interface (HPI) 3-18
3.3.5 External Expansion Interface (EEI) 3-19
3.3.6 Discrete LED Display 3-19
3.4 Memory and Memory-Mapped Peripherals 3-19
3.4.1 Internal Memory 3-20
3.4.2 External Memory and Memory-Mapped
Peripherals 3-20
Chapter 4 Operation
4.1 Boot Modes 4-1
4.2 JTAG Emulation 4-2
4.2.1 JTAG Software Tools 4-2
4.2.2 JTAG Hardware Tools 4-3
4.2.3 Installing JTAG Tools 4-4
4.2.4 Using JTAG Tools 4-4
4.3 RS-232-Based Emulation 4-4
4.3.1 Connecting RS-232 Hardware 4-5
4.3.2 Installing SDK and Using the RS-232 Interface 4-5
4.4 Using Stand-Alone Mode 4-6
Chapter 5 Board Layout and Jumper Settings
5.1 EB402 Jumpers 5-2
5.2 External Connectors 5-5
Appendix A Schematics
Appendix B Bill of Materials
Customer Feedback

Contents ix
Figures 1.1 EB402 Block Diagram 1-4
2.1 Board Layout 2-2
3.1 Evaluation Board Block Diagram 3-2
3.2 Corelis JTAG Connector 3-11
3.3 Macraigor JTAG Connector 3-12
3.4 RS-232 Interface 3-13
3.5 Serial Port Interfaces to Codec Daughterboards 3-14
3.6 J3, BD-EBM-CODEC-1 Serial Port Connector 3-15
3.7 EBM CODEC-1 Board Layout 3-17
3.8 External Memory 3-21
4.1 JTAG Emulation Tools 4-4
4.2 RS-232-Based Emulation 4-5
5.1 Evaluation Board Layout 5-2
5.2 J5, Macraigor, JTAG Connector 5-6
5.3 J6, HPI Interface Connector 5-7
5.4 J7, Corelis JTAG Interface Connector 5-7
5.5 J10, RS-232 Interface Connector 5-8
5.6 J3, SPORT0 Daughterboard Interface Connector 5-8
5.7 J2, SPORT1 Daughterboard Interface Connector 5-9
5.8 J11, EEI A/D Connector 5-10
5.9 J8, EEI Control Connector 5-11
A.1 EB402 Schematics (Sheet 1 of 6) A-2
A.2 EB402 Schematics (Sheet 2 of 6) A-3
A.3 EB402 Schematics (Sheet 3 of 6) A-4
A.4 EB402 Schematics (Sheet 4 of 6) A-5
A.5 EB402 Schematics (Sheet 5 of 6) A-6
A.6 EB402 Schematics (Sheet 6 of 6) A-7
A.7 BD-EBM-CODEC-1 Schematic Sheet 1 of 1 A-8
Tables 3.1 PLL Multiplier Selections 3-4
3.2 LSI402ZX External Interrupt Signal Use 3-6
3.3 PIO Signal Use 3-8
3.4 BD-EBM-CODEC-1 Audio Connectors 3-16
3.5 BD-EBM-CODEC-1 Jumper Settings and Descriptions 3-18

x Contents
3.6 Memory Chip Select 3-24
5.1 Evaluation Board Jumper Settings and Descriptions 5-3
5.2 Connector Summary 5-5
B.1 EB402 Bill of Materials B-1
B.2 BD-EBM-CODEC Bill of Materials B-5

EB402 Evaluation Board User’s Guide 1-1
Chapter 1
Introduction
The EB402 is the evaluation board for the LSI Logic Corporation
LSI402ZX Digital Signal Processor (DSP) device. The EB402 provides a
hardware platform for evaluating the device and a software platform for
developing, debugging, and demonstrating real-time applications for the
LSI402ZX DSP. The EB402 also provides a reference design for
hardware designers, and a flexible full-featured emulation platform for
DSP software designers.
This chapter includes the following sections:
•Section 1.1, “Product Features”
•Section 1.2, “Operating Modes”
•Section 1.3, “Block Diagram”
•Section 1.4, “Packing List”
•Section 1.5, “Related Components”
1.1 Product Features
The EB402 provides the following features:
•RS-232 and JTAG interfaces for emulation, download, and debug.
•Full-speed execution of DSP programs.
•Full visibility and control of device memory and registers.
•Boot execution from nonvolatile flash memory for stand-alone test
and demonstration.
•On-board flash memory, SBSRAM, and SRAM for external
instruction and data memory.

1-2 Introduction
•External Expansion Interface (EEI) for connecting additional external
memory and peripherals.
•Two serial port interfaces for flexible peripheral configurations.
•Codec Daughterboard(s) that supports up to eight channels of
real-time analog audio I/O.
•Host Processor Interface (HPI) for connecting the EB402 to a host
microprocessor.
1.2 Operating Modes
The EB402 has three operating modes:
•JTAG-Based Emulation
•RS-232-Based Emulation
•Stand-Alone Mode
The development and debug capabilities of JTAG- and RS-232-based
emulators are similar. Both modes provide access to all on-chip
resources. The device emulation unit (DEU) works in conjunction with
code residing in the boot ROM to provide full-speed in-circuit emulation,
and to allow full visibility and control of the device’s memory and registers.
The major differences between JTAG- and RS-232-based emulation are
communication speed, RS-232 stack requirements, and hardware debug
capabilities. JTAG-based emulation offers access to hardware debug
capabilities that are not available with RS-232-based emulation. Refer to
the ZSP™ SDK Software Development Kit User’s Guide for more
information about hardware debug capabilities.
1.2.1 JTAG Mode
The EB402 supports JTAG controllers from these manufacturers:
•Corelis JTAG Controller
•Macraigor Raven Controller
Check the ZSP web site (http://www.zsp.com) for the latest information
about compatible JTAG controllers and software.

Operating Modes 1-3
1.2.1.1 Corelis JTAG Controller
JTAG-based emulation requires an IBM-compatible PC, a Corelis JTAG
controller (PCI or PCMCIA) installed on the PC, a JTAG cable connecting
the PC to the EB402, and the LSI Logic Corporation SDK Software
Development Kit. SDK provides a compiler, assembler, linker, debugger,
and other utilities required to create, simulate, debug and execute
LSI402ZX programs on the EB402.
1.2.1.2 Macraigor Raven JTAG Controller
JTAG-based emulation requires an IBM-compatible PC with a parallel
port, a JTAG cable between the parallel port and connector J5 on the
EB402, and the Green Hills Software ZSP development tools. These
software tools provide a compiler, assembler, linker, debugger, and other
utilities required to create, simulate, debug and execute LSI402ZX
programs on the EB402. The Macraigor Raven JTAG controller provides
a hardware reset from the user interface.
1.2.2 RS-232 Mode
RS-232 mode works with IBM-compatible PCs, and workstations running
Solaris 2.5 and later versions. Using either type of system requires an
RS-232 cable and the ZSP SDK Software Development Kit. An RS-232
cable is included with the EB402 package.
SDK provides GUI and command line interfaces for IBM-compatible PC
systems; a command line interface is provided for Solaris. Check the
ZSP web site (http://www.zsp.com) for the latest information about
compatible computers, operating systems, and development software.
RS-232-based emulation does not support modifying the %smode control
register. Consequently, the emulator can access internal memory, but not
external memory.
Note: SDK 2.1 and earlier versions do not support the LSI402ZX.
1.2.3 Stand-Alone Mode
In stand-alone mode, the EB402 executes code from on-board memory
without a host computer attached to the evaluation board. This mode can
demonstrate the Evaluation Board. For example, you can write a

1-4 Introduction
stand-alone application and run it on the EB402, or use the
demonstration code that is included in the flash ROM. The flash ROM is
preprogrammed with code that supports serial port debug and
illuminates LEDs that indicate a successful self-test.
1.3 Block Diagram
A simplified block diagram of the EB402 is shown in Figure 1.1.
Figure 1.1 EB402 Block Diagram
CLKIN
PLL
Clock
Support
JTAG I/F
HP I/F
Serial Port
Daughter Card I/F
Serial Port
Daughter Card I/F
JTAG
HPI
INT2
Serial Port 0
PIO[1:0]
INT3
Serial Port 1
PIO[3:2]
LSI402ZX
RSTN
PIO[6:4]
INT[1:0]
HOLD/HOLDA
16-Bit
External Expansion I/F
XBUS
SB-SRAM
128 K x 32
Flash RAM
512 K x 16 SRAM 256 K x 16
INT4
RS-232C
Off-Board I/F On-Board Memory Logic
INT4
Access Control
LED
Display
Reset
Logic
UART
(Codec Installed)

Packing List 1-5
1.4 Packing List
The EB402 package includes the following components:
•EB402 PCB.
•BD-EBM-CODEC-1 Codec Daughterboard installed on EB402 PCB.
•Power Supply (input; 120 V or 240 V AC 50/60Hz; output: 9 V DC,
2.5 A) with separate AC power cable.
•RS-232 serial cable (9-pin) for RS-232-based emulation.
•This user’s guide, Document DB15-000143-01.
•EB402 Evaluation Board Getting Started.
Confirm that these items are included with your EB402. If any items are
missing, contact LSI Logic Corporation or your LSI Logic manufacturer’s
representative.
1.5 Related Components
Although the following items are not part of the EB402 package, you may
need these items to use with the EB402.
•ZSP400 Software Development Kit (SDK), SW-ZSP400SDK.
LSI Logic USA distribution contacts: Arrow, Avnet, or Insight.
•Green Hills Software MULTI 2000 Integrated Development
Environment. E-mail contact: [e-mail].
•Corelis PCI JTAG Emulator, BD-PCI1149. LSI Logic USA distribution
contacts: Arrow, Avnet, or Insight.
•Corelis PCMCIA JTAG Emulator, BD-PCMCIA1149. LSI Logic USA
distribution contacts: Arrow, Avnet, or Insight.
•Macraigor Systems RAVEN Parallel Port JTAG Interface. Contact:
http://www.macraigor.com.

1-6 Introduction
The following software components are available on the ZSP web site
(http://www.zsp.com):
•Example code
•Utility software
LSI Logic international distributors are listed in the back of this user’s guide.

EB402 Evaluation Board User’s Guide 2-1
Chapter 2
Installation
This chapter explains how to install the EB402 and verify that it is
functioning correctly. It includes the following sections:
•Section 2.1, “Board Layout”
•Section 2.2, “Preparing to Install the Evaluation Board”
•Section 2.3, “Installing the Evaluation Board”
•Section 2.4, “Power-Up Sequence”
2.1 Board Layout
Figure 2.1 is a simplified drawing of the EB402 PCB. It shows the
location of the components that are referenced in this section.

2-2 Installation
Figure 2.1 Board Layout
2.2 Preparing to Install the Evaluation Board
Prepare to install the EB402 by following this procedure:
1. Using appropriate antistatic measures to prevent electrostatic
discharge (ESD) damage, unpack the PCB and the other components.
2. Verify that you have received all the components. Refer to
Section 1.4, “Packing List” on page 1-5, for the contents of the EB402
package. Inspect the components to verify that none are damaged.
If any components are missing or damaged, contact LSI Logic
Corporation or your LSI Logic manufacturer’s representative.
BD-EBM_CODEC-1 Module J1
PLL OUT
J4
PLL
REF IN
JP1
CLKIN
J6
HPI
JP22
A17
1
1
1
19
20
20
J3
2
1
A
T
E
K
R
51015
16
A18
TP7 TP6
1.8VTP5
13
S2
1
BYP
OPEN JP12
J8
1 EXT A/DJ11
PLLSEL
SPORT0
EXT CNTL
13
JP21
A16
JP20
FPV
JP15
IOGND
TP83.3V
CGND
13
01 1 23
3
3
2
456
JP18
XBOOT
1
3
F
A
JP19
D3-XEN
JP17
D2-F
JP16
D1-A
JP14
D0-SB
JP13
IC1-A
LSB
MSB
LD1
LED1
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LD16
LD2
LSI402ZX
1
122
13 14 15 16 3.3V
LED2
LED3
1.8V SELFTEST
PIO
PIN1-2(0)
PIN2-3(1)
2
SPORT1
OFF
J9
R11
VR1 VR1
S3
ON
JTAG
J7
J5
JP5 JP6 JP7 JP8 JP9 JP10 JP11
U5
4
1
S1
RESET
3
2JP2
JP3
JP4
4
1
1
1
S4
INT 0
R12
J10 1
0
C4
8
1
19
J2
EB402 S/N 134-30
REV 2/2.1
SN:

Installing the Evaluation Board 2-3
3. Place the PCB on a flat, dry surface. Like most electronic devices,
the Evaluation Board should be kept away from strong heat and
electromagnetic interference sources, including electric heaters.
4. Familiarize yourself with the PCB. You need to identify and
manipulate connectors, controls, indicators, and jumpers during the
installation. Figure 2.1 shows the board’s components. Refer to
Chapter 5, Board Layout and Jumper Settings, for additional
information on this subject.
2.3 Installing the Evaluation Board
Refer to the silk screen on the PCB for the location of components
referenced in this section. Refer to Table 5.1 on page 5-3 for additional
information about setting jumpers. To configure and install the EB402,
perform the following tasks:
1. Set the PCBs power switch, S3, to the OFF position.
2. Connect the input of the AC power supply to an AC power outlet. The
EB402 power supply is compatible with 120 V or 60 Hz and
240 V or 50 Hz sources.
3. Connect the power supply’s DC output to the EB402 power jack, J9.
4. Select either RS-232- or JTAG-based emulation. You may not use
both emulation modes simultaneously.
For RS-232-based emulation, use the RS-232 cable supplied with
the EB402 to connect the host PC’s RS-232 port to the DB-9
connector, J10, on the PCB.
For JTAG-based emulation, use a JTAG cable to connect the JTAG
interface on the host PC to the JTAG connector, J7 (Corelis) or
J5 (Macraigor), on the PCB.

2-4 Installation
5. Select the boot device. You may boot from either the on-board
external memory or the on-chip internal memory.
To boot from on-board external memory, install the IBOOT jumper,
JP3. Also, verify that the XBOOT jumper, JP18, is installed. The
position of JP18 determines whether flash memory or asynchronous
SRAM is the boot memory. To select SRAM, use a jumper to connect
pins 2–3 of JP18. To select flash memory, use a jumper to connect
pins 1–2 of JP18.
To boot from the LSI402ZX on-chip boot ROM, remove the jumper
at JP3.
6. Verify that the HALT jumper, JP4, is not installed. Installing JP4
causes the DSP to halt.
7. Verify that the GTN jumper, JP2, is not installed. Installing JP2
disables the LSI402ZX I/O drivers.
8. Select the reference clock. You can choose either the on-board
oscillator or an external clock source.
To select the on-board 10 MHz oscillator for the LSI402ZX reference
clock, use a jumper to connect pins 1–2 of JP1.
To select an external clock for the LSI402ZX reference clock, use a
jumper to connect pins 2–3 of JP1. Connect the external clock to
BNC connector J4.
9. Select the processor clock. You can select either the DSP PLL, or
CLKIN for the processor clock.
To select the output of the LSI402ZX PLL for the processor clock,
install the BYP jumper, JP12.
To bypass the PLL and select CLKIN for the processor clock,
remove JP12.