LSI EB402 User manual

®
l14020.A
EB402 Evaluation Board
USER’S GUIDE
July 2001

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB15-000143-01, First Edition (July 2001)
This document describes Revision 1 and Revision 2 of the LSI Logic Corporation
EB402 Evaluation Board and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and ZSP are trademarks or registered trademarks of
LSI Logic Corporation. Solaris is a trademark of Sun Microsystems, Inc. Windows
95, Windows 98, Windows 2000, and Windows NT are registered trademarks of
Microsoft Corporation. All other brand and product names may be trademarks of
their respective companies.
GL
To receive product literature, visit us at http://www.lsilogic.com. and
http://www.zsp.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html

Preface iii
Preface
This document is the primary reference and user’s guide for Revision 1
and Revision 2 of the EB402 Evaluation Board. Unless otherwise noted,
references to the EB402 apply to Revision 1 and Revision 2 printed
circuit boards (PCBs). LSI Logic incorporated the following changes in
Revision 2 of the EB402 Evaluation Board:
•Added + 9 VDC power to SPORT0 and SPORT1 to increase serial
port versatility.
•Added Macraigor JTAG Interface (J5 reserved on Revision 1).
•Added Diode CR1 to PCB to accommodate Macraigor JTAG Interface.
The EB402 is the evaluation board for LSI402ZX Digital Signal
Processors (DSPs). In this manual, the EB402 Evaluation Board is
referred to as the EB402.
Audience
This document assumes that you are familiar with DSPs and related
support devices. The people who benefit from this book are:
•Engineers and managers who are evaluating the LSI402ZX DSP for
possible use in a system.
•Engineers who are designing the LSI402ZX DSP into a system.

iv Preface
Organization
This document has the following chapters:
•Chapter 1, Introduction, provides an overview of the EB402 and
describes its features.
•Chapter 2, Installation, explains how to install EB402 hardware and
verify its functionality with an RS-232-based or a JTAG-based emulator.
•Chapter 3, Hardware Overview, describes the LSI402ZX DSP signals,
the EB402 external interfaces, and the on-board memory configuration.
•Chapter 4, Operation, explains the EB402 operating modes.
•Chapter 5, Board Layout and Jumper Settings, shows the physical
layout of the EB402, lists jumpers and their default settings, and
provides the pinouts for the PCB interface connectors.
•Appendix A, Schematics, contains the schematics for the EB402
and the BD-EBM-CODEC-1 Codec Daughterboard.
•Appendix B, Bill of Materials, lists the materials used in the EB402
and the BD-EBM-CODEC-1 Codec Daughterboard.
Related Publications
The following documents provide supplemental information:
LSI402ZX Digital Signal Processor User’s Guide, LSI Logic Corporation,
Order No. R14021.B.
ZSP Digital Signal Processor Architecture Technical Manual, LSI Logic
Corporation, Order No. l14036.A.
EB402 Evaluation Board Getting Started, LSI Logic Corporation, Order
No. R14019.A.
ZSP SDK Software Development Kit User’s Guide, LSI Logic
Corporation, Order No. R14013.A.

Preface v
Embedded ZSP Development Guide and associated documents for
MULTI version 3.5, Green Hills Software.
ZSP web site, www.zsp.com.
If you would like further information about components that are not
LSI Logic products, refer to the manufacturers’ information.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Courier typeface (Courier) is used for source code. Courier typeface is
also used for information that is displayed on a terminal monitor.

vi Preface

Contents vii
Contents
Chapter 1 Introduction
1.1 Product Features 1-1
1.2 Operating Modes 1-2
1.2.1 JTAG Mode 1-2
1.2.2 RS-232 Mode 1-3
1.2.3 Stand-Alone Mode 1-3
1.3 Block Diagram 1-4
1.4 Packing List 1-5
1.5 Related Components 1-5
Chapter 2 Installation
2.1 Board Layout 2-1
2.2 Preparing to Install the Evaluation Board 2-2
2.3 Installing the Evaluation Board 2-3
2.4 Power-Up Sequence 2-5
Chapter 3 Hardware Overview
3.1 Clock and Control Signals 3-3
3.1.1 CLKIN (Master Clock Input) 3-3
3.1.2 CLKOUT (DSP Clock Output) 3-3
3.1.3 PLLBYPASS (PLL Bypass) 3-4
3.1.4 PLLSEL[3:0] (PLL Multiplier Select) 3-4
3.1.5 RSTN (Device Reset) 3-5
3.1.6 IBOOT (Memory Map Select) 3-6
3.1.7 INT[4:0] (External Hardware Interrupts), NMI
(Nonmaskable Interrupt) 3-6
3.1.8 HALT (Halt Processor Clock) 3-7
3.2 PIO[7:0] (Programmable I/Os) 3-7

viii Contents
3.2.1 Controlling the Codecs 3-8
3.2.2 Controlling the HPI Mode 3-9
3.2.3 Controlling the External Expansion Interface (EEI) 3-9
3.2.4 Controlling Test and Debug Configurations 3-9
3.3 External Interfaces 3-10
3.3.1 JTAG Interfaces 3-11
3.3.2 RS-232 Interface 3-13
3.3.3 BD-EBM-CODEC-1 Daughterboard 3-14
3.3.4 Host Processor Interface (HPI) 3-18
3.3.5 External Expansion Interface (EEI) 3-19
3.3.6 Discrete LED Display 3-19
3.4 Memory and Memory-Mapped Peripherals 3-19
3.4.1 Internal Memory 3-20
3.4.2 External Memory and Memory-Mapped
Peripherals 3-20
Chapter 4 Operation
4.1 Boot Modes 4-1
4.2 JTAG Emulation 4-2
4.2.1 JTAG Software Tools 4-2
4.2.2 JTAG Hardware Tools 4-3
4.2.3 Installing JTAG Tools 4-4
4.2.4 Using JTAG Tools 4-4
4.3 RS-232-Based Emulation 4-4
4.3.1 Connecting RS-232 Hardware 4-5
4.3.2 Installing SDK and Using the RS-232 Interface 4-5
4.4 Using Stand-Alone Mode 4-6
Chapter 5 Board Layout and Jumper Settings
5.1 EB402 Jumpers 5-2
5.2 External Connectors 5-5
Appendix A Schematics
Appendix B Bill of Materials
Customer Feedback

Contents ix
Figures 1.1 EB402 Block Diagram 1-4
2.1 Board Layout 2-2
3.1 Evaluation Board Block Diagram 3-2
3.2 Corelis JTAG Connector 3-11
3.3 Macraigor JTAG Connector 3-12
3.4 RS-232 Interface 3-13
3.5 Serial Port Interfaces to Codec Daughterboards 3-14
3.6 J3, BD-EBM-CODEC-1 Serial Port Connector 3-15
3.7 EBM CODEC-1 Board Layout 3-17
3.8 External Memory 3-21
4.1 JTAG Emulation Tools 4-4
4.2 RS-232-Based Emulation 4-5
5.1 Evaluation Board Layout 5-2
5.2 J5, Macraigor, JTAG Connector 5-6
5.3 J6, HPI Interface Connector 5-7
5.4 J7, Corelis JTAG Interface Connector 5-7
5.5 J10, RS-232 Interface Connector 5-8
5.6 J3, SPORT0 Daughterboard Interface Connector 5-8
5.7 J2, SPORT1 Daughterboard Interface Connector 5-9
5.8 J11, EEI A/D Connector 5-10
5.9 J8, EEI Control Connector 5-11
A.1 EB402 Schematics (Sheet 1 of 6) A-2
A.2 EB402 Schematics (Sheet 2 of 6) A-3
A.3 EB402 Schematics (Sheet 3 of 6) A-4
A.4 EB402 Schematics (Sheet 4 of 6) A-5
A.5 EB402 Schematics (Sheet 5 of 6) A-6
A.6 EB402 Schematics (Sheet 6 of 6) A-7
A.7 BD-EBM-CODEC-1 Schematic Sheet 1 of 1 A-8
Tables 3.1 PLL Multiplier Selections 3-4
3.2 LSI402ZX External Interrupt Signal Use 3-6
3.3 PIO Signal Use 3-8
3.4 BD-EBM-CODEC-1 Audio Connectors 3-16
3.5 BD-EBM-CODEC-1 Jumper Settings and Descriptions 3-18

x Contents
3.6 Memory Chip Select 3-24
5.1 Evaluation Board Jumper Settings and Descriptions 5-3
5.2 Connector Summary 5-5
B.1 EB402 Bill of Materials B-1
B.2 BD-EBM-CODEC Bill of Materials B-5