Lucid Technologies LP130 User manual

LP130
USER'S MANUAL
2021.07.10
Lucid Technologies
http://www.lucidtechnologies.info
[email protected]
Copyright © 1996-2021 by Lucid Technologies
All rights reserved.
The information in this manual has been carefully checked and is believed to be accurate.
However, Lucid Technologies makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document. Lucid Technologies reserves the
right to make changes in the products contained in this manual in order to improve design or
performance and to supply the best possible product. Lucid Technologies assumes no liability
arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights, nor the rights of others.
© Lucid Technologies 1

CONTENTS
1.0 General Information
1.1 Introduction
1.2 Theory of operation
1.3 Specifications
2.0 Hardware description
3.0 Operation
3.1 Baud rate selection
3.2 Using programming-modules
3.3 Opening Menu
3.3.1 [U]pload driver program
3.3.2 [J]ump to driver at 0100 hex
3.3.3 [D]isplay system memory
3.3.4 [T]est static RAM
3.3.5 [C]alibrate Vpp and Vps
4.0 Designing Programming-modules and writing drivers
4.1 Power control
4.2 Programming-modules
4.3 LP130 device driver software
4.3.1 Memory Utilization
4.3.2 Uploading Drivers
4.3.3 Initial Conditions
4.3.4 LP130 software Toolbox
Appendix A S-Record information
Appendix B RS-232 interface connector
Appendix C HC-06 Bluetooth module
Appendix D Programming-module connector
Appendix E Parts list
Appendix F Assembly checklist
Appendix G Schematics
Appendix H Circuit board image
Appendix I Internet resources
Appendix J Toolbox definitions
Appendix K Toolbox equates
Appendix L Driver template
Appendix M HELLO WORLD code example
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LP130 Users Manual
1.0 General Information
1.1 Introduction
The LP130 programmer was is the latest programmer from Lucid Technologies. It is
hardware compatible with Programming-modules developed for the LP120. Throughout this
manual, your PC will be referred to as the "host system". There is only one software requirement
placed on the host system - it must run a communication program that will do terminal emulation
and ASCII file transfer.
1.2 Theory of operation
The LP130 is an 8-bit microprocessor system with its own RAM, EPROM, and I/O. The
LP130 uses a 68HC11 type CPU. Its operating program starts whenever power is applied. All
communication with the host system is via a serial port, via either a hardwired RS-232 connection
(Appendix B) or wirelessly through the optional HC-06 bluetooth module (Appendix C).
The LP130 tries to meet the various hardware requirements for a wide selection of
programmable devices by concentrating the majority of common resources on the main circuit
board. Address and data lines to the device being programmed must be steady during any
programming pulse. This means the device being programmed can not be connected to the
address or data bus of the microcomputer. Therefore parallel ports are used to set the address and
data for the device being programmed. The programming connector (J3, Appendix D) provides
four byte-wide bidirectional I/O ports, one bidirectional digital control line and an SPI port. The
various programming and supply voltages required by the devices are handled by four switchable
voltages. Two of these voltages are fixed (PMVcc and PMVfw) while two are programmable
(Vpp and Vps).
If a particular device doesn't use all the digital lines or voltages, it is only connected to
those it needs. Getting the required signals to the correct pins for different devices is basically just
point to point wiring and is handled with a very simple adapter. The adapter, referred to as a
"programming- module" (PM), plugs into the "programming connector" (J3) a common 44- pin,
0.156 inch, edge connector.
The LP130's firmware doesn't contain the code to program all the devices the LP130 is
capable of programming. The "driver" software for each device must be uploaded to the LP130
before the device can be programmed. Each driver comes with an annex to this manual that
explains its operation.
1.3 Specifications
Size:
6.75 x 5.75 inches
Power requirement:
+5VDC @ 750mA maximum from external source
+15VDC or unregulated +14 to +16VDC @ 1A from external source
Serial interface:
Universal Asynchronous Receiver Transmitter (UART)
No handshaking
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LP130 Users Manual
8 data bits
No parity
1 stop bit
RS-232
Female, 9-pin, D connector
Selectable baud rates: 4800, 9600, 19200, 38400
Bluetooth
via HC-06 module
9600 baud only
2.0 Hardware description
Page 1 of the schematics (Appendix F) shows the memory and DAC (digital to analog
converter). The 68HC11's memory is composed of the 62256, 27128 and 6264. The firmware is
stored in the 27128 EPROM (U4). The 62256 and 6264 chips (U3 and U5) form 40K of
continuous parallel static RAM. The two 23LC1024 serial RAM chips (U10 and U11) provide
256K bytes to store data that can not be buffered in the 68HC11's 64K address space. The dual
DAC (U12) provides the reference voltages that control Vpp and Vps.
Page 2 shows the 68HC11 microprocessor (U1), address latch (U2) and clock oscillator
(Y1). The 68HC11 addresses a 64K byte-wide address space and provides a UART, a SPI port
and a parallel port - all in one chip. The RS-232 baud rate can be set by the BAUD jumper - see
section 3.1 for details.
Page 3 shows the RS-232 interface (U40 and J40), the connector for the optional HC-06
Bluetooth module (J2, Appendix C) and the 16V8 address decoder (U6). The serial connector is a
DB- 9 type, wired as a DCE device. This mates directly with the 9-pin DTE connectors found on
most computers. The MAX232 contains two RS-232 drivers, two RS-232 receivers, and an on
chip charge-pump. The charge-pump uses the 5 volt supply to generate the bipolar voltages
needed by the RS-232 drivers. The 16V8 decodes the chip selects for the parallel RAM chips and
PIAs; it also multiplexes the UART’s Tx and Rx lines to both the MAX232 and Bluetooth circuits.
Page 4 shows the programmable DC converters and the switching circuitry for the fixed
voltages going to the programming-module. Both converters are powered by the full-wave
rectified voltage (Vfw) from the power supply. Both converters are controlled by voltages from
the MCP4802 dual 8-bit DAC shown on page 1. The DAC's outputs go to the reference inputs of
the 78S40 switching voltage regulators (U13 and U14). The 78S40 will try to make its feedback
signal (pin 6) equal the reference input (pin 9) by changing the output voltage. The circuit around
U13 generates the programming voltage, Vpp. This circuit is designed so that Vpp should be 0.1
times the decimal value sent to DACA. For example, if 210 is sent to DACA, Vpp will go to 21.0
volts. The circuit around U14 generates the supply voltage for the device being programmed, Vps.
This circuit is designed so that Vps should be 0.03 times the decimal value sent to DACB. For
example, if 200 is sent to DACB, VPS will go to 6.0 volts. Vcc is switched to the programming-
module, where it is called PMVcc, by Q1. Vfw is switched to the programming-module, where it
is called PMVfw, by Q2-Q4.
Page 5 shows U7 and U8, the two 68B21 parallel interface adapters (PIAs). The PIA's four
bi-directional parallel ports go to the programming connector (J3, Appendix D). The program-
ming-module for the part being programmed plugs into this connector.
The last page of schematics shows a typical external power supply for use with the LP120
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LP130 Users Manual
or LP130.
3.0 Operation
3.1 Baud rate selection
The BAUD jumper sets the RS-232 baud rate. Available baud rates are, from
bottom to top: 4800, 9600, 19200 and 38400. If there is no BAUD jumper the LP130
will default to 9600 baud. The image at the right shows the correct jumper placement
for 9600 baud.
If the BT (Bluetooth) jumper is present the baud rate will be 9600, regardless
of the BAUD jumper. Because there is only one UART the hard-wired RS-232
connection and the HC-06 Bluetooth module will always operate at the same baud
rate.
3.2 Using programming-modules
Programming-modules should be inserted or removed only when the power to the LP130 is
off! As depicted in the diagram below, the programming-module should be inserted so that the
programming socket faces away from the LP130 circuit board.
If the connector fingers on the programming-module
get dirty or corroded they can be cleaned by rubbing
them with a pencil eraser then washing them with
rubbing alcohol.
3.3 Opening Menu
When power is first applied to the programmer it will send an opening menu, similar to the
one shown below, to the host. Menu selections are made by typing the character in brackets. Any
other character will cause the menu screen to be retransmitted.
LP130 Programmer
Firmware 2021.01.01
© Lucid Technologies 1990-2021
-------- LP130 OPENING MENU --------
[U]pload driver program
[J]ump to driver at 0100 hex
[D]isplay system memory
[T]est parallel static RAM
[C]alibrate Vpp and Vps
?
3.3.1 [U]pload driver program
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LP130 Users Manual
Use this option to upload the driver for the device you want to program. Drivers are stored
as ASCII files in the Motorola S-record format. The upload is accomplished via the ASCII file
transfer facility of whatever terminal/communication program you are using on the host. After
uploading, control should automatically transfer to the driver program and its menu screen should
appear. If the LP130 OPENING MENU reappears, use the [J]ump option to start the driver.
3.3.2 [J]ump to driver at 0100 hex
Use this option to transfer control to 0100 hex which is the address where driver programs
should begin. See section 4.3 for details.
3.3.3 [D]isplay system memory
This option is included as a debugging aid for those users who write their own driver
programs for the LP130. The following submenu will be displayed which allows you to look at
any portion of the LP130 memory space.
Display memory menu
[1] Serial RAM 1
[2] Serial RAM 2
[3] Parallel memory
[X] Exit
?
After selecting the memory you want displayed you will be prompted to enter the starting address
for the display. The Exit option returns control to the main menu.
3.3.4 [T]est static RAM
This test checks all RAM in the 68HC11's address space, from $0040 to $9FFF. Each
memory scan writes the same test byte at every address then goes back and reads every
address to confirm the data is correct. The test byte is incremented with each new scan. An
"*" is printed on the screen every 256 scans. If an error is encountered the test will halt and
the address of the bad byte will be displayed. The test may be stopped at any time by
pressing the ESCape key.
3.3.5 [C]alibrate Vpp and Vps
Use this option to calibrate the DC-to-DC converter circuits. This calibration corrects the
gain of the DC-DC converters so their outputs match the voltages called for by the microprocessor.
4.0 Designing Programming-modules and writing drivers
4.1 Power Control
The four power lines going to the programming connector are all controlled by the LP130.
All four can be switched on and off under program control but only Vpp and Vps are
programmable.
Port A, bit 3, on the 68HC11 is the SWVCC signal. When low, SWVCC switches 5V to
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LP130 Users Manual
the programming-module, PMVcc. PMVcc should be used to power 5V components on the
programming-module other than the device being programmed. The maximum drain on PMVcc is
100 milliamps. When PMVcc is off it is floating.
Port A, bit 4, on the 68HC11 is the SWVFW signal. When low, SWVFW switches the
unregulated full-wave rectified voltage to the programming-module, PMVfw. Since PMVfw is
unregulated, it can vary from 15V to as low as 12V in response to the total load on the power
supply. PMVfw can be used to supplement the other switched voltages on the PM. Limit the
maximum drain on PMVfw to 500 milliamps. When PMVfw is off it is floating.
Schematic page 1 shows the MCP4802, a write-only 8-bit dual voltage output digital-to-
analog converter (DAC). It is the reference for the DC-DC converter circuits that generate Vpp
and Vps. Subroutines are provided in the toolbox for setting both these voltages.
Vpp should be used as the programming pulse voltage. Vpp can be set from 4.5 to 25.5
volts in 0.1 volt steps; settings below 4.5 volts are unreliable. A setting of 0 will effectively turn
off Vpp. The maximum current delivered by the Vpp circuit can be approximated by the equation
below.
Ipp -0.262 + 0.299e(4.8/Vpp) - 21.99e(-Vpp) Amps
Vps should be used as the voltage powering the device in the programming socket, some
devices require different supply voltages for programming and verification. Any other circuitry on
the programming-module that must run on the same voltage can also be powered from Vps. Vps
can be set from 1.8 to 7.5 volts in 0.03 volt steps; settings outside this range are unreliable. A
setting of 0 will effectively turn off Vps. The maximum current delivered by the Vps circuit can be
approximated by the equation below.
For Vps 6.0 V, Ips 0.5 Amp
For Vps > 6.0 V, Ips 0.5 - 0.074(Vps-6) Amp
Because Vpp and Vps are generated by switching circuits their rise-time is on the order of
1 to 4 milliseconds. In most cases the rise time of the voltage to the device being programmed is
not important because the part can be held in reset, or inactive, until the voltage stabilizes.
However, if the rise or fall time is critical, it may be necessary to use a transistor switch on the
PM.
4.2 Programming-Modules
Programming-modules are based on standard 44 contact (0.156" spacing) plug-in prototype
boards, such as:
• Vector 3662-5,
• Lucid Technologies PM-WW.
Odd numbered contacts are on the component side of the board.
Be sure to consider the load you are putting on the ports of the 68B21s when designing
programming-modules.
All programming-modules should have a red LED that lights up whenever PMVcc is on.
This LED indicates power is applied to the programming-module. The device being programmed
should never be removed or inserted when this LED is on.
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Whenever a programmable device is inserted or removed from the programming-module
all signals going to it should be as close to ground potential as possible. PMVfw, PMVcc, Vpp,
and Vps should all be turned off. Some ports on the PIAs have internal pullups so parallel ports
should be changed to outputs and set low. Subroutines to accomplish this are provided as part of
the software toolbox.
Most of you will be using DIP packages and you'll find the necessary ZIF
(Zero-Insertion-Force) sockets are very expensive. If you plan on building several
personality-modules you can sink a lot of money into ZIF sockets. It's more economical to buy one
ZIF in each size you'll need and move it from one programming-module to another. The Aries
(black) ZIF sockets (available in 24, 28, and 40 pins) will plug straight into a machine pin socket.
The 3M/Textool (green) ZIF sockets have larger pins that won't fit a machine pin socket. However,
you can solder a header onto the pins of the textool socket. This makes the socket ride higher, but
it can now be moved from one machine pin socket to another.
4.3 LP130 Device Driver Software
The LP130 supercedes the LP120 which used a 6803 processor. The 68HC11 is source and
object code compatible with the 6803 but LP120 drivers (*.D12) can not be used with the LP130.
There are two reasons for this:
1) The 68HC11's internal registers do not map to the same memory locations as the 6803, and
2) The addresses of the LP130 software toolbox routines do not match those of the LP120.
If the source code for an LP120 driver is updated with the proper 68HC11 registers and toolbox
addresses it can be assembled for the LP130. Drivers for the LP130 should use a ‘D13' extension -
*.D13.
Cross-assemblers and compilers that generates S19 object code files for the MC68HC11
are available and many are available for free on the internet. Appendix H lists some of the many
freeware cross-assemblers and other tools that can be found on the internet.
4.3.1 Memory Utilization
In expanded-multiplexed mode the 68HC11 addresses a full 64K memory space. The table
below shows the memory map for the LP130.
$0000-$003F 68HC11A0 REGISTERS
$0040-$00FF INTERNAL RAM, 68HC11A0
$0100-$7FFF EXTERNAL RAM, 62256
$8000-$9FFF EXTERNAL RAM, 6264
$A000-$A3FF UNUSED
$A400-$A7FF PIA ZERO
$A800-$ABFF PIA ONE
$AC00-$BFFF UNUSED
$C000-$FFFF EXTERNAL EPROM, 27128
Parallel RAM is continuous from $0040 to $9FFF. The top 1K of RAM ($9C00-$9FFF) is
reserved for LP130 stack and system variables, the rest ($0040-$9BFF) is available for your use.
The normal convention for drivers is to use RAM from $0040 to $00FF as variable storage and
'ORG' the executable code at $0100. If you need a large buffer area use the memory above the
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executable code.
The LP130 has two 23LC1024 128Kx8 SPI serial memory chips, providing 256K bytes of
additional storage. Serial RAM 1 is selected when SPIM1 (Port A, bit 6) is low. Similarly, SPIM2
(Port A, bit 7) selects the second serial RAM when it is low. The serial RAM chips are initialized
in sequential access mode. See the 23LC1024 datasheet for details on how to address and access
these memories. Subroutines are provided in the toolbox for sending headers, reading, and writing
to these chips.
4.3.2 Uploading Drivers
Drivers are uploaded to the LP130 using the [U]pload option in the opening menu. Drivers
are uploaded as a Motorola S-record files. As a driver is uploaded, each S- record is checked for
accuracy then stored at the absolute address in the record. Any error will cause the upload to
abort. At the end of a successful upload one of two things will happen:
1) If the driver's S9-record has an address of $0000, control will return to the LP130 main menu.
From the main menu you can start your driver by selecting the [J]ump to $0100 option, assuming
your driver follows the normal conventions.
2) If the S9-record has any address other than zero, it will transfer control to that address.
So, assuming a driver's executable code begins at $0100 and you want it to run as soon as it
uploads, delete the S9- record in the assembler's output file (*.S19) and insert the one shown
below.
S9030000FC *Delete this original S9-record, (address = $0000)
S9030100FB *Insert this S9-record in its place, (address = $0100)
4.3.3 Initial Conditions
Because drivers load from the opening menu, they will always see the following
conditions:
* All interrupts are disabled. The 68HC11's interrupt vectors are in high memory.
These vectors are fixed in the EPROM so drivers can’t use any interrupts.
* The stack is assigned to LP130 reserved RAM.
There is no need to reassign the stack pointer.
* The SCI (Serial Communications Interface) is initialized.
* The SPI (Serial Peripheral Interface) is initialized.
* The 23LC1024 serial RAM chips are in Sequential mode.
* All power (PMVfw, PMVcc, Vpp, Vps) going to the programming-module is off.
* All PIA ports are outputs and set low.
Drivers are transient programs that run in the LP130's RAM. When the driver is done, it should do
a JMP (Jump) to RESET ($C000) which returns control to the firmware in EPROM. The jump to
reset will restore all initial conditions.
4.3.4 LP130 software Toolbox
Many software routines that deal with the LP130 hardware, serial I/O, data conversion and
data display are stored in the 27128 EPROM. Drivers can reduce complexity and size by accessing
these Toolbox routines. See Appendix I for the explanation of the various Toolbox routines and
Appendix J for the equate (EQU) statements that need to be included in the driver source code in
order to access the Toolbox.
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APPENDIX A
S-RECORD INFORMATION
INTRODUCTION
Motorola's S-record format for output modules was devised for the purpose of encoding programs
or data files in a printable (ASCII) format. This allows viewing of the object file with standard
tools and easy file transfer from one computer to another, or between a host and target. An
individual S-record is a single line in a file composed of many S-records.
S-RECORD CONTENT
S-Records are character strings made of several fields which specify the record type, record length,
memory address, data, and checksum. Each byte of binary data is encoded as a 2-character
hexadecimal number: the first ASCII character representing the high-order 4 bits, and the second
the low-order 4 bits of the byte.
The 5 fields which comprise an S-record are:
TYPE - RECORD LENGTH - ADDRESS - CODE/DATA - CHECKSUM
The fields are defined as shown in this table.
Field Characters Content
Type 2 S-record type - S1 or S9
Record length 2 The count of the character pairs in the record, excluding the
type and record length.
Address 4 The 2-byte address at which the data field is to be loaded into
memory.
Data 0-2n From 0 to n bytes of executable code, or memory loadable
data. n is normally $20 (32 decimal) or less.
Checksum 2 The least significant byte of the one's complement of the sum
of the values represented by the pairs of characters making up
the record length, address, and data fields.
Each record may be terminated with a CR/LF/NULL. Additionally, an S-record may have an
initial field to accommodate other data such as line numbers. Accuracy of transmission is ensured
by the record length (byte count) and checksum fields.
S-RECORD TYPES
Eight types of S-records have been defined to accommodate various encoding, transportation, and
decoding needs. Lucid programmers use the 8-bit data types, the S1 and S9:
• S0 A header record contains no program information and is ignored by the LP130.
• S1 A record containing data and the 2-byte address at which the data is to reside.
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