Maxim Integrated MAX2771 Operating and maintenance instructions

General Description
The MAX2771 is a next-generation Global Navigation
Satellite System (GNSS) receiver covering E5/L5, L2,
E6, E1/L1 bands and GPS, GLONASS, Galileo, QZSS,
IRNSS, and BeiDou navigation satellite systems on a
single chip.
Designed on Maxim’s advanced, low-power SiGe BiCMOS
process technology, the MAX2771 offers the highest
performance and integration at a low cost. Incorporated
on the chip is the complete receiver chain, including
a dual-input LNA and mixer, followed by filter, PGA,
and multi-bit ADC, along with a fractional-N frequency
synthesizer, and crystal oscillator. The total cascaded
noise figure of this receiver is as low as 1.4dB.
The MAX2771 completely eliminates the need for exter-
nal IF filters by implementing on-chip monolithic filters
and requires only a few external components to form a
complete, low-cost GNSS RF receiver solution.
The MAX2771 is the most flexible receiver on the
market. The integrated delta-sigma fractional-N frequency
synthesizer allows programming of the IF frequency within
a ±30Hz (fXTAL = 32MHz) accuracy while operating with
any reference or crystal frequencies that are available in
the host system. The ADC outputs CMOS logic levels with
one or two quantized bits for both I and Q channels, or up
to 3 quantized bits for the I channel. The on-chip ADCs
can be bypassed and the analog I and Q signals output
for sampling with external ADCs. An analog monitoring
feature is provided that allows simultaneous output of the
on-chip ADC samples and the I analog signal.
The MAX2771 is packaged in a 5mm x 5mm, 28-pin,
TQFN package with an exposed paddle.
Applications
●Location-Enabled Mobile Handsets
●PNDs (Personal Navigation Devices)
●Telematics (Asset Tracking, Inventory Management)
●Marine/Avionics Navigation
●Software GPS
●Laptops and Netbooks
●Surveying Equipment
●Digital Still Cameras and Camcorders
●Vehicle Tracking and Fleet Management
Ordering Information appears at end of data sheet.
19-100378; Rev 0; 7/18
Benets and Features
●Multi-Constellation Support
• GPS, Galileo, GLONASS, BeiDou, IRNSS, QZSS,
SBAS
●Multiband Support
• L1, L2, L5, E1, E5, E6, B1, B2, B3
●Programmable IF Bandwidths of 2.5MHz, 4.2MHz,
8.7MHz, 16.4MHz, 23.4MHz, 36MHz
• Supports Wide-Band Carriers for Precision
Applications (e.g., GPS L5, Galileo E5)
●Operates in Low IF or Zero IF Mode
• Programmable IF Center Frequency
●Fractional-N Synthesizer with Integrated VCO
Supports Wide Range of Reference Frequencies
●On-Chip LNAs to Support Multiple Bands
●1.4dB Cascaded Noise Figure and 110dB of
Cascaded Gain with Gain Control Range of 59dB
from PGA
●Integrated Crystal Oscillator
●Supply Voltage Range: 2.7V to 3.3V
●28-Pin, RoHS-Compliant, Thin QFN Lead-Free
Package (5mm x 5mm)
Click here for production status of specic part numbers.
MAX2771 Multiband Universal GNSS Receiver
EVALUATION KIT AVAILABLE

Block Diagram
22 26 23 20 27 16 15
2128 5678
19
24
25
21
17
4
3
12
13
11
10
14
18
9
LANIN_HI
LANOUT_HI
VCCCP
I0
VCCRF
LNA LNA
FILTER
SPI
PLL
VCO
90
0
MIXIN_HI
NC
LD
CLKOUT
XTAL
I1
Q0
Q1
VCCADC
SHDN
CSN
CPOUT
VCCVCO
ADC_CLKIN
VCCD
SDATA
SCLK
MIXIN_LO LNAOUT_LO LNAIN_LO VCCIF ANAINOUT ANAIPOUT
ADC
ADC
MAX2771
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│ 2
MAX2771 Multiband Universal GNSS Receiver

General Description ............................................................................ 1
Applications .................................................................................. 1
Benefits and Features .......................................................................... 1
Block Diagram ................................................................................ 2
Absolute Maximum Ratings ...................................................................... 6
Package Information ........................................................................... 6
28 TQFN-EP ................................................................................6
Electrical Characteristics ........................................................................ 6
Typical Operating Characteristics ................................................................ 10
Pin Configuration ............................................................................. 14
Pin Description ............................................................................... 14
Functional Diagrams .......................................................................... 16
Detailed Description........................................................................... 17
Default Register Setting ......................................................................17
Low-Noise Amplifier (LNA) ....................................................................17
Mixer .....................................................................................17
Synthesizer ................................................................................18
IF Filter ...................................................................................18
Programmable Gain Amplifier (PGA) ............................................................19
Automatic Gain Control (AGC) .................................................................19
ADC......................................................................................20
ADC Fractional Clock Divider ..................................................................22
ADC Clock Alignment ........................................................................22
DSP Interface ..............................................................................22
Reference Clock ............................................................................24
Serial Interface .............................................................................25
Register Map ................................................................................ 28
Register Details.............................................................................31
Configuration 1 (0x0) ......................................................................31
Configuration 2 (0x1) ......................................................................33
Configuration 3 (0x2) ......................................................................35
PLL Configuration (0x3) ....................................................................37
PLL Integer Division Ratio (0x4) .............................................................39
PLL Fractional Division Ratio (0x5) ...........................................................40
TABLE OF CONTENTS
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MAX2771 Multiband Universal GNSS Receiver

RESERVED (0x6) ........................................................................41
Clock Configuration 1 (0x7) .................................................................42
Test Mode 1 (0x8) ........................................................................43
Test Mode 2 (0x9) ........................................................................44
Clock Configuration 2 (0xA).................................................................45
Applications Information........................................................................ 46
IF Filter Center Frequency Configuration .........................................................46
Operation for Wideband Signals................................................................46
Determining AGC Gain Setpoint................................................................47
PCB Layout Considerations ...................................................................47
Power-Supply Layout ........................................................................47
Typical Application Circuit ...................................................................... 48
Circuit 1 ...................................................................................48
External Component List .....................................................................49
Ordering Information .......................................................................... 49
Revision History .............................................................................. 50
Figure 1. ADC Quantization Levels for 2 and 3-Bit Cases ............................................. 21
Figure 2. DSP Interface Top Level Connectivity and Control Signals ..................................... 23
Figure 3. Clock Distribution ..................................................................... 24
Figure 4. Register Read Functional Timing ......................................................... 26
Figure 5. Register Write Functional Timing ......................................................... 26
Figure 6. Three-Wire Interface Timing Diagram ..................................................... 27
TABLE OF CONTENTS (CONTINUED)
LIST OF FIGURES
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MAX2771 Multiband Universal GNSS Receiver

Table 1. Required Register Bit Field Values ........................................................ 17
Table 2. Default Register Setting ................................................................. 17
Table 3. LNA Selection ........................................................................ 17
Table 4. Mixer Selection........................................................................ 18
Table 5. IF Filter Mode Selection ................................................................. 18
Table 6. IF Filter Order Selection................................................................. 19
Table 7. IF Filter Bandwidth Selection ............................................................. 19
Table 8. Gain Reference Settings ................................................................ 19
Table 12. Output Data Format ................................................................... 20
Table 9. ADC Output Data Format Settings......................................................... 20
Table 10. IQ Channels Enable Settings ............................................................ 20
Table 11. ADC Output Bits Setting................................................................ 20
Table 13. Frequency of ADC Sampling Clock vs. Reference Clock ...................................... 22
Table 14. Reference Divider Settings.............................................................. 25
Table 15. Serial Interface Timing Requirements ..................................................... 27
Table 16. External Component List ............................................................... 49
LIST OF TABLES
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│ 5
MAX2771 Multiband Universal GNSS Receiver

VCC to GND.........................................................-0.3V to +4.2V
MIXIN_ to GND ....................................................-0.3V to +0.3V
Other Pins to GND (Note 1) ........................-0.3V to VCC + 0.3V
Maximum RF Input Power..............................................+15dBm
Continuous Power Dissipation
(TA= +70°C, derate 27 mW/°C above +70°C.) ........2500mW
Operating Temperature Range..............................-40°C to 85°C
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (Soldering, 10 seconds) .................... +300°C
(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the specified default states. LNA input is driven from
a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to GAININ = 111010
through SPI interface, unless otherwise noted. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are
at VCC = 2.85V and TA= +25°C, unless otherwise noted. (Note 1))
Note 1: Except for LNAIN_HI, LNAIN_LO, MIXIN_HI, MIXIN_LO, XTAL, LNAOUT_HI and LNAOUT_LO
Idle Mode is a trademark of Maxim Integrated Products, Inc.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS
Supply Voltage VCC 2.7 2.85 3.3 V
Supply Current
Default mode, high-band LNA and mixer
input is active (Note 2) 26
mA
Default mode, low-band LNA and mixer input
is active (Note 2) 27
Idle ModeTM, IDLE bit is 1, SHDN = high 5
Shutdown mode, SHDN= low 200 μA
Digital Input Logic-High VIH Measure at the SHDN pin 1.5 V
Digital Input Logic-Low VIL Measure at SHDN pin 0.4 V
Package Code T2855+8
Outline Number 21-0140
Land Pattern Number 90-0023
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package Information
28 TQFN-EP
Electrical Characteristics
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│ 6
MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the specified default states. LNA input is driven from
a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to GAININ = 111010
through SPI interface, unless otherwise noted. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are
at VCC = 2.85V and TA= +25°C, unless otherwise noted. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS/ASCADED RF PERFORMANCE
RF Frequency L1 band 1575.42 MHz
RF Frequency - L2/L5 Band L2/L5 band 1227.6 MHz
Noise Figure High band LNA input active, default mode
(Note 3) 1.4 dB
Noise Figure - L2/L5 Band L2/L5 band (Note 6). Low-band LNA input
active, default mode (Note 3) 1.6 dB
Noise Figure Measured at the high-band mixer input 10.3 dB
Noise Figure - L2/L5 Band L2/L5 band (Note 6). Measured at the
low-band mixer input 10.3 dB
Out-of-Band 3rd-Order Input
Intercept Point
Measured at the high-band mixer input
(Note 4) -9 dBm
Out-of-Band 3rd-Order Input
Intercept Point - L2/L5 Band
L2/L5 band (Note 6). Measured at the
low-band mixer input (Note 4) -9 dBm
In-Band Mixer Input Referred
1dB Compression Point Measured at the high-band mixer input -85 dBm
In-Band Mixer Input Referred
1dB Compression Point –
L2/L5 Band
L2/L5 band (Note 6). Measured at the
low-band mixer input -85 dBm
Mixer Input Return Loss Measured at high-band mixer input 10 dB
Mixer Input Return Loss -
L2/L5 Band Measured at low-band mixer input 8 dB
Image Rejection 25 dB
Image Rejection -
L2/L5 Band L2/L5 band (Note 6) 25 dB
Spurs at High-Band
LNA Input LO leakage -101 dBm
Spurs at Low-Band LNA Input L2/L5 band (Note 6). LO leakage -101 dBm
Spurs at High-Band LNA
Input Reference harmonics leakage -103 dBm
Spurs at Low-Band LNA Input L2/L5 band (Note 6). Reference harmonics
leakage -103 dBm
Maximum Voltage Gain Measured from the high-band mixer input to
the baseband analog output 89 96 104 dB
Maximum Voltage Gain -
L2/L5 Band
L2/L5 band (Note 6). Measured from the
low-band mixer input to the baseband
analog output
89 96 104 dB
Variable Gain Range Measured at high-band mixer input 53 59 dB
Electrical Characteristics (continued)
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MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the specified default states. LNA input is driven from
a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to GAININ = 111010
through SPI interface, unless otherwise noted. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are
at VCC = 2.85V and TA= +25°C, unless otherwise noted. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS/FILTER RESPONSE
Passband Center Frequency
FBW = 000, FCEN = 1011000 (Note 7) 3.9
MHzFBW = 010, FCEN = 1011000 (Note 7) 7.1
FBW = 001, FCEN = 1101001 (Note 7) 7.6
Passband 3dB Bandwidth
FBW = 000 (Note 7) 2.5
MHzFBW = 010 (Note 7) 4.2
FBW = 001 (Note 7) 8.7
Lowpass 3dB Bandwidth
FBW = 011, single-sided BW (Note 7) 11.7
MHzFBW = 111, single-sided BW (Note 7) 8.2
FBW = 100, single-sided BW (Note 7) 18
Stopband Attenuation
3rd-order lter, bandwidth = 2.5MHz,
measured at 4MHz o󰀨set (Note 7) 30
dB
5th-order lter, bandwidth = 2.5MHz,
measured at 4MHz o󰀨set (Note 7) 50
Passband Flatness
FBW = 001, Filter center frequency =
8.9MHz, 5th-order BPF, |response
magnitude at 5.1MHz - response magnitude
at 11.6MHz| (Note 7)
3 dB
AC ELECTRICAL CHARACTERISTICS/HIGH-BAND LNA
Power Gain 18 dB
Noise Figure 0.9 dB
Input IP3 (Note 5) -1.1 dBm
Output Return Loss 10 dB
Input Return Loss
With external matching circuit components
of 5.6nH series inductor and 1.7pF shunt
capacitor.
10 dB
AC ELECTRICAL CHARACTERISTICS/LOW-BAND LNA
Power Gain 18 dB
Noise Figure 0.9 dB
Input IP3 (Note 5) -1.1 dBm
Output Return Loss 10 dB
Input Return Loss
With external matching circuit components
of 8.4nH series inductor and 1.1pF shunt
capacitor.
8 dB
Electrical Characteristics (continued)
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MAX2771 Multiband Universal GNSS Receiver

Note 1: MAX2771 is production tested at TA= 25ºC. User must program the registers to the specified default settings upon
power-up.
Note 2: Default mode of the IC. PLL is an an integer-N mode with fCOMP = fTCXO/16 = 1.023MHz and ICP = 0.5mA. The complex
IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz.
Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3: The LNA output connects to the mixer input without a SAW filter between them.
Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz or
1227.6MHz depending on band. Passive pole at the mixer output is programmed to be 13MHz.
Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from
the GPS center frequency of 1575.42MHz or 1227.6MHz depending on band.
Note 6: Same global conditions except tune LO to 1223.508 MHz which means change PLL integer divider ratio to 1196 and
program LOBAND bit to 1.
Note 7: Filter response measured with PGA gain setting of GAININ = 000100, and mixer pole set to 36 MHz (MIXPOLE = 1).
(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the specified default states. LNA input is driven from
a 50Ω source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to GAININ = 111010
through SPI interface, unless otherwise noted. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are
at VCC = 2.85V and TA= +25°C, unless otherwise noted. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS/FREQUENCY SYNTHESIZER
LO Frequency Range 0.2V < VTUNE < (VCC - 0.25V), LOBAND = 0 1525 1610 MHz
LO Frequency Range—
L2/L5 Band 0.2V < VTUNE < (VCC - 0.25V), LOBAND = 1 1160 1290 MHz
LO Tuning Gain 70 MHz/V
LO Tuning Gain - L2/L5 Band 76 MHz/V
Reference Input Frequency 8 44 MHz
Main Divider Ratio 36 32,767 ─
Reference Divider Ratio 1 1023 ─
Charge-Pump Current ICP = 0 0.5 mA
ICP = 1 1
AC ELECTRICAL CHARACTERISTICS/TXCO INPUT BUFFER/OUTPUT CLOCK BUFFER
Frequency Range Load = 10kΩ||10pF 8 44 MHz
Output High Level With respect to ground, IOH = 10μA
(DC-coupled) 2 V
Output Low Level With respect to ground, IOL = 10μA
(DC-coupled) 0.8 V
Capacitive Slew Current Load = 10KΩ||10pF, fCLKOUT = 44MHz 11 mA
Output Load 10||10 KΩ||pF
Reference Input Level Sine wave 0.5 VP-P
Clock Output Multiply/
Divide Range
x2: max input frequency of 22MHz,
x4: max input frequency of 11MHz /4 x4 ─
AC ELECTRICAL CHARACTERISTICS/ADC
ADC Di󰀨erential Nonlinearity AGC enabled, 3-bit output ±0.1 LSB
ADC Integral Nonlinearity AGC enabled, 3-bit output ±0.1 LSB
Electrical Characteristics (continued)
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│ 9
MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the default power-up states. LNA input is driven from
a 50Ω source. LNA input has specied external matching circuit. All RF measurements are done in the analog output mode with ADC
bypassed. PGA gain is set to GAININ = 111010 except for IF lter response plots in which case it is set to GAININ = 000100. For IF lter
response plots, MIXPOLE = 1. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are at VCC = 2.85V
and TA= +25°C, unless otherwise noted.)
Typical Operating Characteristics
0
0.2
0.4
0.6
0.8
1
1.2
1.4
15
15.5
16
16.5
17
17.5
18
-40 -15 10 35 60 85
HIGH-
BAND LNA NOISE FIGURE (dB)
HIGH-BAND LNA GAIN (dB)
TEMPERATURE(°C)
HIGH-BAND LNA GAIN AND NOISE FIGURE
vs. TEMPERATURE toc01toc01
NOISE FIGURE
GAIN
-60
-50
-40
-30
-20
-10
0
10
20
30
40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
HIGH-BAND LNA |S21| AND |S12| (dB)
FREQUENCY (MHz)
HIGH-BAND LNA |S21| and |S12|
vs. FREQUENCY toc04
|S12|
|S21|
-50
-40
-30
-20
-10
0
11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 22.1 2.2
LOW-
BAND LNA INPUT RETURN LOSS (dB)
FREQUENCY (MHz)
LOW-BAND LNA INPUT RETURN LOSS
vs. FREQUENCY toc07
-30
-25
-20
-15
-10
-5
0
11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 22.1 2.2
HIGH-
BAND LNA OUTPUT RETURN LOSS (dB)
FREQUENCY (MHz)
HIGH-BAND LNA OUTPUT RETURN LOSS
vs. FREQUENCY toc02
0
0.2
0.4
0.6
0.8
1
1.2
1.4
17
17.5
18
18.5
19
19.5
20
-40 -15 10 35 60 85
LOW-
BAND LNA NOISE FIGURE (dB)
LOW-BAND LNA GAIN (dB)
TEMPERATURE(°C)
LOW-BAND LNA GAIN AND NOISE FIGURE
vs. TEMPERATURE toc05
GAIN
NOISE FIGURE
-60
-50
-40
-30
-20
-10
0
10
20
30
40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
LOW-
BAND LNA |S21| and |S12| (dB)
FREQUENCY (MHz)
LOW-BAND LNA |S21| and |S12|
vs. FREQUENCY toc08
|S12|
|S21|
-50
-40
-30
-20
-10
0
11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 22.1 2.2
HIGH-
BAND LNA INPUT RETURN LOSS (dB)
FREQUENCY (MHz)
HIGH-BAND LNA INPUT RETURN LOSS
vs. FREQUENCY toc03
-35
-30
-25
-20
-15
-10
-5
0
11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 22.1 2.2
LOW-
BAND LNA OUTPUT RETURN LOSS (dB)
FREQUENCY (MHz)
LOW-BAND LNA OUTPUT RETURN LOSS
vs. FREQUENCY toc06
Maxim Integrated │ 10
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MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the default power-up states. LNA input is driven from
a 50Ω source. LNA input has specied external matching circuit. All RF measurements are done in the analog output mode with ADC
bypassed. PGA gain is set to GAININ = 111010 except for IF lter response plots in which case it is set to GAININ = 000100. For IF lter
response plots, MIXPOLE = 1. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are at VCC = 2.85V
and TA= +25°C, unless otherwise noted.)
-50
-40
-30
-20
-10
0
10
0 1 2 3 4 5 6 7 8 9 10
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER POLYPHASE FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 000)
toc09
FCEN = 1011000
Typical Operating Characteristics (continued)
-50
-40
-30
-20
-10
0
10
0 1 2 3 4 5 6 7 8 9 10
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER POLYPHASE FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 000)
toc10
FCEN = 1011000
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14 16 18 20
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER POLYPHASE FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 001)
toc13
FCEN = 1101001
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14 16 18 20
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 011)
toc16
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER POLYPHASE FILTER RESPONSE
vs. BASEBAND FREQUENCY (FBW = 010)
toc11
FCEN = 1011000
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14 16 18 20
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER POLYPHASE FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 001)
toc14
FCEN = 1101001
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER POLYPHASE FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 010)
toc12
FCEN = 1011000
-50
-40
-30
-20
-10
0
10
0 2 4 6 8 10 12 14 16 18 20
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 011)
toc15
Maxim Integrated │ 11
www.maximintegrated.com
MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the default power-up states. LNA input is driven from
a 50Ω source. LNA input has specied external matching circuit. All RF measurements are done in the analog output mode with ADC
bypassed. PGA gain is set to GAININ = 111010 except for IF lter response plots in which case it is set to GAININ = 000100. For IF lter
response plots, MIXPOLE = 1. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are at VCC = 2.85V
and TA= +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
-50
-40
-30
-20
-10
0
10
0 3 6 9 12 15
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 111)
toc19
40
50
60
70
80
90
100
110
120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
LOW-BAND CASCADED GAIN (dB)
PGA GAIN CODE (°)
LOW-BAND CASCADED GAIN
vs. PGA GAIN CODE
toc22
TA= +85°C
TA= -40°C
TA= 25°C
-50
-40
-30
-20
-10
0
10
0 3 6 9 12 15
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 111)
toc20
0
0.5
1
1.5
2
2.5
95
100
105
110
115
120
-40 -15 10 35 60 85
HIGH-
BAND NOISE FIGURE (dB)
HIGH-
BAND CASCADED GAIN (dB)
TEMPERATURE (°C)
HIGH-BAND CASCADED GAIN AND NOISE FIGURE
vs. TEMPERATURE toc23
NOISE FIGURE
GAIN
40
50
60
70
80
90
100
110
120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
HIGH-
BAND CASCADED GAIN (dB)
PGA GAIN CODE (°)
HIGH-BAND CASCADED GAIN
vs. PGA GAIN CODE
toc21
TA= +85°C
TA= -40°C
TA= 25°C
0
0.5
1
1.5
2
2.5
95
100
105
110
115
120
-40 -15 10 35 60 85
LOW-
BAND CASCADED NOISE FIGURE (dB)
LOW-
BAND CASCADED GAIN (dB)
TEMPERATURE (°C)
LOW-BAND CASCADED GAIN AND NOISE FIGURE
vs. TEMPERATURE
toc24
NOISE FIGURE
GAIN
-50
-40
-30
-20
-10
0
10
0 3 6 9 12 15 18 21 24 27 30
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
3RD-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 100)
toc17
-50
-40
-30
-20
-10
0
10
0 3 6 9 12 15 18 21 24 27 30
MAGNITUDE (dB)
BASEBAND FREQUENCY (MHz)
5TH-ORDER LOW-PASS FILTER RESPONSE
vs.BASEBAND FREQUENCY (FBW = 100)
toc18
Maxim Integrated │ 12
www.maximintegrated.com
MAX2771 Multiband Universal GNSS Receiver

(MAX2771 EV kit, VCC = 2.7V to 3.3V, TA= -40°C to +85°C. Registers are set to the default power-up states. LNA input is driven from
a 50Ω source. LNA input has specied external matching circuit. All RF measurements are done in the analog output mode with ADC
bypassed. PGA gain is set to GAININ = 111010 except for IF lter response plots in which case it is set to GAININ = 000100. For IF lter
response plots, MIXPOLE = 1. Maximum IF output load is not to exceed 10kΩ||7.5pF on each pin. Typical values are at VCC = 2.85V
and TA= +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
-20
-15
-10
-5
0
11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 22.1 2.2
HIGH-
BAND MIXER INPUT RETURN LOSS (dB)
FREQUENCY (MHz)
HIGH-BAND MIXER INPUT RETURN LOSS
vs. FREQUENCY
toc28
6
8
10
12
14
16
18
0 5 10 15 20 25 30 35 40 45 50 55 60 65
HIGH-
BAND NOISE FIGURE (MIXER INPUT) (dB)
PGA GAIN CODE (°)
HIGH-BAND NOISE FIGURE (MIXER INPUT)
vs. PGA GAIN CODE
toc25
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30 35 40 45 50 55 60 65
LOW-
BAND MIXER INPUT REFERRED GAIN (dB)
PGA GAIN CODE (°)
LOW-BAND MIXER INPUT REFERRED GAIN
vs. PGA GAIN CODE toc29
TA= =85°°C
TA= 25ºC
TA= -40ºC
6
8
10
12
14
16
18
20
0 5 10 15 20 25 30 35 40 45 50 55 60 65
LOW-
BAND NOISE FIGURE (MXER INPUT) (dB)
PGA GAIN CODE (°)
LOW-BAND NOISE FIGURE (MIXER INPUT)
vs. PGA GAIN CODE
toc26
-20
-15
-10
-5
0
0.6 0.7 0.8 0.9 11.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
HIGH-
BAND MIXER INPUT RETURN LOSS (dB)
FREQUENCY (MHz)
LOW-BAND MIXER INPUT RETURN LOSS
vs. FREQUENCY
toc30
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30 35 40 45 50 55 60 65
HIGH-
BAND MIXER INPUT REFERRED GAIN (dB)
PGA GAIN CODE (°)
HIGH-BAND MIXER INPUT REFERRED GAIN
vs. PGA GAIN CODE
toc27
TA= =85ºC
TA= -40ºC
TA= 25ºC
Maxim Integrated │ 13
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MAX2771 Multiband Universal GNSS Receiver

PIN NAME FUNCTION TYPE
1 CPOUT Charge-Pump Output. Connect a PLL loop lter as a shunt C and a shunt combination
of series R and C (see Typical Application Circuit). Analog output
2 VCCCP PLL Charge-Pump Supply Voltage. Bypass to ground with a 100nF capacitor as close
as possible to the pin. Power
3 XTAL XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if a
TCXO is used. Analog input
4 CLKOUT Reference Clock Output. Digital output
5 ADC_CLKIN ADC Clock Input. Optionally, the ADCs can be clocked from the clock input on this pin.
Refer to ADC Clock Alignment section for details. Digital input
6 VCCD Digital Circuitry Supply Voltage. Bypass to ground with a 100nF capacitor as close as
possible to the pin. Power
7SDATA Data Signal of 3-Wire Serial Interface. Digital Input/
Output
8 SCLK Clock Input of 3-Wire Serial Interface. Serial data is clocked in on the rising-edge of
the SCLK and output on the falling-edge of SCLK. Digital Input
9 CSN Chip-Select Input of 3-Wire Serial Interface. Set CSN low to select device.
Set CS high when the SPI transaction is completed. Digital Input
Pin Conguration
21 20 19 18 17 16 15
+
EP
TOP VIEW
MAX2771
N.C. LNAIN_LO LNAIN_HI SHDN LD ANAINOUT ANAIPOUT
VCCRF
LNAOUT_LO
LNAOUT_HI
MIXIN_HI
MIXIN_LO
VCCIF
22
23
24
25
26
27
VCCVCO 28
14
13
12
11
10
9
VCCADC
I1
I0
Q0
Q1
CSN
8 SCLK
1 2 3 4 5 6 7
CPOUT VCCCP
XTAL
CLKOUT
ADC_CLKIN
VCCD
SDATA
*CONNECTED EXPOSED PAD TO GROUND
Pin Description
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│ 14
MAX2771 Multiband Universal GNSS Receiver

PIN NAME FUNCTION TYPE
10 Q1 Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or analog
di󰀨erential voltage output.
Digital or
analog output
11 Q0 Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or analog
di󰀨erential voltage output.
Digital or
analog output
12 I0 I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or analog
di󰀨erential voltage output.
Digital or
analog output
13 I1 I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or analog
di󰀨erential voltage output.
Digital or
analog output
14 VCCADC ADC Supply Voltage. Bypass to ground with a 100nF capacitor as close as
possible to the pin. Power
15 ANAIPOUT
The Analog I+ Channel is Output On This Pin. This is used for the continuous
spectrum monitoring function if the ANAIMON bit is set to 1. If continuous spectrum
monitoring feature is not required, leave unconnected.
Analog output
16 ANAINOUT
The Analog I- Channel is Output On This Pin. This is used for the continuous spectrum
monitoring function if the ANAIMON bit is set to 1. If continuous spectrum monitoring
feature is not required, leave unconnected.
Analog output
17 LD Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked. Digital output
18 SHDN Operation Control Logic Input. A logic-low shuts o󰀨 the entire device. Digital input
19 LNAIN_HI High-Band LNA Input Port. Requires external matching circuit of 5.6nH series
inductor and 1.7pF shunt capacitor. Analog input
20 LNAIN_LO Low-Band LNA Input Port. Requires external matching circuit of 8.4nH series
inductor and 1.1pF shunt capacitor. Analog input
21 NC No Connection. Leave this pin unconnected.
22 VCCRF RF Section Supply Voltage. Bypass to ground with 100nF and 100pF capacitors in
parallel as close as possible to the pin. Power
23 LNAOUT_LO Low-Band LNA Output. The LNA output is internally matched to 50Ω for L2/L5 band. Analog output
24 LNAOUT_HI High-Band LNA Output. The LNA output is internally matched to 50Ω for L1 band. Analog output
25 MIXIN_HI High-Band Mixer Input. The mixer input is internally matched to 50Ω for L1 band. Analog input
26 MIXIN_LO Low-Band Mixer Input. The mixer input is internally matched to 50Ω for L2/L5 band. Analog input
27 VCCIF IF Section Supply Voltage. Bypass to ground with a 100nF capacitor as close as
possible to the pin. Power
28 VCCVCO VCO Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible
to the pin. Power
Pin Description (continued)
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│ 15
MAX2771 Multiband Universal GNSS Receiver

Functional Diagrams
LANIN_HI
LANOUT_HI
LD
I0
LNA LNA
FILTER
SPI
PLL
VCO
90
0
MIXIN_HI
CLKOUT
XTAL
I1
Q0
Q1
CSN
CPOUT
SDATA
SCLK
MIXIN_LO LNAOUT_LO LNAIN_LO
ANAINOUT ANAIPOUT
ADC
ADC
MAX2771
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│ 16
MAX2771 Multiband Universal GNSS Receiver

Detailed Description
Default Register Setting
The registers will contain the reset values specified in the
Registers section of the data sheet upon power-up. It is
necessary for certain bit fields in particular registers to
be programmed with fixed values that are different from
the power-on reset values. These register bit fields and
the required values are given in Table 1. These values
must be programmed whenever the IC is power-cycled.
Note that these bits are described as “Reserved" in the
datasheet. Nevertheless, for these reserved bits alone,
the values indicated must be programmed.
Table 2 includes the default register bit values with the
above specified bits programmed, as in Table 1.
Low-Noise Amplier (LNA)
The MAX2771 integrates two low-noise amplifiers, one for
the L1 band (high band) and the other for the L2/L5 band
(low band). Both inputs require AC coupling capactors.
Bits LNAMODE in the Configuration 1 register control
the modes of the two LNAs. See Table 3. The high-band
LNA input impedance is matched to 50Ω at a frequency
of 1575MHz, providing the specified high-band external
matching circuit is used. The low-band LNA input imped-
ance is matched to 50Ω at a frequency of 1227MHz,
providing the specified low-band external matching circuit
is used.
The output of each LNA is brought out to a separate pin.
The output impedance of the high-band LNA is matched
to 50Ω at frequency of 1575MHz, and the low-band LNA
input impedance is matched to 50Ω at a frequency of
1227MHz.
Mixer
The MAX2771 includes a quadrature mixer to output low-
IF, or zero-IF, I and Q signals. There are two inputs to
the mixer; one for high-band and the other for low-band.
The high-band mixer input impedance is matched to 50Ω
at a frequency of 1575MHz, while the low-band mixer
input impedance is matched to 50Ω at a frequency of
1227MHz. The quadrature mixer requires a low-side LO
injection. The output of the LNA and the input of the mixer
are brought off-chip to facilitate the use of a SAW filter. On
the MAX2771, the RF signal has been made accessible
between the first LNA stage output and mixer input. If
filtering is not desired, these pins can be connected
through a coupling capacitor. However, filtering introduced
at this point has minimal effect on the excellent sensitivity
of the receiver. For example, for typical device parameters,
a SAW filter with 1dB insertion loss would degrade
cascaded NF (and therefore receiver sensitivity) by only
about 0.15dB. While no external filtering is required for
Table 1. Required Register Bit Field
Values
Table 2. Default Register Setting
Table 3. LNA Selection
REGISTER
ADDRESS
BIT
RANGE
BINARY
VALUE
0x0 29:22 11111010
0x9 24:22 011
REGISTER
NAME ADDRESS DEFAULT
Conguration 1 0x0 0xBEA41603
Conguration 2 0x1 0x20550288
Conguration 3 0x2 0x0EAFA1DC
PLL Conguration 0x3 0x698C0008
PLL Integer
Division Ratio 0x4 0x00C00080
PLL Fractional
Division Ratio 0x5 0x08000070
DSP Interface 0x6 0x08000000
Clock
Conguration 1 0x7 0x010061B2
Test Mode 1 0x8 0x01E0F401
Test Mode 2 0x9 0x00C00002
Clock
Conguration 2 0xA 0x010061B0
LNA MODE
(CONFIGURATION 1
REGISTER)
MODE
00 LNA_HI is active
01 LNA_LO is active
10 Both LNA_HI and
LNA_LO are o󰀨
11 RESERVED
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│ 17
MAX2771 Multiband Universal GNSS Receiver

stand-alone applications, coexistence with cellular or WiFi
transmissions in close proximity may require additional
filtering to prevent compressing the receiver front-end.
The mixer is configured for the desired band by the
MIXERMODE[1:0] bits. Refer to Table 4.
Synthesizer
The MAX2771 integrates a 20-bit, sigma-delta, fractional-N
synthesizer allowing the device to tune to a required
LO frequency with an accuracy of approximately ±30Hz
(when fXTAL ≤ 32MHz). The synthesizer includes a 10-bit
reference divider with a divisor range programmable from
1 to 1023, a 15-bit integer portion main divider with a
divisor range programmable from 36 to 32767, and also
a 20-bit fractional portion main divider. The reference
divider is programmable through the RDIV bits in the PLL
Integer Division Ratio register, and can accommodate
reference frequencies from 8MHz to 44MHz. The
reference divider needs to be configured so the Phase
Frequency Detector comparison frequency falls between
0.05MHz and 32MHz. In Integer-N mode, if the integer
division ratio is divisible by 32, setting the PWRSAV bit of
the PLL Configuration Register to 1 will reduce the power
consumed by the PLL.
The PLL loop filter is the only external block of the
synthesizer. A typical PLL filter is the classic C-R-C
network at the charge-pump output. For example, see
the Typical Application Circuit for the recommended loop
filter component values for fCOMP = 1.023MHz and loop
bandwidth = 56KHz, with charge pump current of 0.5mA
and L1 band VCO. To calculate the loop filter component
values for different LO frequencies, please refer to the
Design Resources section of the MAX2771 product page
on the Maxim Integrated website. The desired integer
and fractional divider ratios can be calculated by dividing
the LO frequency (fLO) by fCOMP. fCOMP can be
calculated by dividing the TCXO frequency, fTCXO, by the
PLL reference division ratio, RDIV. For example, let the
TCXO frequency be 20MHz, RDIV be 1, and the nominal
LO frequency be 1575.42MHz. The following method can
be used when calculating divider ratios supporting various
reference and comparison frequencies:
TCXO
COMP
f20MHz
f 20MHz
RDIV 1
= = =
LO
COMP
f1575.42MHz
LO_Frequency_Divider 78.771
f 20MHz
= = =
Integer Divider = 78(d) = 000 0000 0100 1110 (binary)
Fractional Divider = 0.771 x 220 = 808452 (decimal) =
1100 0101 0110 0000 0100
In the fractional mode, the synthesizer should not be
operated with integer division ratios greater than 251.
There are two LO tuning bands provided. These are
referred to as the L1 band and L2/L5 band respectively.
The L1 band is designed for L1 and Commercial Mobile
Satellite Services (CMSS) such as Inmarsat used for
SBAS. The L2/L5 band is for L2 and L5 bands. The selection
of a band is done by programming the LOBAND bit in the
PLL Configuration register. For example, if the desired
LO frequency is 1227.6MHz, since this falls into the L2/
L5 band, set LOBAND = 1. Assuming the same comparison
TCXO frequencies as the previous example, the PLL
divider ratio would be set to 1227.6/20 = 61.38.
Integer Divider = 61(d) = 000 0000 0011 1101 (binary)
Fractional Divider = 0.38 x 220 = 398459 (decimal) = 0110
0001 0100 0111 1011
The LD output provides an indication of the PLL lock
state. Note that the lock detector requires a reference
clock in order to operate.
IF Filter
The IF filter of the receiver can be programmed to be a
low pass filter or a complex bandpass filter by setting the
bit FCENX bit in the Configuration 1 register to either 0
for low pass filter mode or 1 for bandpass filter mode.
See Table 5.
Table 4. Mixer Selection
MIXERMODE
(CONFIGURATION 1
REGISTER)
MODE
00 High-band mixer enabled
01 Low-band mixer enabled
10 Both mixers disabled
11 RESERVED
Table 5. IF Filter Mode Selection
FCENX
(CONFIGURATION 1
REGISTER)
FILTER MODE
0 Low Pass
1 Bandpass
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│ 18
MAX2771 Multiband Universal GNSS Receiver

Also, the IF filter can be configured either as a 3rd-order
Butterworth filter for reduced group delay or a 5th-order
Butterworth filter for steeper out-of-band rejection by
setting the bit F3OR5 either 1 or 0, respectively, in the
Configuration 1 register. See Table 6.
The two-sided 3dB corner bandwidth can be selected
to be 2.5MHz, 4.2MHz, 8.7MHz, 16.4MHz, 23.4MHz, or
36MHz by programming the FBW bits in the Configuration
1 register. See Table 7. When the FCENX bit in the
Configuration 1 register is set to 1, the low-pass filter
becomes a complex bandpass filter and the center
frequency can be programmed with the FCEN bits in
the Configuration 1 register. The IF center frequency is
adjustable in 127 steps with the 7-bit FCEN value. Refer
to the Applications section for information on how to
configure the desired IF filter center frequency. If the
filter is configured as a low-pass filter, the FCEN bits are
ignored and the center frequency of the filter is at 0Hz.
The narrow-band filter settings are designed to pass
the first null-to-first null main lobe of narrowband signals
such as GPS L1 (2.046MHz) or Beidou B1 (4.092MHz).
The 8.7MHz setting is for the GLONASS L1 band. The
16.4MHz setting is for signals having an intermediate
bandwidth greater than the narrow band signals, but
not as wide as the 20.46MHz wide signals; for example,
Galileo E1 (14.3MHz) or Galileo E6 (10.23MHz). The
23.4MHz setting is for the wide-band signals typically hav-
ing main lobe bandwidth of 20.46MHz. For example, GPS
L1 P(Y), modernized GLONASS L3OC, or BeiDou B2.
Finally, the 36MHz setting is designed to allow simultane-
ous reception of two constellations, specifically GPS and
GLONASS in either the L1 or L2 bands. Simultaneous
reception of GPS L1 and GLONASS L1 provides a
greater selection of visible satellites, which in turn allows
faster time to fix and a more accurate navigation solution.
Programmable Gain Amplier (PGA)
The MAX2771 integrates a baseband programmable
gain amplifier that provides typically 59dB of gain control
range. The PGA gain can either be controlled autono-
mously by the MAX2771 using the AGC function, or
be directly controlled by the host through programming
of the GAININ bits in the Configuration 3 register. The
AGCMODE bits in the Configuration 2 register are used
to select the control mode for the PGA gain. The gain can
be adjusted with approximately 1 dB resolution.
Automatic Gain Control (AGC)
The MAX2771 provides a control loop that automatically
programs the PGA gain to provide the ADC with an input
power that optimally fills the converter and establishes
a desired magnitude bit density at its output. The AGC
algorithm operates by counting the number of magnitude
bits over 512 ADC clock cycles and comparing the
magnitude bit count to the reference value provided
through a control word (GAINREF) in the Configuration 2
register. The desired magnitude bit density is expressed
as a value of GAINREF in a decimal format divided by
the counter length of 512. For example, to achieve the
magnitude bit density of 33%, which is optimal for a 2-bit
converter, program GAINREF to 170, since 170/512 =
33%. See Table 8.
Table 6. IF Filter Order Selection
Table 7. IF Filter Bandwidth Selection
Table 8. Gain Reference Settings
F3OR5
(CONFIGURATION 1
REGISTER)
IF FILTER ORDER
05th order
Butterworth
13rd order
Butterworth
FBW
(CONFIGURATION 1
REGISTER)
BANDWIDTH
(DOUBLE-SIDED)
000 2.5MHz
010 4.2MHz
001 8.7MHz
011 (Low-pass mode only) 23.4MHz
111 (Low-pass mode only) 16.4MHz
100 (Low-pass mode only) 36.0MHz
All other settings RESERVED
GAINREF
(CONFIGURATION 2
REGISTER)
MAGNITUDE
BIT DENSITY
REFERENCE
11101010 234
1010100 84
100111010 314
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│ 19
MAX2771 Multiband Universal GNSS Receiver

ADC
The MAX2771 features an on-chip ADC to digitize the
down-converted GNSS signal. The ADC supports the
digital output in three different formats: unsigned binary,
sign and magnitude, or two’s complement format by set-
ting the FORMAT bits in Configuration 2 register. Refer to
Table 9. The sampled output is provided in a 2-bit format
(1-bit magnitude and 1-bit sign) by default, and also can
be configured as 1-bit or 2-bit in both I and Q channels,
or 1-bit, 2-bit, or 3-bit in the I channel only. If only the
I channel is used, the Q channel can be disabled with
the IQEN bits in the Configuration 2 register. See Table
10. MSB bits are output on the I1 or Q1 pins and LSB
bits are output on the I0 or Q0 pins, for I or Q channel,
respectively. In the case of 3-bit output data format, the
MSB is output on I1, the second bit is on I0, and the LSB
is on Q1. The Q ADC must be enabled in 3-bit output data
mode by setting the IQEN bit to 1. The number of bits of
the ADC can be configured through the BITS field in the
Configuration 2 register. See Table 11. Figure 1 illustrates
the ADC quantization levels for 2-bit and 3-bit cases and
also describes the sign/magnitude data mapping. The
variable T = 1 designates the location of the magnitude
threshold for the 2-bit case. Also refer to Table 12. The
maximum ADC sampling rate is 44MHz.
Table 9. ADC Output Data Format Settings
Table 10. IQ Channels Enable Settings
Table 11. ADC Output Bits Setting
Table 12. Output Data Format
FORMAT
(CONFIGURATION 2
REGISTER)
ADC OUTPUT DATA
FORMAT
00 Unsigned Binary
01 Sign and Magnitude
1X Two’s Complement Binary
IQEN
(CONFIGURATION 2
REGISTER)
ENABLED CHANNEL
0 I channel only
1 Both I and Q channels
BITS
(CONFIGURATION 2
REGISTER)
NUMBER OF BITS
IN THE ADC
000 1 bit
010 2 bits
100 3 bits
INTEGER
VALUE
SIGN/MAGNITUDE UNSIGNED BINARY TWO’S COMPLEMENT BINARY
1b 2b 3b 1b 2b 3b 1b 2b 3b
7 0 01 011 111 111 0 01 011
5 0 01 010 1 11 110 0 01 010
3 0 00 001 1 10 101 0 00 001
1 0 00 000 1 10 110 0 00 000
-1 1 10 100 0 01 011 111 111
-3 1 10 101 0 01 010 1 11 110
-5 1 11 110 0 00 001 1 10 101
-7 1 11 111 0 00 000 1 10 100
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│ 20
MAX2771 Multiband Universal GNSS Receiver